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Thats correct. CoolRunner-II devices do not have clamp diodes... Thanks, Mark Eric Smith wrote: > Austin Lesea <austin@xilinx.com> writes: > >>Spartan 3 has clamp diodes that always prevent the voltage on the pin >>from being more than a diode drop above Vcco (or below ground). > > > And CoolRunner-II do not?Article: 75876
I don't have
>access to the Verilog code. I want to take the design, make a small
>change and reconfigure just to get a handle on the flow, etc. Is it
>possible to extract the .bit file from the ISP PROM and generate the
>source code via WebPack tools?
Short version: "No!"
Long version:
It might be possible with a big enough budget. It's far from
practical for a hobby project.
Many (most?) demo boards have lots of info on the web: schematics,
sample code, how-to-get-started memos...
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 75877Hi Eric, Eric Crabill wrote: > Let me ask another question, if you don't mind. Do > you (or anyone reading) know if it's possible to > open files with dynamic file names? By that, I > mean instead of using the string "test.bin" in $fopen > is there a way to form a string with a 2D reg and > then pass that as the file name? I tried playing > around with this, but the simulator I was using at > the time did not like anything but actual strings... I know it can be done in VHDL, but not sure about Verilog sorry. I can dig out the details if you're interested. JohnArticle: 75878
Try this (tested in mti 5.8e):
module wr_bin ();
reg [7:0] data;
reg [10*8:0] fn;
reg [7:0] seq;
integer fd;
integer i, j;
initial begin
for (j = 0; j < 8; j = j + 1) begin
seq = 8'h30 + j;
fn = {"frame", seq, ".tif"};
fd = $fopen(fn, "wb");
for (i = 0; i < 256; i = i + 1) begin
data = i;
if (data == 0) begin
$fwriteb(fd, "%u", data);
$fseek(fd, 1, 0);
end
else
$fwriteb(fd, "%c", data);
end
$fclose(fd);
end
$display("Done");
$finish;
end
HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips
"Eric Crabill" <eric.crabill@xilinx.com> wrote in message
news:419BDA61.4AF0BC09@xilinx.com...
>
> Dude, you rock!!! Since I'm using Modelsim at home
> for my hobby projects, this will work fantastic...
> Now I can write out TIFF files direct from Verilog.
>
> Let me ask another question, if you don't mind. Do
> you (or anyone reading) know if it's possible to
> open files with dynamic file names? By that, I
> mean instead of using the string "test.bin" in $fopen
> is there a way to form a string with a 2D reg and
> then pass that as the file name? I tried playing
> around with this, but the simulator I was using at
> the time did not like anything but actual strings...
>
> My desire is to have a loop, that writes each display
> frame to a separate file, with names like:
>
> frame01.tif
> frame02.tif
> frame03.tif
> frame04.tif
> and so on...
>
> Thanks, I appreciate your help,
> Eric
>
> Jim Wu wrote:
> >
> > > Hi,
> > >
> > > Well, let me know if you figure this one out. I had
> > > a similar issue -- I wanted a Verilog simulation to
> > > write out a TIFF file. I couldn't find a way to write
> > > out a binary file, so wrote out ASCII data values to
> > > text file and then post-processed it into a binary
> > > TIFF file using a small program I wrote in C.
> >
> > The attached code is kind of kludge, but it works, with modelsim 5.8e
> > anyway.
> >
> > HTH,
> > Jim
> > jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> > http://www.geocities.com/jimwu88/chips
> >
> > module wr_bin ();
> >
> > reg [7:0] data;
> >
> > integer fd;
> > integer i;
> >
> > initial begin
> > fd = $fopen("test.bin", "wb");
> >
> > for (i = 0; i < 256; i = i + 1) begin
> > data = i;
> >
> > if (data == 0) begin
> > $fwriteb(fd, "%u", data);
> > $fseek(fd, 1, 0);
> > end
> > else
> > $fwriteb(fd, "%c", data);
> > end
> >
> > $fclose(fd);
> > $display("Done");
> > $finish;
> > end
> >
> > endmodule
Article: 75879
A typo, fn should have been defined as "reg [10*8:1] fn;".
"Jim Wu" <nospam@nospam.com> wrote in message
news:cngs9m$jq2@cliff.xsj.xilinx.com...
> Try this (tested in mti 5.8e):
>
> module wr_bin ();
>
> reg [7:0] data;
> reg [10*8:0] fn;
> reg [7:0] seq;
>
> integer fd;
> integer i, j;
>
> initial begin
>
> for (j = 0; j < 8; j = j + 1) begin
> seq = 8'h30 + j;
> fn = {"frame", seq, ".tif"};
> fd = $fopen(fn, "wb");
> for (i = 0; i < 256; i = i + 1) begin
> data = i;
>
> if (data == 0) begin
> $fwriteb(fd, "%u", data);
> $fseek(fd, 1, 0);
> end
> else
> $fwriteb(fd, "%c", data);
> end
>
>
> $fclose(fd);
> end
>
> $display("Done");
> $finish;
> end
>
> HTH,
> Jim
> jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> http://www.geocities.com/jimwu88/chips
>
> "Eric Crabill" <eric.crabill@xilinx.com> wrote in message
> news:419BDA61.4AF0BC09@xilinx.com...
> >
> > Dude, you rock!!! Since I'm using Modelsim at home
> > for my hobby projects, this will work fantastic...
> > Now I can write out TIFF files direct from Verilog.
> >
> > Let me ask another question, if you don't mind. Do
> > you (or anyone reading) know if it's possible to
> > open files with dynamic file names? By that, I
> > mean instead of using the string "test.bin" in $fopen
> > is there a way to form a string with a 2D reg and
> > then pass that as the file name? I tried playing
> > around with this, but the simulator I was using at
> > the time did not like anything but actual strings...
> >
> > My desire is to have a loop, that writes each display
> > frame to a separate file, with names like:
> >
> > frame01.tif
> > frame02.tif
> > frame03.tif
> > frame04.tif
> > and so on...
> >
> > Thanks, I appreciate your help,
> > Eric
> >
> > Jim Wu wrote:
> > >
> > > > Hi,
> > > >
> > > > Well, let me know if you figure this one out. I had
> > > > a similar issue -- I wanted a Verilog simulation to
> > > > write out a TIFF file. I couldn't find a way to write
> > > > out a binary file, so wrote out ASCII data values to
> > > > text file and then post-processed it into a binary
> > > > TIFF file using a small program I wrote in C.
> > >
> > > The attached code is kind of kludge, but it works, with modelsim 5.8e
> > > anyway.
> > >
> > > HTH,
> > > Jim
> > > jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> > > http://www.geocities.com/jimwu88/chips
> > >
> > > module wr_bin ();
> > >
> > > reg [7:0] data;
> > >
> > > integer fd;
> > > integer i;
> > >
> > > initial begin
> > > fd = $fopen("test.bin", "wb");
> > >
> > > for (i = 0; i < 256; i = i + 1) begin
> > > data = i;
> > >
> > > if (data == 0) begin
> > > $fwriteb(fd, "%u", data);
> > > $fseek(fd, 1, 0);
> > > end
> > > else
> > > $fwriteb(fd, "%c", data);
> > > end
> > >
> > > $fclose(fd);
> > > $display("Done");
> > > $finish;
> > > end
> > >
> > > endmodule
>
>
Article: 75880John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<newscache$qjab7i$zy6$1@lbox.itee.uq.edu.au>... > Allan Herriman wrote: > > > A lot of open cores *aren't* on opencores. Opencollector attempts to > > list them all: > > http://www.opencollector.org/summary.php#Designs > > Ah yes - good catch. > > John Thanks. I see a few cpu cores there available for free. I wonder if selling a 80386sx core will be seen in the near future... should require a rather large fpga.Article: 75881
Hi all,
Just over two years ago, Allan Herriman posted about having synchronous
AND asynchronous resets in Xilinx FPGAs.
http://groups.google.com/groups?hl=en&lr=&threadm=3dc210cc.14049401%40netnews.agilent.com&rnum=11&prev=/groups%3Fq%3Dsynchronous%2Breset%2Bstartup%2Bgroup:comp.arch.fpga%26hl%3Den%26lr%3D%26start%3D10%26sa%3DN
This should be possible if you use the STARTUP block, because that
provides the async reset, leaving each flop's reset input free for the
synchronous reset. The following code should work (+ STARTUP block);
p: process (gsr, clk)
begin
if gsr = '1' then
dout <= (others => '0');
elsif rising_edge(clk) then
if sync_reset = '1' then
dout <= (others => '0');
else
dout <= din;
end if;
end if;
end process;
However, it doesn't do the right thing in Synplify (7.7 etc). The
resulting netlist has FD components, which don't use the reset input at
all. It should generate FDR components instead. Judging by the RTL and
technology views, the compiler has already moved the sync reset to the D
input, so the mapper has no chance once it realises the reset input is
free. In the 2002 thread, Ken McElvain said it should work but
unfortunately, it still doesn't.
So, has anyone found any new workarounds since then?
I'm also open to others ideas. I don't actually need to async reset most
of the design, but it's handy for simulation. I'm aware of Ken Chapman's
techXclusives article about this; however it's a big change in
methodology and I'm not the only designer working on this code.
Some other experiments I tried:
1. Instantiate an ROC component to provide the correct simulation
behaviour, and hope that Synplify realises what it does, removes the
reset net but preserves the initial values (which may not all be zero).
Unfortunately, it doesn't realise that ROC is anything but a blackbox;
Xilinx MAP will rip it out, but I still won't have FDRs.
2. Don't connect the async reset during synth (translate_on/off etc).
This doesn't preserve the initial values though. In one case, we saw
Synplify generate an illegal value for a one-hot encoded enumerated
type, meaning an FSM would start in an illegal state (ouch!).
One known solution for synth is instantiating the FDRs manually, but
then you don't get async resets in simulation. Also this is ugly.
thanks,
Hamish
--
Hamish Moffatt
R&D Engineer
Data Networks Division
Agilent Technologies
Article: 75882"Greg" <gsletch@yahoo.com> wrote in message news:1c163be7.0411171249.6883d5e7@posting.google.com... > First of all, I am a newbie to FPGAs and trying to learn the tools...I > have had coursework in Verilog as it applies to ASICs, etc. I have an > Insight Electronics FPGA Spartan II(100,000 gates) prototype > board...it is a couple of years old. I am using the latest free Xilinx > WebPack tools, etc. > > The board came with the simple counter design already loaded and > ready. You just put power to it and it starts counting. I don't have > access to the Verilog code. I want to take the design, make a small > change and reconfigure just to get a handle on the flow, etc. Is it > possible to extract the .bit file from the ISP PROM and generate the > source code via WebPack tools? If it is a Johnson counter, you will find the code on the Xilinx web site. It's a standard demo they use with most of their kits - FPGAs and CPLDs. I think it is supplied with the WebPack software. Leon LeonArticle: 75883
Hello, I'm wondering if there is any advantage on using a separate regulator for the Vccaux. I already have 2.5V generated on the board by a switching regulator for the multiple DDR chips and for some Vccio of the spartan 3. Now, with the new TI regulator that has 3 regulators in a chip, I can have a separate LDO to power just the Vccaux portion. Is it useful to have it separate ? Thanks, SylvainArticle: 75884
Hi,
see below
Sylvain Munaut wrote:
> Hello,
>
>
> I'm wondering if there is any advantage on using a separate regulator for
> the Vccaux.
>
> I already have 2.5V generated on the board by a switching regulator for
> the multiple DDR chips and for some Vccio of the spartan 3.
Do not use a switching reg for Vccaux, it's noisy and not recomended to
power your DCM (DCM is powered by VCCaux)
> Now, with the
> new TI regulator that has 3 regulators in a chip, I can have a
> separate LDO
> to power just the Vccaux portion. Is it useful to have it separate ?
Yes it is.
Aurash
>
>
>
> Thanks,
>
> Sylvain
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 75885gabor@alacron.com (Gabor Szakacs) writes: > htj@es.lth.se (Hongtu) wrote in message news:<842b837e.0411161440.5f8cc802@posting.google.com>... > > Thank you guys! that is very helpful for me. > > I just wanna ask one last question: After processing the input video > > stream, I got a binary outputs to be displayed in a either a monitor > > or sent back to a computer for real-time supervision, any > > recommendations on how to implement this? > > <snip> > For a local monitor (no computer involved) you can use a RAM/DAC > if you want to get fancy. I've used the ADV7160 / ADV7162 (Analog > Devices) with good results on PC-style analog video monitors. Depending > on image quality and pixel rate there may be much simpler and cheaper > solutions for analog RGB video. > Since it's a binary image to be output, just drive the RGB (and syncs) signals from the FPGA pins via termination resistors (like the Spartan-3 demo board does), no RAMDAC required. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 75886
"Brad Smallridge" <bradsmallridge@dslextreme.com> writes: > I would eventually like to be able to read a BMP file directly into the > ModelSim simulator. I understand now with VHDL the only file you can read > are text files. Is there a way to read in binary data in another way, > perhaps by using Verilog? > > Brad Smallridge > > Personally I use PNG format for grayscale images and PPM for colour, as they can both be text only. The files are big, but the ease with which I can fiddle with them in VHDL compensates! I have a package which allows me to read and write both types of files to/from frame buffers. Just a thought! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 75887
APS has released its new APS-ArmXF FPGA Rapid Development Platform The APS-ArmXF Rapid Development Platform is a highly programmable FPGA and ARM development system used for product development, product implementation, and algorithm testing, just to mention a few. The system includes one ARM-Block and up to 3 XF-Blocks along with software and ARM C, VHDL, and LINUX example code and templates. ARM-BLOCK DESCRIPTION Each ARM-Block contains A 166 MHz 32 bit ARM Processor, with 32 MB of High speed SDRAM, 8MB of on board flash, an IDE Compact Flash interface to allow up to 1GB of storage space. The ARM-Block also contains a large number IO options including SERIAL, SPI, TCP/IP, and USB ports. THE ARM-Block exists as the main support, configuration, and control interface to the large programmable logic XF-Blocks. The ARM-Block interfaces to up to 3 XF-Blocks via a fast 16 bit IO interface bus. Having the ARM processor existing outside of the FPGA blocks leaves 100% of the large FPGAs logic in the XF-Blocks available for user designs. The fact that an ARM processor exists in the system does not preclude the system from being used for embedded processor design in the FPGAs them selves in the XF-Blocks. In fact the XF-Block architecture is set up rather well for FPGA embedded processor design as well as Digital Signal Processing. The ARM-Blocks also can load and run the complete development system for the ARM- Block. The system is shipped with a preloaded LINUX kernel and a complete GNU development tool chain. XF-BLOCK DESCRIPTION Each XF-Block in the system contains a large million gate FPGA, optional 256K by 18 ZBT SRAM, three oscillator sockets, XC9572 CPLD, optional on board programmable Direct Digital Synthesized (DDS) clock, Phase Lock Loop Clock Multiplier chip, and 2 RS232 transceivers, along with up to 166 IO pins. The system's small size makes it great for embedded designs where a powerful programmable logic device is required. Up to three XF-Blocks can be stacked onto one ARM-Block to yield a modular 3 Million gate stack with 3 CPLD arrays, up to 3 separate DDS clock modules up to 3 256K x 18 ZBT SRAM modules (12 Mbits ) up to six separate oscillator sockets, 6 XF-Block serial port transceivers, 3 PLL clock multiplier chips, and up to 498 IO connections. The XF-Block stack's modularity works well for separating design task assignments. Each engineer can design and test his/her portion of the design separately in their own XF-Block The APS-ArmXF web page is http://www.associatedpro.com/armxf.htmlArticle: 75888
Hi! I have spartan-3 xc3s50-vq100 device, handmade parallel cable (JTAG) and Xilinx WebPack 6.2.03i software. I'm trying to configure this device with iMPACT and I have the following problem. When "Initialize Chain" command is chosen iMPACT finds the chip but doesn't recognize it properly. Here is fragment from the log: PROGRESS_START - Starting Operation. Identifying chain contents .... INFO:iMPACT:1588 - '1':The part does not appear to be Xilinx Part. '1': : Manufacturer's ID=Unknown, Version : 15 INFO:iMPACT:501 - '1': Added Device UNKNOWN succesfully. --------------------------------------------------------------------------- ---- --------------------------------------------------------------------------- ---- done. PROGRESS_END - End Operation. After that a dialog window appears with question "Do you have a BSDL or BIT file for this device?" I choose Yes and select file generated before: top.bit. // *** BATCH CMD : deleteDevice -position 1 // *** BATCH CMD : addDevice -position 1 -file "C:\Xilinx\new\nowy\top.bit" '1': Loading file 'C:\Xilinx\new\nowy\top.bit' ... done. INFO:iMPACT:1777 - Reading C:/Xilinx/spartan3/data/xc3s50.bsd... INFO:iMPACT:501 - '1': Added Device xc3s50 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- // *** BATCH CMD : setAttribute -position 1 -attr configFileName -value "C:\Xilinx\new\nowy\top.bit" '1': Loading file 'C:\Xilinx\new\nowy\top.bit' ... done. INFO:iMPACT:501 - '1': Added Device xc3s50 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- When I try to program this device i get messages: Device #1 selected // *** BATCH CMD : Program -p 1 PROGRESS_START - Starting Operation. Validating chain... Boundary-scan chain validated successfully. ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000000000000000 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001010000001101000010010011 PROGRESS_END - End Operation. Elapsed time = 2 sec. And I don't know what else should I do. Regards.Article: 75889
Hi, >> I'm wondering if there is any advantage on using a separate regulator for >> the Vccaux. >> >> I already have 2.5V generated on the board by a switching regulator for >> the multiple DDR chips and for some Vccio of the spartan 3. > > > Do not use a switching reg for Vccaux, it's noisy and not recomended to > power your DCM (DCM is powered by VCCaux) Thanks for the information, just what I needed SylvainArticle: 75890
Hi,
Be aware:
the programming pins are powered from 2.5V (Vccaux) can your "hand
made cable handle" 2.5V levels?
- looks like your TDO (output from the fpga) doesn't get propagated trhu
your hand made cable (or the cable reads 2.5V High level as LOW)
from your impact logfile: INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000000000000000
very likely because of the 2.5v logic levels. You can (should) use the debug mode for the cable in Impact, to debug the cable and/or connections
Aurash
Maciejos wrote:
>Hi!
>I have spartan-3 xc3s50-vq100 device, handmade parallel cable (JTAG) and
>Xilinx WebPack 6.2.03i software. I'm trying to configure this device with
>iMPACT and I have the following problem.
>When "Initialize Chain" command is chosen iMPACT finds the chip but doesn't
>recognize it properly.
>Here is fragment from the log:
>
>PROGRESS_START - Starting Operation.
>Identifying chain contents ....
>INFO:iMPACT:1588 - '1':The part does not appear to be Xilinx Part.
>'1': : Manufacturer's ID=Unknown, Version : 15
>INFO:iMPACT:501 - '1': Added Device UNKNOWN succesfully.
>---------------------------------------------------------------------------
>----
>---------------------------------------------------------------------------
>----
>done.
>PROGRESS_END - End Operation.
>
>After that a dialog window appears with question "Do you have a BSDL or BIT
>file for this device?" I choose Yes and select file generated before:
>top.bit.
>
>// *** BATCH CMD : deleteDevice -position 1
>
>// *** BATCH CMD : addDevice -position 1 -file "C:\Xilinx\new\nowy\top.bit"
>
>'1': Loading file 'C:\Xilinx\new\nowy\top.bit' ...
>
>done.
>
>INFO:iMPACT:1777 -
>
>Reading C:/Xilinx/spartan3/data/xc3s50.bsd...
>
>INFO:iMPACT:501 - '1': Added Device xc3s50 successfully.
>
>----------------------------------------------------------------------
>
>----------------------------------------------------------------------
>
>// *** BATCH CMD : setAttribute -position 1 -attr configFileName -value
>"C:\Xilinx\new\nowy\top.bit"
>
>'1': Loading file 'C:\Xilinx\new\nowy\top.bit' ...
>
>done.
>
>INFO:iMPACT:501 - '1': Added Device xc3s50 successfully.
>
>----------------------------------------------------------------------
>
>----------------------------------------------------------------------
>
>----------------------------------------------------------------------
>
>----------------------------------------------------------------------
>
>
>
>When I try to program this device i get messages:
>
>Device #1 selected
>
>// *** BATCH CMD : Program -p 1
>
>PROGRESS_START - Starting Operation.
>
>Validating chain...
>
>Boundary-scan chain validated successfully.
>
>ERROR:iMPACT:583 - '1': The idcode read from the device does not match the
>idcode in the bsdl File.
>
>INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000000000000000
>
>INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001010000001101000010010011
>
>PROGRESS_END - End Operation.
>
>Elapsed time = 2 sec.
>
>
>
>And I don't know what else should I do.
>
>Regards.
>
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 75891On Thu, 18 Nov 2004 11:32:50 +0100, Sylvain Munaut wrote: > Hello, > > > I'm wondering if there is any advantage on using a separate regulator for > the Vccaux. > > I already have 2.5V generated on the board by a switching regulator for > the multiple DDR chips and for some Vccio of the spartan 3. Now, with the > new TI regulator that has 3 regulators in a chip, I can have a separate LDO > to power just the Vccaux portion. Is it useful to have it separate ? > > > Thanks, > > Sylvain Vccaux powers the DCMs so having a separate power supply should help to reduce clock jitter. If you have a separate supply available I'd use it.Article: 75892
Aurelian Lazarut wrote: > Hi, > Be aware: > the programming pins are powered from 2.5V (Vccaux) can your "hand > made cable handle" 2.5V levels? > - looks like your TDO (output from the fpga) doesn't get propagated > trhu > your hand made cable (or the cable reads 2.5V High level as LOW) > > from your impact logfile: INFO:iMPACT:1578 - '1': Device IDCODE : > 00000000000000000000000000000000 > > very likely because of the 2.5v logic levels. You can (should) use > the debug mode for the cable in Impact, to debug the cable and/or > connections > > Aurash Thanks for quick answer. I've done a test. I had disconnected TDO pin from programmer and Initialize Chain function didn't found any device (ERROR:iMPACT:585 - A problem may exist in the hardware configuration). After connecting TDO back - the same happened what was described in my first post. INFO:iMPACT:1588 - '1':The part does not appear to be Xilinx Part. '1': : Manufacturer's ID=Unknown, Version : 15 INFO:iMPACT:501 - '1': Added Device UNKNOWN succesfully. ...but 'something' was found. I checked the cable before I connected it to my board and high level is 2.5V. I used LM2576-ADJ switching regulators (with 220uH coil and 1000uF cap) to get power supply for my chip (VCCINT 1.23, VCCAUX 2.5, VCCO 3.3). There is quartz generator 80MHz connected to GCLK input. It is driven by 5V but I used the voltage divider (2 resistors) to connect it to xc3s50. But I think that it doesn't matter what is connected to GCLK during configuration. Maybe I'm wrong. Nothing else is connected to xc3s50. Regards.Article: 75893
Maybe update your ISE by 6.3 + sp Laurent www.amontec.com Maciejos wrote: > Hi! > I have spartan-3 xc3s50-vq100 device, handmade parallel cable (JTAG) and > Xilinx WebPack 6.2.03i software. I'm trying to configure this device with > iMPACT and I have the following problem. > When "Initialize Chain" command is chosen iMPACT finds the chip but doesn't > recognize it properly. > Here is fragment from the log: > > PROGRESS_START - Starting Operation. > Identifying chain contents .... > INFO:iMPACT:1588 - '1':The part does not appear to be Xilinx Part. > '1': : Manufacturer's ID=Unknown, Version : 15 > INFO:iMPACT:501 - '1': Added Device UNKNOWN succesfully. > --------------------------------------------------------------------------- > ---- > --------------------------------------------------------------------------- > ---- > done. > PROGRESS_END - End Operation. > > After that a dialog window appears with question "Do you have a BSDL or BIT > file for this device?" I choose Yes and select file generated before: > top.bit. > > // *** BATCH CMD : deleteDevice -position 1 > > // *** BATCH CMD : addDevice -position 1 -file "C:\Xilinx\new\nowy\top.bit" > > '1': Loading file 'C:\Xilinx\new\nowy\top.bit' ... > > done. > > INFO:iMPACT:1777 - > > Reading C:/Xilinx/spartan3/data/xc3s50.bsd... > > INFO:iMPACT:501 - '1': Added Device xc3s50 successfully. > > ---------------------------------------------------------------------- > > ---------------------------------------------------------------------- > > // *** BATCH CMD : setAttribute -position 1 -attr configFileName -value > "C:\Xilinx\new\nowy\top.bit" > > '1': Loading file 'C:\Xilinx\new\nowy\top.bit' ... > > done. > > INFO:iMPACT:501 - '1': Added Device xc3s50 successfully. > > ---------------------------------------------------------------------- > > ---------------------------------------------------------------------- > > ---------------------------------------------------------------------- > > ---------------------------------------------------------------------- > > > > When I try to program this device i get messages: > > Device #1 selected > > // *** BATCH CMD : Program -p 1 > > PROGRESS_START - Starting Operation. > > Validating chain... > > Boundary-scan chain validated successfully. > > ERROR:iMPACT:583 - '1': The idcode read from the device does not match the > idcode in the bsdl File. > > INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000000000000000 > > INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001010000001101000010010011 > > PROGRESS_END - End Operation. > > Elapsed time = 2 sec. > > > > And I don't know what else should I do. > > Regards. > >Article: 75894
Hi again
See below,
Maciejos wrote:
>Aurelian Lazarut wrote:
>
>
>>Hi,
>>Be aware:
>> the programming pins are powered from 2.5V (Vccaux) can your "hand
>>made cable handle" 2.5V levels?
>>- looks like your TDO (output from the fpga) doesn't get propagated
>>trhu
>>your hand made cable (or the cable reads 2.5V High level as LOW)
>>
>>from your impact logfile: INFO:iMPACT:1578 - '1': Device IDCODE :
>>00000000000000000000000000000000
>>
>>very likely because of the 2.5v logic levels. You can (should) use
>>the debug mode for the cable in Impact, to debug the cable and/or
>>connections
>>
>>Aurash
>>
>>
>
>Thanks for quick answer.
>I've done a test. I had disconnected TDO pin from programmer and Initialize
>Chain function didn't found any device (ERROR:iMPACT:585 - A problem may
>exist in the hardware configuration).
>
At this point I guess the cable has a pull up (or the floating input is
seen as 1) and will read all ones (111111) you can check this in Impact
debug cable menu, you can toggle TCK and sample TDO
>After connecting TDO back - the same
>happened what was described in my first post.
>INFO:iMPACT:1588 - '1':The part does not appear to be Xilinx Part.
>'1': : Manufacturer's ID=Unknown, Version : 15
>INFO:iMPACT:501 - '1': Added Device UNKNOWN succesfully.
>
>...but 'something' was found.
>
yes probably some zeroes - again will be a good idea to probe the signal
(using Impact in in debug mode) what you can try is to add a
comparator and compare with 1.25V at the input, and have a pull up at
the output to 3.3Vcc (or your respective cable Vcc)
>
>I checked the cable before I connected it to my board and high level is
>2.5V.
>I used LM2576-ADJ switching regulators (with 220uH coil and 1000uF cap) to
>get power supply for my chip (VCCINT 1.23, VCCAUX 2.5, VCCO 3.3).
>
not a good idea to have a switchig reg on the 2.5V (see a previous post)
>There is quartz generator 80MHz connected to GCLK input. It is driven by 5V
>but I used the voltage divider (2 resistors) to connect it to xc3s50. But I
>think that it doesn't matter what is connected to GCLK during
>configuration. Maybe I'm wrong.
>Nothing else is connected to xc3s50.
>
looks good from the config point of view, but your issue is with the
jtag cable unable to comunicate with the part, after you 'll fix this we
can talk about configuration.
>
>Regards.
>
>
>
If you are using the PIII cable schematics from Xilinx website, be aware
of the 3.3V supply (or 5V) - this cable as it is,
is not directly compatible with cmos 2.5V levels you need to modify it
as I mentioned above.
If Impact recognise your cable (assuming PIII cable) doesn't mean that
is conecting with the JTAG tap - it means that that the loopback
conections on some pins on the paralell port are recognised - thats all.
(your cable has some conections directly on the connector and more, it
sense the VCC cable power on a pin)
Aurash
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 75895
Hamish Moffatt wrote:
> Just over two years ago, Allan Herriman posted about having synchronous
> AND asynchronous resets in Xilinx FPGAs.
> http://groups.google.com/groups?hl=en&lr=&threadm=3dc210cc.14049401%40netnews.agilent.com&rnum=11&prev=/groups%3Fq%3Dsynchronous%2Breset%2Bstartup%2Bgroup:comp.arch.fpga%26hl%3Den%26lr%3D%26start%3D10%26sa%3DN
>
> So, has anyone found any new workarounds since then?
I still like Alan Fitch's recomendation in the thread above.
Don't use the gsr.
A real reset signal allows for clean, portable code
for synthesis and simulation.
-- Mike Treseler
Article: 75896Aurelian Lazarut wrote: > Hi again > See below, > > Maciejos wrote: > >> Aurelian Lazarut wrote: >> >> [cut] Thanks again, I'll focus on my cable and will try to find some docs on debugging. Regards.Article: 75897
All, A separate power supply for Vccaux which powers the DCM delay lines, IO predrivers, and some bias circuits is a good idea to reduce system jitter. Switching regulators are just fine to use in this application. As long as there is no more than a 10 mV droop in a 1 ms period (that would be a really slow switcher -- 1 KHz????). Variations of hundreds of mV at a fast rate are smoothed out by the DCM's filtering (typical of a switcher). It is a sudden droop followed by a slow recovery that affects the DCM, as it can not track fast enough to correct for the push out in delay of the delay lines. This primarily affects the falling edge of the clock coming out, and the Clock 2X output, and Clock DV output (which all use falling edges to synthesize their signals). Austin (who was on the DCM design team for V2, V2P, S3, and V4, and did the subsequent verification and characterization) Sylvain Munaut wrote: > Hello, > > > I'm wondering if there is any advantage on using a separate regulator for > the Vccaux. > > I already have 2.5V generated on the board by a switching regulator for > the multiple DDR chips and for some Vccio of the spartan 3. Now, with the > new TI regulator that has 3 regulators in a chip, I can have a separate LDO > to power just the Vccaux portion. Is it useful to have it separate ? > > > Thanks, > > SylvainArticle: 75898
I have a PCI core that when i implement in my fpga I don't obtain tsu<7n and tco<11ns. What happen ????? What it will not work???Article: 75899
Hi, Jim posted some stuff that looks like it will solve my problem. I'm going to work on my TIFF writer over the weekend and when I'm done (and if it works...) I will post it here. Thanks, Eric John Williams wrote: > > Hi Eric, > > Eric Crabill wrote: > > > Let me ask another question, if you don't mind. Do > > you (or anyone reading) know if it's possible to > > open files with dynamic file names? By that, I > > mean instead of using the string "test.bin" in $fopen > > is there a way to form a string with a 2D reg and > > then pass that as the file name? I tried playing > > around with this, but the simulator I was using at > > the time did not like anything but actual strings... > > I know it can be done in VHDL, but not sure about Verilog sorry. > > I can dig out the details if you're interested. > > John
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