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Messages from 78025

Article: 78025
Subject: Re: Comparison of LEON2, Microblaze and Openrisc processors
From: Luc <lb.edc@pandora.be>
Date: Sun, 23 Jan 2005 10:41:21 GMT
Links: << >>  << T >>  << A >>
In any case, you would expect that the MicroBlaze would perform better
on a Xilinx device. Can one of the Xilinx Apps Guys comment why an
open core CPU has a better performance than MicroBlaze?

Thanks,

Luc

On 19 Jan 2005 02:29:02 -0800, "jiri_gaisler" <jiri@gaisler.com>
wrote:

>A master thesis comparing the LEON2, Microblaze and Openrisc-1200
>processors has been carried out by two students from the Chalmers
>University in Sweden. The final report is now available online at:
>
>http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf
>.
>
>Jiri Gaisler
>
>Gaisler Research


Article: 78026
Subject: Re: Xilinx: xst internal error
From: "jiri_gaisler" <jiri@gaisler.com>
Date: 23 Jan 2005 03:21:52 -0800
Links: << >>  << T >>  << A >>
This is a typicall message that occurs when XST hits some code it could
not synthesize. Make sure you are running the latest version (6.3.02i),
as
this version is somewhat less error-prone. If that does not help, then
remove module by module from your design to isolate which part of
the code XST doesn't like.

Jiri.


Article: 78027
Subject: What's difference of low/high level driver in Xilinx MicroBlaze?
From: "AdamS" <sutongqi@gmail.com>
Date: 23 Jan 2005 04:28:02 -0800
Links: << >>  << T >>  << A >>
I'm a newbie to MicroBlaze

in the drivers guide, almost all the drivers have low level version and
high level version, what's the difference?? just the style??

I just found that low level are more likely to asm.
does any pdf tells? or can any one tells me?

and by the way, how to use an interrupt handle in C file? does any one
has example? thx!


Article: 78028
Subject: Re: Queries regarding PCI with Spartan3
From: Ben Popoola <ben.popoola@REMOVE.recontech.co.uk>
Date: Sun, 23 Jan 2005 14:48:43 GMT
Links: << >>  << T >>  << A >>
Sylvain Munaut wrote:
> Hi
> 
> 
>> i have been designing a pci target using spartan3 for some time.
>> i m a new comer to this field and i have got some queries regarding
>> the fpga configuration and its voltage requirements -
> 
> 
>> the motherboard that i m going to use, has 5V connector for sure.
>> so i suppose the i/o s are 5V. now the spartan3 specifies its
>> VCCO as 3.3Vmax. can this configuration of 5V pci and 3V spartan3,
>> work reliably? are there any added precautions to be observed?


As you probably know, PCI cards support 3 different formats, 3v, 5v and 
both 3.3v and 5v. It depends on the keying of your card. If you want to 
use the spartan 3 FPGA in a 3.3V configuration only, you should design a 
3v PCI card. This is determined by the keying of the card.

Note: Many of the newer computers can ONLY accept 3.3V PCI or 
UniversalPCI cards.

Hope this helps
Ben

Article: 78029
Subject: Don't touch in altera maxplus 2
From: "Jezwold" <edad3000@yahoo.co.uk>
Date: 23 Jan 2005 07:03:21 -0800
Links: << >>  << T >>  << A >>
Simple question..
Is there anyway to set the altera maxplus2 synthesis tool to preserve a
static hazard which has been deliberatly introduced?I cannot use a very
high frequency clock but I do want a very short but not necceserily
accurate output pulse using an xor and a string of LCELLs


Article: 78030
Subject: Re: Microscope examination of a PLD
From: "Jezwold" <edad3000@yahoo.co.uk>
Date: 23 Jan 2005 07:07:58 -0800
Links: << >>  << T >>  << A >>
Tradationally people use fuming nitric acid to remove the
encapsulation.I wouldnt recomment it though without some serious
protection as fuming nitric acid is highly toxic and will strip flesh
to the bone in seconds.


Article: 78031
Subject: Re: Master's Project
From: John McBride <rp.costellomacbride@ntlworld.ie>
Date: Sun, 23 Jan 2005 15:41:39 GMT
Links: << >>  << T >>  << A >>
Lois wrote:
> Hi all,
> 
> I'm seeking your knowledge on some "attemptable" Master Project for a Computer Engineering student. I have done some courses on Digital Design, Verilog, Computer Architecture and Microprocessor Design. I'll love to try my hands on FPGA but I have no idea where to start. I've checked Xilinx site but had difficulty focusing on varieties of choices. I need some ideas on project that can be done in 4-5 months' timeframe, with next to none budgetry, not to mention skill and graduate level req...
> 
> thanks, lois

How about putting together a RISC processor, and as an extension 
demonstrate the effect of pipelining on throughput.

Choose a simple architecture:

say A and B reg feeding into an ALU which has only a few opcodes (well 
preferrably 2,4,8 or 16 opcodes), the ALU feeds onto bus.  Have a simple 
memory interface and at the heart a state machine, which you code up 
behaviourally perhaps.

If you want the FPGA slant look up on Xilinx.com the picoblaze 
processor, written by Ken Chapman, also known as KCPSM (officially K 
constant programmable state machine, but in the KC prob stands for Ken 
Chapman).  Compare your processor with Picoblaze in terms of:
1)area
2)throughput
3)power
4)... think of more criteria

I think there are plenty of angles here.  And your background in 
computer architecture is a good foundation.

-- 
+---------------+
|John McBride   |
|Dublin, Ireland|
|EEE Student@QUB|
+---------------+

Article: 78032
Subject: ModelSim & Constant
From: "Alexis GABIN" <alexis.gabin@gmail.com>
Date: Sun, 23 Jan 2005 17:13:15 +0100
Links: << >>  << T >>  << A >>
Hi,

I want to know if it is possible to watch a constant in the Modelsim 
waveform viewer because I tried to make a model of ROM memory with an array 
of std_logic_vector but when I adress the array it don't give me the right 
value (it seem to choose the first or the final one). So I would like to 
verify if Modelsim put the right value in the memory
the declaration of the memory look like this:

--declaration of a memory subtype
type TYPE_RAM is array (512 downto 0) of
    std_logic_vector(7 downto 0);
--declaration of the memory and his contents
constant ram1: TYPE_RAM :=
(
std_logic_vector(to_unsigned(10#1#,8)),
std_logic_vector(to_unsigned(10#2#,8)),
std_logic_vector(to_unsigned(10#3#,8)),
std_logic_vector(to_unsigned(10#0#,8)),
others => ("11111111")

);

--read at the adress wanted
data_out <= ram1(to_integer(unsigned(adress_ram)));

and when i simulate this i got the value of data_out= "11111111" for all 
value of adress_ram
and i would like to verify the contents of ram1.
How could I see it with modelsim??

Thanks.

Alexis 



Article: 78033
Subject: Re: Master's Project
From: "Jan Gray" <jsgray@acm.org>
Date: Sun, 23 Jan 2005 16:33:22 GMT
Links: << >>  << T >>  << A >>
> How about putting together a RISC processor, and as an extension 
> demonstrate the effect of pipelining on throughput.

That reminds me.  Lois might find inspiration in the last two sections of 
"Hands On Computer Architecture: Teaching Processor and Integrated Systems 
Design with FPGAs" [http://fpgacpu.org/papers/isca00-wcae-paper.pdf].

Jan Gray



Article: 78034
Subject: Re: Microscope examination of a PLD
From: Captain Rick <ME@127.0.0.1>
Date: Sun, 23 Jan 2005 17:16:55 +0000
Links: << >>  << T >>  << A >>
On 23 Jan 2005 02:26:32 -0800, "logjam" <grant@cmosxray.com> wrote:

>Is there a substance that will break down the IC  potting material but
>not the electronics?  I noticed that the back of the silicon was coated
>with metal.  Next I might try comming in from the back, carving around
>the back plane, and lifting the guy out.  Forget that x-ray stuff.  My
>in-head math was off by a few decimal places.  ;)

Try searching Google - fuming nitric acid is commonly used I believe.
Be careful with it though...

Article: 78035
Subject: Re: What's difference of low/high level driver in Xilinx MicroBlaze?
From: Dan Henry <usenet@danlhenry.com>
Date: Sun, 23 Jan 2005 10:39:10 -0700
Links: << >>  << T >>  << A >>
"AdamS" <sutongqi@gmail.com> wrote:

>I'm a newbie to MicroBlaze
>
>in the drivers guide, almost all the drivers have low level version and
>high level version, what's the difference?? just the style??

Not just style.  Look at the driver source code to see the difference.
The low-level drivers are what one would use in a simple design that
lacks an O/S.  The high-level drivers support instances, buffers,
etc., and appear be what one would hook into an O/S.  The high-level
drivers use the low-level drivers.

--
Dan Henry

Article: 78036
Subject: Re: Google citation top 10 for FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Sun, 23 Jan 2005 17:39:32 GMT
Links: << >>  << T >>  << A >>
"Tim" <tim@rockylogic.com.nooospam.com> wrote in
news:csv7ve$586$1$8302bc10@news.demon.co.uk: 

> Herewith the current top 10 papers in citation order,
> as indexed on Google scholar search.  Any suggestions
> for a more authoritative list of key papers?

What are you looking for?  Just general papers on FPGAs?  Just typing 
"FPGA" into Google scholar search isn't going to get you that if the list 
below is an example of the result.  Only item #6 looks relevant.

You should try the general-interest journals for articles on FPGAs and 
then trace the references from them.  I would try IEEE Spectrum, Design & 
Test, and Micro for starters.  Scientific American also had an article on 
Reconfigurable Computing using FPGAs a few years ago.  Check the 
references in these articles and that will lead you to additional papers 
concerning FPGAs in general.

> 
> Good to see a c.a.f. regular at number 2.  And having
> a 4-letter surname seems to help, though for #3
> Alberto must have enjoyed the contrast with his
> co-author's name length ;-)
> 
> -------------------------------------
> 1. FlowMap: An Optimal Technology Mapping Algorithm for Delay
> Optimization in Lookup-Table Based FPGA. J Cong, Y Ding
> 
> 2. VPR: A New Packing, Placement and Routing Tool for FPGA Research. V
> Betz, J Rose
> 
> 3. Defining platform-based design. A Sangiovanni-Vincentelli, F An
> 
> 4. OneChip: An FPGA Processor with Reconfigurable Logic. RD Wittig, P
> Chow 
> 
> 5. A Time-Multiplexed FPGA. S Trimberger, D Carberry, A Johnson, J
> Wong 
> 
> 6. FPGA Technology. SM Trimberger
> 
> 7. NAPA C: Compiling for a Hybrid RISC/FPGA Architecture. MB Gokhale,
> JM Stone 
> 
> 8. DAG-Map: Graph-Based FPGA Technology Mapping for Delay
> Optimization. KC Chen, J Cong, Y Ding, AB Kahng, P Trajmar
> 
> 9. Virtual Wires: Overcoming pin limitations in FPGA-based logic
> emulation. J Babb, R Tessier, A Agarwal
> 
> 10. On area/depth trade-off in LUT-based FPGA technology mapping. J
> Cong, Y Ding 
> 
> 
> 



-- 
----------------------------------------------------------------
Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com


Article: 78037
Subject: Re: Altera HardCopy and SEUs
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Sun, 23 Jan 2005 13:32:24 -0500
Links: << >>  << T >>  << A >>
Hi Roger,

> Is the die shrink that's mentioned with HardCopy devices by virtue of the
> configuration cells being removed? I presume the feature size of the logic
> remains the same though so the characteristics of the logic are unchanged?
> Is the speed up by virtue of the logic now being hardwired?

Programmable routing (comprising multiplexors, buffers, and configuration
SRAMs) is replaced by traditional ASIC routing (buffers + wires only).  This
is the primary source of the area reduction.  Speed comes from the routing
being hardwired (vs. switched via multiplexors) as well from the reduction
in area and some other changes.  The main logic of the device and especially
items such as the RAMs, IOs, and PLLs are the same as the FPGA, so you get
the same behaviour.

As for your second question (separate post), I don't know what the NRE is
for HardCopy.  I don't see $$$ values in my job with Altera, except on my
paycheque :-).  You should contact an Altera sales rep for pricing
information.

- Paul



Article: 78038
Subject: Re: Google citation top 10 for FPGA
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Sun, 23 Jan 2005 18:33:01 -0000
Links: << >>  << T >>  << A >>
"Dave Vanden Bout" wrote
> "Tim" wrote
>
>> Herewith the current top 10 papers in citation order,
>> as indexed on Google scholar search.  Any suggestions
>> for a more authoritative list of key papers?
>
> What are you looking for?  Just general papers on FPGAs?  Just typing
> "FPGA" into Google scholar search isn't going to get you that if the list
> below is an example of the result.  Only item #6 looks relevant.
>
> You should try the general-interest journals for articles on FPGAs and
> then trace the references from them.  I would try IEEE Spectrum, Design &
> Test, and Micro for starters.  Scientific American also had an article on
> Reconfigurable Computing using FPGAs a few years ago.  Check the
> references in these articles and that will lead you to additional papers
> concerning FPGAs in general.

Thanks.  Like most of the people here, I'm interested in
technology, implementation, and applications.  I can make
a stab at following my specialities, but sometimes one
just keeps one's nose too close to the grindstone and
misses key developments.  Especially if conferences aren't
attended regularly.

I wondered whether there is a list of papers the "well
informed amateur" should have read. 



Article: 78039
Subject: Re: Queries regarding PCI with Spartan3
From: "Shreyas Kulkarni" <shyran@gmail.com>
Date: 23 Jan 2005 11:05:13 -0800
Links: << >>  << T >>  << A >>
that's right. but if ur motherboard is having 5v pci slots, then a 3.3v
key will not fit into it.

my board has a 5v one, yet i want to use spartan3. hence the bus switch
- SN74CBTD16211. as Sylvain has mentioned, this ic converts 5v logic
level to 3.3v which are perfect for spartan3.

regards,
Shreyas


Article: 78040
Subject: Re: ModelSim & Constant
From: Elder Costa <elder.costa@terra.com.br>
Date: Sun, 23 Jan 2005 17:14:24 -0200
Links: << >>  << T >>  << A >>
Alexis GABIN wrote:

> Hi,
> 
> I want to know if it is possible to watch a constant in the Modelsim 
> waveform viewer because I tried to make a model of ROM memory with an array 
> of std_logic_vector but when I adress the array it don't give me the right 
> value (it seem to choose the first or the final one). So I would like to 
> verify if Modelsim put the right value in the memory
> the declaration of the memory look like this:
> 
> --declaration of a memory subtype
> type TYPE_RAM is array (512 downto 0) of
                           ^^^^^^^^^^^^^
I dare to say for arrays of any type one will mostly want to declare 0 
to 2**N-1 (in your case, 0 to 511). I was having the very same problem a 
few weeks ago just because of that. I also thed to automaticaly type 
downto when coding arrays but in this particular category the outcome is 
clearly not what one wants though it's sintaticaly correct.

HTH.

Elder.




Article: 78041
Subject: Re: Google citation top 10 for FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Sun, 23 Jan 2005 20:37:34 GMT
Links: << >>  << T >>  << A >>
"Tim" <tim@rockylogic.com.nooospam.com> wrote in
news:ct0qlf$gm4$1$8302bc10@news.demon.co.uk: 

> "Dave Vanden Bout" wrote
>> "Tim" wrote
>>
>>> Herewith the current top 10 papers in citation order,
>>> as indexed on Google scholar search.  Any suggestions
>>> for a more authoritative list of key papers?
>>
>> What are you looking for?  Just general papers on FPGAs?  Just typing
>> "FPGA" into Google scholar search isn't going to get you that if the
>> list below is an example of the result.  Only item #6 looks relevant.
>>
>> You should try the general-interest journals for articles on FPGAs
>> and then trace the references from them.  I would try IEEE Spectrum,
>> Design & Test, and Micro for starters.  Scientific American also had
>> an article on Reconfigurable Computing using FPGAs a few years ago. 
>> Check the references in these articles and that will lead you to
>> additional papers concerning FPGAs in general.
> 
> Thanks.  Like most of the people here, I'm interested in
> technology, implementation, and applications.  I can make
> a stab at following my specialities, but sometimes one
> just keeps one's nose too close to the grindstone and
> misses key developments.  Especially if conferences aren't
> attended regularly.

You might try reading the proceedings for an FPGA-centered conference 
like FCCM.  Or keep abreast of the announcements on the Actel, Altera, 
Lattice, Xilinx websites.  It depends upon what your definition of a "key 
development" is.

> 
> I wondered whether there is a list of papers the "well
> informed amateur" should have read. 

Look at the first few paragraphs of several academic paper on FPGAs.  
They will reference what they (and the reviewers) consider key papers on 
FPGAs in a terse summary of the field so they can quickly get on with 
describing their own research.  These references may be the list you 
want.  A place to find these references online is CiteSeer 
(http://citeseer.ist.psu.edu).



-- 
----------------------------------------------------------------
Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com


Article: 78042
Subject: Re: ModelSim & Constant
From: "kcl" <kclo4@free.fr>
Date: Sun, 23 Jan 2005 21:38:16 +0100
Links: << >>  << T >>  << A >>
Argh!!

You are right Elder, how stupid I am,
baka baka baka!!
lol
moreover I took exemple from an old file I have done during my last 
internship and in this file I used 0 to 2xx too
Thank You for correcting my error.

Alexis

"Elder Costa" <elder.costa@terra.com.br> a écrit dans le message de news: 
35iba7F4npp6qU1@individual.net...
> Alexis GABIN wrote:
>
>> Hi,
>>
>> I want to know if it is possible to watch a constant in the Modelsim 
>> waveform viewer because I tried to make a model of ROM memory with an 
>> array of std_logic_vector but when I adress the array it don't give me 
>> the right value (it seem to choose the first or the final one). So I 
>> would like to verify if Modelsim put the right value in the memory
>> the declaration of the memory look like this:
>>
>> --declaration of a memory subtype
>> type TYPE_RAM is array (512 downto 0) of
>                           ^^^^^^^^^^^^^
> I dare to say for arrays of any type one will mostly want to declare 0 to 
> 2**N-1 (in your case, 0 to 511). I was having the very same problem a few 
> weeks ago just because of that. I also thed to automaticaly type downto 
> when coding arrays but in this particular category the outcome is clearly 
> not what one wants though it's sintaticaly correct.
>
> HTH.
>
> Elder.
>
>
> 



Article: 78043
Subject: where can I find description for Synopsys library (such as and_or.ib, class.lib etc)
From: "Simin" <simindai@hotmail.com>
Date: Sun, 23 Jan 2005 14:09:10 -0800
Links: << >>  << T >>  << A >>
Hi all,

     I am working on a project that will translate VHDL to EDIF format, the 
netlist shall only contain logic gates. I have tried XILINX XST, but netlist 
not only have logic gates but also have LUT and cell such as multiplier. So 
I transfer to Synopsys, by using target library and_or , I could see the 
netlist  have  'and' ,'or','inv', "ripper'  primitive. I really need to find 
out description for and_or library. But searching the whole Synopsys folder, 
none of documentation is about library.

   Anyone knows where can I find the library documentation?

   Thanks in advance

   Simin 



Article: 78044
Subject: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
From: "Mr M" <mrs@telia.com>
Date: Sun, 23 Jan 2005 23:09:41 +0100
Links: << >>  << T >>  << A >>
I'm not using it for an UART. It's used for an ADS1251 AD-converter to get
an exact sampling frequency of 4800 Hz.

But now I got some new ideas, thanks :-)

"Kryten" <kryten_droid_obfusticator@ntlworld.com> skrev i meddelandet
news:EpzId.1975$uK5.52@newsfe3-gui.ntli.net...
>
> "Mike Harrison" <mike@whitewing.co.uk> wrote in message
> news:jke5v0h4o2vfurfsv9allhdo8ir9cm3g0n@4ax.com...
> > On 22 Jan 2005 10:38:45 -0800, skolpojken72@yahoo.se (Elektro) wrote:
> >
> >>Hello
> >>
> >>I'm using a Spartan-3. I'm wondering if there is an easy way to
> >>fabricate a clock with 1.8432 MHz from a 24 MHz input clock?
> >>
> >>Could I use a DCM to get this exact clock frequency?
> >>
> >>Or should I make a frequency that over a period of time has an average
> >>of 1.8432 MHz?
> >
> > Is divide by 13 not close enough...? 1.8461 would be close enough for
> > RS232 comms
>
> 240000 / 18432 = 625 / 48
>
> How about a 10-bit register that decrements by 48 every clock tick.
> Whenever it goes negative, add 625 as well and output a UART clock pulse.
> Alternatively, if the last clock tick sent it negative, add (625-48)= 577
on
> the next.
>
> I think this should give the exact average frequency, with a little jitter
> (edges may vary by one 24MHz clock period.
>
>
>
>
>
>
>



Article: 78045
Subject: Re: Comparison of LEON2, Microblaze and Openrisc processors
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 24 Jan 2005 09:13:13 +1000
Links: << >>  << T >>  << A >>
Luc wrote:
> In any case, you would expect that the MicroBlaze would perform better
> on a Xilinx device. Can one of the Xilinx Apps Guys comment why an
> open core CPU has a better performance than MicroBlaze?

This just suggests to me that the Sparc instruction set architecture 
(ISA) used by Leon is more "efficient" than Microblaze, in the sense 
that it does more computational work per cycle (MIPS per MHz).

However, that efficiency is clearly coming at significant logic expense, 
as evidenced by Microblaze demolishing both Leon and OpenRisc when the 
numbers are normalised with respect to LUTs (MIPS/MHZ/LUT), where I 
think Microblaze was better by factors of 4X to 8X in all configurations.

What this suggests to me is that if you can exploit parallelism in your 
application by plonking down two or more microblazes [1], then you will 
get a big win over Leon or OpenRisc, in terms of FPGA size, and thus 
perhaps power consumption and all the rest[2].

No-one in this newsgroup should be surprised by an experiment that 
demonstrates that you can trade time for area.  It's just a design choice.

Seperate to that, there are possibly some other irregularities with the 
comparison, such as the fact that microblaze debug logic was left 
enabled, which introduces both Fmax and LUT count penalties.

Of course, what it really proves is that meaningful benchmarks are hard. 
  No surprises there.

Regards,

John

[1] and keep them busy with meaningful work

[2] Multiprocessor microblaze systems are getting more and more 
attention recently - as evidenced by recent posts here and in other 
forums.  I think this is largely due to the Microblaze's FSL bus, which 
is much much easier to work with than conventional shared bus 
architectures, and the cache coherency issues that they introduce.

Article: 78046
Subject: Re: Microscope examination of a PLD
From: "logjam" <grant@cmosxray.com>
Date: 23 Jan 2005 15:31:37 -0800
Links: << >>  << T >>  << A >>
I know I have access to 20% nitric acid, possibly stronger if I sweet
talk the metallurgy lab guy.  We use it for etching polished metals to
look at the microstructure.

So I will try this on monday:
-Shave PLD about 1/8"
-place flat on a hot plate, around 130*C
-Drip nitric acid on it until the silicon is visible

I'll be doing this in a lab with full negative pressure fume hood and a
face shield.  Not a range top stove and exhaust vent.  ;)

If that doesn't work I guess there are companies who do it for $50.
There are also manufactures of these decapping machines.  I might try
sweet talking them into helping out a poor student.  ;)

Here is a link I found on decapping the little buggers:

http://www.mrlaser.com/Brodsky9-1.pdf

If all else fails, I'm getting a 100MHz 18 channel 128k+ sample logic
analyzer...so...  ;)

Grant


Article: 78047
Subject: Re: How does a SDRAM controller work?
From: a <a@a1>
Date: Mon, 24 Jan 2005 11:06:10 +1100
Links: << >>  << T >>  << A >>
Gabor wrote:
> Georgi Beloev wrote:
> 
>>savingsandloan wrote:
>>
>>>Just out of curiosity, is it possible to pipeline successive reads
> 
> and
> 
>>>writes to SDRAM? For example, I want to send a read command and
> 
> then a
> 
>>>write command, where the memory address will be different for reads
> 
> and
> 
>>>writes. After the necessary latency after the first read command,
> 
> will
> 
>>>there also be a delay between when I clock in data from that read
> 
> and
> 
>>>when I can start outputting write data?
>>>
>>
>>As far as I remember, there is no delay if the write is to a row that
> 
> is
> 
>>currently active. In SDRAM you have 2 or 4 banks and each bank can
> 
> have
> 
>>one row active at a time. There are special commands to activate a
> 
> row
> 
>>and precharge (store back) a previously activated row. You can only
>>read/write to an activated row.
>>
> 
>>From a practical standpoint you should figure on wasting at least one
> cycle when switching between read and write in order to avoid
> overlapping
> drive on the DQ pins.  If you're continuing to just write (or just
> read)
> you can burst continuously by "burying" the row precharge.  This
> requires
> switching banks whenever you start a new row, however if you define
> "sequential" addresses such that the bank address bits are lower than
> the
> row address, you will be able to burst write or read the entire memory
> without any NOP cycles on the data lines.
> Also when switching from write - which presents data and command on the
> same cycle - to read, which has the "CAS latency" between the read
> command
> and the data cycle you will have multiple unused data cycles if you
> stay
> on the same bank (i.e. one bank cannot have a read command issued
> during a write burst).
> 
>>SDRAM datasheets from Micron, ISSI, and others have nice timing
> 
> diagrams 
> 
>>illustrating different cases.
>>
>>-- Georgi
> 
> 
"you will be able to burst write or read the entire memory without any 
NOP cycles on the data lines."

Also, when bursting like this you need to make sure you touch an 
individual row at least once every 64ms. This depends on the clock 
frequency you're running the SDRAM at and the size of the SDRAM.
You also have to be careful with what you do once you exit your bursting 
state.  If you then revert to using a refresh command and the SDRAMs 
internal refresh counters, you'll have to assume that you come out of 
bursting with the worst case alignment between the row you last accessed 
while bursting and the internal refresh counters used by the refresh 
commands.


Article: 78048
Subject: imported ip
From: "Fayette" <tortoisedundee@yahoo.com>
Date: Sun, 23 Jan 2005 20:39:39 -0500
Links: << >>  << T >>  << A >>
I have used Create/Import IP Wizard to import an IP i created into the
edk_user_repository. When I try to generate a bitstream it produces the
following errors.



Article: 78049
Subject: Re: imported ip
From: "Fayette" <tortoisedundee@yahoo.com>
Date: Sun, 23 Jan 2005 20:57:00 -0500
Links: << >>  << T >>  << A >>

"Fayette" <tortoisedundee@yahoo.com> wrote in message
news:unYId.15858$zi3.7021@fe07.lga...
> I have used Create/Import IP Wizard to import an IP i created into the
> edk_user_repository. When I try to generate a bitstream it produces the
> following errors.
>
Sorry about that.

ERROR:MDT - File not found in any repository
'quadrature/hdl/vhdl/shift.vhd'

This error is repeated for all the files in the ip, but they exist in
the
repository. I tried setting the repository directory, but that doesn't
change anything. This is probably very simple, but please help.

Thanks





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