Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thank you all. I made a 625/96 divider and toggled the clock output bit by that, and it worked nicely. :-) I got 48 clocks out when I put 625 clocks in. Others than me selected this "odd" frequency, so I couldn't select a more appropriate one by myself. :-/ Otherwise I would have selected another frequency. And by the way, does anybody know a good book with these kinds of examples? Thanks :-) "Jim Granville" <no.spam@designtools.co.nz> skrev i meddelandet news:41f47e00$1@clear.net.nz... > > > Hal Murray wrote: > > >>I'm not using it for an UART. It's used for an ADS1251 AD-converter to get > >>an exact sampling frequency of 4800 Hz. > > > > > > What do you mean by "exact"? How good is the crystal you are > > starting with? > > > > 24 MHz divided by 5000 gives a nice clean 4800 HZ. > > Why go through 1.8432 MHz? > > I'd guess the ADS1251 starts with that ? > > So there are a couple of choices > > a) Divide by 13, and accept the slight sample error, but zero jitter, > or > b) divide by 625/48 as someone else suggested. > > However, rather than implement split adders as counters, this can also > be done with a much simpler swallow counter : > > for 47/48 times divide by 13, and for 1/48 times, divide by 14. > > Result is 625 clocks in, for 48 out. > Freq average is exact, but has slight edge jitter on the /14 cases > > -jg >Article: 78076
the schwantz wrote - > >Try to find an old Data IO PAL programmer. You can read out the fuse >pattern from a PAL. I don't remember there being any copy protection >available in PALs of that vintage. > if you can get the JED file, Lattice has available on it's website - PAL2GAL.exe - this is a useful utility that converts pretty much any older PAL device file to an equivalent, pin compatilble GAL - good luck - Mike Thomas LSC FAEArticle: 78077
I am in urgent need of the XCF02S EPROM. A very standard component for Xilinx device yet it is impossible to source. INSITE will only sell but in the bucket load only, while I only require one or two. Does anyone know how or who sells to the small people Cheers ChukArticle: 78078
On Mon, 24 Jan 2005 16:17:57 +0100, "Elektro" <mrs@telia.com> wrote: >Thank you all. I made a 625/96 divider and toggled the clock output bit by >that, and it worked nicely. :-) I got 48 clocks out when I put 625 clocks >in. Are you aware of the effects of clock jitter on ADC performance? You should check with your system designers about this effect, otherwise you may get "sub-optimal" results, i.e. it won't work. The ADS1251 is a 24 bit ADC. Assuming a full scale input signal of 1000Hz (a guess, based on Fs = 4800Hz), 41ns p-p of clock jitter will degrade the performance to about 12 bits. This gets better as the input frequency is reduced, e.g. a 100Hz input will give about 15-16 bits. (I made some assumptions that may not apply to Sigma-Delta ADCs though. Unfortunately, the ADS1251 data sheet does not mention its sensitivity to jitter.) It's possible that the divide by 13 counter would be better, as it generates no jitter. Can you tolerate the frequency error? Regards, AllanArticle: 78079
On 24 Jan 2005 06:38:07 -0800, "kart" <brick_in_the_wall2003@yahoo.co.in> wrote: > >Stressed: Suppling voltage higher than normal operating voltage, to >Vcc and Vss pins of SRAM for certain time duration,which is below >chip failure time for that voltage. This is not a valid stress test, and will provide no meaningful results to an OEM. Stress testing involves operating devices within their specified maximum ratings. Exceeding them serves no useful purpose in design verification or validation, unless it is done in cooperation with the part's manufacturer. In that case, most of your questions could be resolved by those with knowledge of the specific part in question; it's design, fab materials and process limitations. RLArticle: 78080
Chuk,
try www.avnet.com
Aurash
charlesg77@yahoo.com wrote:
>I am in urgent need of the XCF02S EPROM. A very standard component for
>Xilinx device yet it is impossible to source. INSITE will only sell
>but in the bucket load only, while I only require one or two. Does
>anyone know how or who sells to the small people
>
>Cheers
>
>Chuk
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 78081Hi *, I have some doubts on the use of LVPECL25-input buffers. The situation is as follows: I have a 3.3V-LVPECL-clock source, which I need to connect to a global clock pin that is inside a bank powered with VCCO=3.3V. But the only LVPECL-input buffer available for instantiation in V2P is the IBUFDS_LVPECL_25, hinting at VCCO=2.5V. xapp696 ( http://www.xilinx.com/bvdocs/appnotes/xapp696.pdf ) explains how to connect a 3.3V-LVPECL-Transmitter to a 2.5V-LVPECL-receiver. But is the IBUFDS_LVPECL_25 really 2.5V, even if it resides in a bank powered with 3.3V? The tools (PACE, map and par) allow to place LVCMOS33 and LVPECL25-IOs in the same bank, so I guess everything should be OK. Is this because differential input buffers are powered by VCCAUX, which is 2.5V, regardless of the bank's VCCO? Or is an IBUFDS_LVPECL_25 really LVPECL_33 when it's inside a 3.3V-powered bank? In that case I would have to use a different termination scheme... -- cu, SeanArticle: 78082
On Mon, 24 Jan 2005 14:18:38 +0100, Göran Bilski wrote: > Hi, > > Try to simulate a little more than 2 us. > In the first 2 us after reset not much is toggled. > > Göran I tried up to 100 us, but no improvement in accuracy. I forced the sys_clk_pin signal to be a 50MHz clock and the sys_clk_rst signal to provide for a warm reset, but still no improvement in accuracy. Thanks, kl31nArticle: 78083
Il Mon, 24 Jan 2005 13:05:13 +0000, Aurelian Lazarut ha scritto: > The XPower results are dependant on the toggling information coverage > from your VCD file, which is dependant on other factors like your > software running on the Microblaze processor and/or external events > (like interrupts, network packets etc.) . To give you a simple example > you can have a counter/timer in your Microblaze system but your software > doesn't enable the counter/timer (is not running) so it will not take > much power (as if it was running) try to write a test software which > enables all the peripherals in your system (dummy functions) to force a > better coverage in your VCD file. The software I've written is already a simple version of the custom DSP I've designed(the software has been written just for the power analisys). It doesn't use interrupt, it doesn't even use functions. There's just the main with inside an infinite loop. The only peripheral used is the EMC. I forced the sys_clk_pin signal to be a 50MHz clock and the sys_rst_pin to provide for a warm reset. I cannot understand what keeps the accuracy low as the whole thing is very simple. Thanks, kl31nArticle: 78084
I've been trying to divide a 60Hz signal down to 1Hz and slower using an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60, and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input which seemed to remove some problems. It still has random delays in the output. Is 60Hz too slow for this device? NathanArticle: 78085
Do you have any printout in the code? If the program starts with some printouts, then it will wait on the UART to transmit the characters before doing something useful. Göran kl31n wrote: > On Mon, 24 Jan 2005 14:18:38 +0100, Göran Bilski wrote: > > >>Hi, >> >>Try to simulate a little more than 2 us. >>In the first 2 us after reset not much is toggled. >> >>Göran > > > I tried up to 100 us, but no improvement in accuracy. I forced the > sys_clk_pin signal to be a 50MHz clock and the sys_clk_rst signal to > provide for a warm reset, but still no improvement in accuracy. > > Thanks, > > kl31nArticle: 78086
Hello all, I am trying to implement a DSP algorithm on a FPGA(SpartanIIE). I was wondering if somebody could comment on whats the best way to truncate the multiplier outputs to the 8bit inputs I have. If I have 8bits inputs to the multiplier I want the output to be 8bits too instead of 16bits. I know I'l be losing out on precision but thats fine. Whats the best way to do it in hardware? Thanks, SourabhArticle: 78087
nathan_wilson@hotmail.com wrote: > I've been trying to divide a 60Hz signal down to 1Hz and slower using > an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60, > and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input > which seemed to remove some problems. It still has random delays in the > output. Is 60Hz too slow for this device? An RF choke sounds good, but you should have more than that. A Schmidt trigger so it doesn't count noise that still comes through. Otherwise 60Hz counting isn't too slow, but the edge must be faster than that. If you put it through a few inverters (and make sure they don't get optimized away) that would speed up the transition. -- glenArticle: 78088
Luc wrote: "Can one of the Xilinx Apps Guys comment why an open core CPU has a better performance than MicroBlaze?" Why do you assume that a CPU which is open-source should perform worse than a CPU which is closed-source? Sun will open-source the Solaris 10 operating system - will Solaris then become less performant than when it was closed source? LEON was designed for critical space applications at the European Space Agency. It has been open-sourced to increase testing in order to minimize the risk of latent errors. The fact that it has better CPI (clock per instruction) than Microblaze and Openrisc depends on several aspects: more advanced cache, lower branch and load delay, larger register file, better optimizing compiler. Whether it is open-source or not does not affect the performance ... Jiri.Article: 78089
Moti: Thank you very much for your reply. Clearly you went to a lot of trouble, and this was very helpfull. I am now able to include my ip in my design. Again thank you, Fayette "Moti" <moti@terasync.net> wrote in message news:1106565401.479122.162450@z14g2000cwz.googlegroups.com... > I made a mistake in the follwoing line: > > b) in the "how to locate your hdl files" - set "use an xst project > file" and browse to the prj file (under the \projnav\ root in your > repository). > > the .prj file should be under the peripheral_name \devl\synthesis\ in > your > repository > > Moti. >Article: 78090
Kryten, > > [see http://www.lsi.usp.br/~jecel/mac512.html] > > Very impressive. > > Might we get to see your equations? > Pretty please? :-) As I mentioned in that page, after the job was done I gave Unitron all the material I had created without keeping a copy for myself (that was one of the terms of our contract). Many years later, however, I did find the very first draft of the equations (badly scribbled on) and the middle two pages of a report I wrote inside an old notebook. Since by that time Unitron had abandoned the computer industry entirely, I decided not to destroy this material. This morning I scanned it converting each page into a (very large) PDF file. For it to be of any use to people I would have to translate the comments and report from Portuguese to English, but if you want it anyway: http://www.merlintec.com/download/unitron1.pdf (8.4MB) first page of equations http://www.merlintec.com/download/unitron2.pdf (7.4MB) second page of equations http://www.merlintec.com/download/unitronrelatoriop2.pdf (300KB) page 2 (of ?) of project report http://www.merlintec.com/download/unitronrelatoriop3.pdf (1.7MB) page 3 (of ?) of project report This was the very first draft I mentioned in my story (which impressed Alberto Diez (not Dias like I spelled on that page) when he thought it took me a week to do) and the second draft, probably incorporating most of the hand written notes in the above file, was broken enough that even the power supply wouldn't start up. It was the third draft that after a small patch made the machine work and I don't have that available. Note that I had to come up with my own names for many of the pins and they won't match the schematics you can see online.Article: 78091
Hi Sean, Please let me know if you get an answer! Check out these CAF threads where I got some information, but not much. Cheers, Syms. Differential terminations in Virtex2 Pro. Differential terminations in Virtex2 Pro.Attempt II! Xilinx LVDS_25_DT termination issues???? "Sean Durkin" <smd@despammed.com> wrote in message news:41f533a8$1@news.ginko.net... > > But is the IBUFDS_LVPECL_25 really 2.5V, even if it resides in a bank > powered with 3.3V? The tools (PACE, map and par) allow to place LVCMOS33 > and LVPECL25-IOs in the same bank, so I guess everything should be OK. > > Is this because differential input buffers are powered by VCCAUX, which > is 2.5V, regardless of the bank's VCCO? Or is an IBUFDS_LVPECL_25 really > LVPECL_33 when it's inside a 3.3V-powered bank? In that case I would > have to use a different termination scheme...Article: 78092
Sourabh, Signed or Unsigned? Syms. "SD" <sourabh.dhir@gmail.com> wrote in message news:1106591437.954338.25640@c13g2000cwb.googlegroups.com... > Hello all, > I am trying to implement a DSP algorithm on a FPGA(SpartanIIE). I was > wondering if somebody could comment on whats the best way to truncate > the multiplier outputs to the 8bit inputs I have. If I have 8bits > inputs to the multiplier I want the output to be 8bits too instead of > 16bits. I know I'l be losing out on precision but thats fine. Whats the > best way to do it in hardware? > > Thanks, > Sourabh >Article: 78093
Hi all - I'm just doing my first device (a Spartan 3S200 or 400) after a break of 5 years, and I'd like to do a scripted flow (I've done this previously with 4K&Virtex/Leonardo/Foundation, running par/map/ngdbuild/etc from a makefile). Can anyone tell me if this is possible with the free Webpack tools, or will I have to buy something? Is the free XST scriptable? Is XST any good? Finally, any ideas on whether the flow has changed radically since 2000, or should I just be able to take up where I left off? Cheers - RickArticle: 78094
<nathan_wilson@hotmail.com> wrote in message news:1106590027.557745.170670@f14g2000cwb.googlegroups.com... > I've been trying to divide a 60Hz signal down to 1Hz and slower using > an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60, > and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input > which seemed to remove some problems. It still has random delays in the > output. Is 60Hz too slow for this device? > > Nathan You need a good sharp edge transition. Buffer the signal with a schmidtt-trigger, something along the lines of a 74HC14 should work. Tie the HC14's unused inputs to a single level so they don't make the unused output chatter. I'm assuming you have already done some kind of signal conditioning on the 60Hz signal to make it at least TTL compatible. Rob YoungArticle: 78095
On Mon, 24 Jan 2005 19:08:57 +0100, Göran Bilski wrote: > Do you have any printout in the code? > If the program starts with some printouts, then it will wait on the UART to > transmit the characters before doing something useful. No, it doesn't have any sort of I/O to the RS-232 port. The app used for the power analisys has been taylored just for that purpose and all of the data come and go on the SRAM(they aren't meaningful data, as I said the app is taylored only for power analisys). As I said in the reply to Aurelian the only peripheral which is used is the EMC. Thanks, kl31nArticle: 78096
nathan_wilson@hotmail.com wrote: > I've been trying to divide a 60Hz signal down to 1Hz and slower using > an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60, > and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input > which seemed to remove some problems. It still has random delays in the > output. Is 60Hz too slow for this device? A 60Hz sine wave certainly is. Where does the 60Hz come from - i guess the AC mains [hopefully isolated]? You will need a low pass filter, and a schmitt trigger, to give the fast clock edges the PLD likes. The low pass filter can be series R with shunt C, and should have a corner < 100Hz. There is a lot of glitch noise on the AC mains, and the 9572 will otherwise faithfully count those that fall inside the schmitt crossing band. The LPF removes that. -jgArticle: 78097
Hi All, Just a wild guess here, but would it be possible to increase the 24MHz using a DCM by 2x of 4x, and then using this faster clock to generate the 1.8...MHz signal. The clock period would be smaller, and thus, I assume you could reduce the edge jitter using this fact? Just an idea..haven't given it a lot of thought! Allan Herriman wrote: > On Mon, 24 Jan 2005 16:17:57 +0100, "Elektro" <mrs@telia.com> wrote: > > >>Thank you all. I made a 625/96 divider and toggled the clock output bit by >>that, and it worked nicely. :-) I got 48 clocks out when I put 625 clocks >>in. > > > Are you aware of the effects of clock jitter on ADC performance? You > should check with your system designers about this effect, otherwise > you may get "sub-optimal" results, i.e. it won't work. > > The ADS1251 is a 24 bit ADC. > Assuming a full scale input signal of 1000Hz (a guess, based on Fs = > 4800Hz), 41ns p-p of clock jitter will degrade the performance to > about 12 bits. > This gets better as the input frequency is reduced, e.g. a 100Hz input > will give about 15-16 bits. > (I made some assumptions that may not apply to Sigma-Delta ADCs > though. Unfortunately, the ADS1251 data sheet does not mention its > sensitivity to jitter.) > > > It's possible that the divide by 13 counter would be better, as it > generates no jitter. Can you tolerate the frequency error? > > Regards, > AllanArticle: 78098
I plan to have it "unsigned".Article: 78099
<nathan_wilson@hotmail.com> wrote in message news:1106590027.557745.170670@f14g2000cwb.googlegroups.com... > I've been trying to divide a 60Hz signal down to 1Hz and slower using > an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60, > and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input > which seemed to remove some problems. It still has random delays in the > output. Is 60Hz too slow for this device? > > Nathan > What else do you have in the pld? A "normal" clk? some extra ff's? I would set ff Q1 when 60 hz = '1' and QUAL = '0' and clear ff Q1 when 60 hz = '0' and QUAL = '1' where QUAL is ff Q1 delayed by a ms or so using the "normal" clk and some ff's. Use ff Q1 as your 60 hz global clk and you should be good to go. If you do this you can probably lose the rf choke too.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z