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Messages from 5275

Article: 5275
Subject: Re: Altera BitBlaster
From: Woody Johnson <woodyj@transition.com>
Date: Mon, 03 Feb 1997 13:09:33 -0600
Links: << >>  << T >>  << A >>
Steve Schossow wrote:
> 
> I've been using the Altera FPGAs for 6 months or so and one of the first
> things that bugged me was the cost of the BitBlaster.  $200 for a little
> box (with an Altera FPGA in it no less) just to download the parts.
> 
> So I dabble in programming and wrote a short program to wiggle a couple
> of bits on the printer port to download my 81188 and 10K50 parts.
> 
> It works great and is at least as fast as the BitBlaster.  It reads the
> design's .ttf file created when you do place and route.
> 
> Any interest?  I'll e-mail or post depending on how many responses I
> get.

Or you could use the printer port using their ByteBlaster cable for 
_much_ faster programming times (than the BitBlaster serial cable 
method).  Again they charge too much for the cable but its pretty
simple to make your own (I have a rough schematic).
Article: 5276
Subject: Re: Reconfigurable Logic Query
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 3 Feb 1997 19:18:44 GMT
Links: << >>  << T >>  << A >>
There is actually quite a bit of information regarding reconfigurable logic
and reconfigurable computing available on the Web.  Check out the following
link for a list of applicable sites:

http://www.netcom.com/~optmagic/research.html

I hope this is helpful.
-- 
Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Ed Vogel <epv@pcsi.cirrus.com> wrote in article
<32F0F9D3.18E2@pcsi.cirrus.com>...
| I am considering the design of a dynamically reconfigurable logic 
| platform. It is more in line with tinkering than a serious product 
| application. Has anyone else tried to build an in circuit programmable 
| interface inside an FPGA or CPLD? 
| 
|   I realize that Lattice offers something of this sort(pseudo JTAG port) 
| but I want to go one step further; to make connections between "user 
| defined" muxes surrounding "user defined" logic blocks. In short I want 
| to waste the resources provided for me by the chip manufacturer and third

| party tool designers to functionally design and program an FPGA or CPLD 
| in favor of using those resources to build a "scaffolding" inside to 
| facilitate the construction of dynamically reconfigurable logic. I 
| realize this is wasteful. I want control over routing delays and 
| repeatability without consulting a third party. It also would allow 
| greater flexibility in interfacing to C compiler outputs. Just curious. .

| .
| 


Article: 5277
Subject: Re: Steven K. Knapp - no such article
From: Lance Gin <c43lyg@dso.hac.com>
Date: Mon, 03 Feb 1997 11:44:18 -0800
Links: << >>  << T >>  << A >>
Aage Farstad wrote:

> Can anybody give me a hint of what's wrong with my newsreader? Every
> time I try to open a message from this guy, my newsreader (netscape3.0)
> says: No Such article, Perhaps the article has expired! He is the only
> one treated this way!
> 
> Best Regards Aage Farstad
> 
> aage.farstad@ffi.no

same happens to me. let's hope steve can provide some insight.

-- 

Lance Gin                            "off the keyboard, over the bridge
Delco Systems-GM Hughes Electronics   through the gateway,
C43LYG@dso.hac.com                    nothing but NET!"
Article: 5278
Subject: Re: Safety Critical Apps -> Xilinx Checker.
From: kgold@watson.ibm.com (K Goldman)
Date: 3 Feb 1997 20:08:29 GMT
Links: << >>  << T >>  << A >>

fliptron@netcom.com (Philip Freidin) writes:
|> Brian reminds us that the XC4K readback includes a CRC, and by setting 
|> the appropriate option, and not using the CLB RAM capability, the CRC 
|> value will be constant, and can be read back continuously, using only 
|> internal resources. The compare need only be done between the readback 
|> CRC, and a constant copy kept somewhere else.
|> 
|> He goes on to suggest that the compare (and I assume the reference copy 
|> of the CRC) might also be done on chip. I have thought about this for a 
|> few years, and I suspect but can not prove, that this is not possible. 
|> The reason is that the storing of a reference CRC value on chip will 
|> permute the calculated CRC. If you then change the reference value to the 
|> new value, it will just permute again. I suspect you may be able to play 
|> this silly game forever. 
|> 
|> Reference: Patent 5,321,704
|> 
|> Recomendation: Store the reference CRC outside the FPGA.

If a lurker may barge in ...

There are ways to append a generated CRC to a serial bit stream such
that, when the receiver checks the total CRC including the generated
CRC, a _constant_ magic number results when there are no errors.

See, for example, C Programmer's Guide to Serial Communications"
by Joe Campbell, for details.

-- 
Ken Goldman   kgold@watson.ibm.com   914-945-1466
Article: 5279
Subject: boundary scan - vhdl - xilinx
From: Christian Mautner <chm@vlsivie.tuwien.ac.at>
Date: 03 Feb 1997 21:30:37 +0100
Links: << >>  << T >>  << A >>

Anyone succeeded using boundary scan user modes (SEL1/SEL2) within Xilinx
xc4000 devices using ViewSynthesis?  We are using Workview Office and the
Synthesis tool fails to instantiate and connect the BSCAN component
correctly. When defining it using Viewdraw it works.

Moreover, a possibility to simulate the bscan component, at gate level or
behaviourally, would be great, and I am missing behavioural xblox
descriptions in VHDL, too. Didn't anyone start writing some? This should
to be no big deal. But Xilinx is probably to busy porting their software
to NT. at last.

chm.

-- 
Christian Mautner  chm@vlsivie.tuwien.ac.at


Article: 5280
Subject: Xilinx keys break on fast machines
From: jhallen@world.std.com (Joseph H Allen)
Date: Mon, 3 Feb 1997 20:35:41 GMT
Links: << >>  << T >>  << A >>
Being tired of those long APR times, I recently upgraded my 486 to a P6-200. 
This caused both my Xilinx and PADS dongles to stop working.  PADS includes
a program (called ssiact) to determine timing parameters which match your PC
to the dongle (it talks to the dongle for a while and then gives you an
environment variable to set for the main program to work).

Xilinx has no such program, and when I called them for help, they told me 
that I either had to buy the latest version or go back to using the 486.  

I am not happy.

Admittedly, my version of Xact is four years old (APR version 3.30), but
really, four years is not _that_ long ago.  What are these idiots doing
using processor speed dependant timing loops for anyway?

Grrrrrr......    maybe it's time to look at those AT&T ORCA FPGAs that I've
been hearing so much about.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 5281
Subject: Re: DES Challenge
From: gah@u.washington.edu (G. Herrmannsfeldt)
Date: 3 Feb 1997 20:38:26 GMT
Links: << >>  << T >>  << A >>

I downloaded the .ps.gz file as indicated in the follow up, but it
seems to have two mistakes.  As it is a gz file, these could not happen
during transmission to me.

In line 15101  insert 0  at the beginning of the line.

In line 14379 insert a space between the 5 and the 2.

-- glen
Article: 5282
Subject: Re: Q is Xilinx Foundation BASE worth buying?
From: kenk@teleport.com (Ken Krolikoski)
Date: Mon, 03 Feb 1997 21:08:35 GMT
Links: << >>  << T >>  << A >>
peter,
The foundation software is an excellent package. It's allows either
abel or schematic entry. Includes a simulator and the the fitter. Also
there is a migration path to a version which will allow you to use
VHDL.

Contact the Xilinx rep or one of the Xilinx distributors (Marshall,
Hamilton-Hallmark or Insight). There is an eval kit available for
foundation that lets you try the software.


pac1@waikato.ac.nz (pac1) wrote:

>I'm trying to decide if it is worth buying Xilinx Foundation BASE as
>oppose to the standard XACT Step package (because its much cheaper).

>Can anyone tell me if it is any good, what are its limitations - I've
>looked on Xilinx home page and can't find a good description of what it
>can or can't do!

>Thanks Peter.


Article: 5283
Subject: Re: Steven K. Knapp - no such article
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 3 Feb 1997 23:05:57 GMT
Links: << >>  << T >>  << A >>
I believe that I have the problem ironed out.  You should be able to
receive this.  It was an RTFM problem on my end with some of the finer
setup points with Internet Explorer and my ISP.
-- 
Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

R. T. Wurth <rwurth@att.com> wrote in article <32F22DA0.148D@att.com>...
| =?iso-8859-1?Q?Bj=F8rn?= B. Larsen wrote:
| > 
| > Aage Farstad wrote:
| > >
| > > Can anybody give me a hint of what's wrong with my newsreader? Every
| > > time I try to open a message from this guy, my newsreader
(netscape3.0)
| > > says: No Such article, Perhaps the article has expired! He is the
only
| > > one treated this way!
| > 
| > The same happens to me!
| > 
| > I am also using Netscape 3.0 now.
| > 
| > Bjørn BL.
| >
| 
| 
| I noticed it too, with netscape 2.?.  I did manage to see one of his 
| articles using trn on a UNIX box, and it has a special character in 
| the message-id field.  (No, I don't recall exactly what:  perhaps one 
| of {#$%}).  I could tell that was the problem, because the netscape 
| error message indicated the message-id, and the indicated message-id 
| was truncated starting with the offending character.  
| 
| So, Steve, if you want Netscape users to read your messages, see if you 
| can somehow get your software and/or ISP to provide a message-id.  I 
| suspect that somewhere there is an Internet RFC specifying the grammar 
| for parsing this field, that most newsreader-writers decided to be 
| generous in accepting errors, and that Netscape is being technically 
| correct (but wrong from a software engineering viewpoint) in rejecting 
| them.
| 
| Perhaps this should be further considered somewhere in the 
| news.software.*, or news.admin.* hierarchies.
| 
| -- 
|    R. T. Wurth / (w) Holmdel, NJ / (h) Rumson, NJ
|    rwurth@att.com
| 
Article: 5284
Subject: Re: boundary scan - vhdl - xilinx
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 4 Feb 1997 00:09:36 GMT
Links: << >>  << T >>  << A >>
I don't know if this helps but the following excerpt is from the HDL
Synthesis for FPGAs Design Guide available at
(http://www.xilinx.com/appnotes/hdl_dg.pdf) on the web (it is a 2.0 Mb
Acrobat document).  With Synopsys, you must assign a Don't Touch attribute
to the net connected to the TDO pad.  There may be a similar restriction
for VIEWsynthesis.  I'm not sure if anybody has created the behavioral
model yet.

Excerpt beginning on page 3-40:

Implementing Boundary Scan (JTAG 1149.1)
Note: Refer to the Development System User Guide for a detailed
description of the XC4000 boundary scan capabilities.
XC4000 FPGAs contain boundary scan facilities that are compatible
with IEEE Standard 1149.1. Xilinx devices support external (I/O and
interconnect) testing and have limited support for internal self-test.
You can access the built-in boundary scan logic between power-up
and the start of configuration. Optionally, the built-in logic is
available after configuration if you specify boundary scan in your
design. During configuration, a reduced boundary scan capability
(sample/preload and bypass instructions) is available.
In a configured FPGA device, the boundary scan logic is enabled or
disabled by a specific set of bits in the configuration bitstream. To
access the boundary scan logic after configuration in HDL designs,
you must instantiate the boundary scan symbol, BSCAN, and the
boundary scan I/O pins, TDI, TMS, TCK, and TDO.
Note: Do not use the FPGA Compiler boundary scan commands such
as set_jtag_implementation, set_jtag_instruction, and set_jtag_port
with FPGA devices.
Instantiating the Boundary Scan Symbol
To incorporate the XC4000 boundary scan capability in a configured
FPGA using Synopsys tools, you must manually instantiate
boundary scan library primitives at the source code level. These
primitives include TDI, TMS, TCK, TDO, and BSCAN. The example
in Figure 3-20 shows how to instantiate the boundary scan symbol,
BSCAN, into your HDL code. In this example, the four TAP pins are
declared as ports. The schematic for this design is shown in
Figure 3-21.
You must assign a Synopsys Don’t Touch attribute to the net
connected to the TDO pad before you use the Insert_pads and
Compile commands. Otherwise, the TDO pad is removed by the
compiler. In addition, you do not need IBUFs or OBUFs for the TDI,
TMS, TCK, and TDO pads. These special pads connect directly to the
Xilinx boundary scan module.

-- 
Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Christian Mautner <chm@vlsivie.tuwien.ac.at> wrote in article
<m2pvyhmy36.fsf@picard.gaga.at>...
| 
| Anyone succeeded using boundary scan user modes (SEL1/SEL2) within Xilinx
| xc4000 devices using ViewSynthesis?  We are using Workview Office and the
| Synthesis tool fails to instantiate and connect the BSCAN component
| correctly. When defining it using Viewdraw it works.
| 
| Moreover, a possibility to simulate the bscan component, at gate level or
| behaviourally, would be great, and I am missing behavioural xblox
| descriptions in VHDL, too. Didn't anyone start writing some? This should
| to be no big deal. But Xilinx is probably to busy porting their software
| to NT. at last.
| 
| chm.
| 
| -- 
| Christian Mautner  chm@vlsivie.tuwien.ac.at
| 
Article: 5285
Subject: Re: DES Challenge
From: Steve Casselman <sc@vcc.com>
Date: Tue, 4 Feb 1997 01:38:30 GMT
Links: << >>  << T >>  << A >>
The guy who broke the 40-bit code made the LA times.
It took 250 workstations 3 1/2 hours. If he had to search
to the last combination it would have taken 10 hr. I 
figured that a 50MHz engine would have taken 6 hrs.
The 48-bit key search (which is next) should take
256 times longer. 

Steve Casselman
Article: 5286
Subject: Thanks for suggestions
From: gtd750a@acmey.gatech.edu (Scott McIntosh)
Date: 4 Feb 1997 04:16:23 GMT
Links: << >>  << T >>  << A >>
Thanks for the feedback.  I think we're going to go with Mill-Max, 7 day
turnaround and sub-$40 price.  They also happen to have some other stuff
we want to get to.  One order, lower shipping.  Thanks again.

--
Scott McIntosh						U. of Kentucky
Georgia Tech : gtd750a@prism.gatech.edu		 	  WILDCATS
Scientific Research Corp.: smcintosh@scires.com		NCAA Champions
Article: 5287
Subject: REPOST: New Web Site Dedicated to Programmable Logic
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 4 Feb 1997 05:48:07 GMT
Links: << >>  << T >>  << A >>
This is a repost of a message due to problems reported by Netscape 3.0 news
reader users.

There is a new site for designers interested in programmable logic.  The
Programmable Logic Jump Station provides quick and easy access to 

* all major FPGA, CPLD, and PLD device manufacturers
* most EDA companies that support programmable logic design
* books on programmable logic
* university and industry research groups studying programmable logic and
its applications
* search engines and links to other sources of information on programmable
logic
* design consultants for programmable logic applications
* conferences and trade shows about programmable logic

Programmable Logic Jump Station: 
http://www.netcom.com/~optmagic/index.html

The Programmable Logic Jump Station was recently named an 'Outstanding
Site' by the PC Webopaedia.

-- 
Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic
Article: 5288
Subject: Re: Xilinx keys break on fast machines
From: Brad Taylor <blt@emf.net>
Date: Mon, 03 Feb 1997 22:09:36 -0800
Links: << >>  << T >>  << A >>
Joseph H Allen wrote:
> 
> Being tired of those long APR times, I recently upgraded my 486 to a P6-200.
> This caused both my Xilinx and PADS dongles to stop working.  PADS includes
>
...
> I am not happy.
>

I believe the PADS web site has some doc on this very subject. As I
remember it, they suggest that you buy a cheap ISA card for your
parallel port, which I guess will slow it down enough. 
-
Brad
Article: 5289
Subject: Re: Verilog --> FPGA
From: scottydm@aol.com
Date: 4 Feb 1997 12:37:16 GMT
Links: << >>  << T >>  << A >>
    I'll add VeriBest Designer to the list.
                   Scott


Scott D. Miller        Freelance chip designer
ScottyDM@aol.com       Arete, Ltd.
"always  #5 FOO = ~FOO;   //the sound of a beating heart"

Article: 5290
Subject: Re: Xilinx keys break on fast machines
From: ecla@world.std.com (alain arnaud)
Date: Tue, 4 Feb 1997 13:23:40 GMT
Links: << >>  << T >>  << A >>
Brad Taylor (blt@emf.net) wrote:
: Joseph H Allen wrote:
: > 
: > Being tired of those long APR times, I recently upgraded my 486 to a P6-200.
: > This caused both my Xilinx and PADS dongles to stop working.  PADS includes
: >
: ...
: > I am not happy.
: >

	There's two kind of Xilinx keys, the real old one which was black
	and the newer one which is grey and has a serial number starting with
	"C". The C key works with version 4 and above. All of the black ones
	were replaced with the grey one in 94 when version 4.0 was released.

	When XACT 6.0 was released in the summer 95, the C key stopped
	working on some machines because the parallel port was too fast.
	There are two solutions to that:

	1. Check the hardware setting for the parallel port  and set the port
	to unidirectional (some PC call it compatible), the Xilinx key should 
	then work. It is a good idea to also try all the settings.

	2. Install an "old" ISA card with a parallel port, that only supported
	unidirectional ports.
Article: 5291
Subject: Re: Altera BitBlaster
From: Ed Barrett <ed.barrett@worldnet.att.net>
Date: Tue, 04 Feb 1997 09:08:10 -0800
Links: << >>  << T >>  << A >>
Martin Mason wrote:
> 
> >
> > Steve Schossow wrote:
> > >
> > > I've been using the Altera FPGAs for 6 months or so and one of the first
> > > things that bugged me was the cost of the BitBlaster.  $200 for a little
> > > box (with an Altera FPGA in it no less) just to download the parts.
> > >
> > > So I dabble in programming and wrote a short program to wiggle a couple
> > > of bits on the printer port to download my 81188 and 10K50 parts.
> > >
> > > It works great and is at least as fast as the BitBlaster.  It reads the
> > > design's .ttf file created when you do place and route.
> > >
> > > Any interest?  I'll e-mail or post depending on how many responses I
> > > get.
> > Or you could use Atmel's AT17C series in system programmable serial EEPROM
> FPGA configuration memories, which work with *all* SRAM FPGAs.  For more
> information or to request a FREE sample pay a visit to
> 
> http://www.atmel.com/atmel/products/products22.html
> 
> Martin.

Or, try Lattice In System Programmable CPLDs. they program from the PC 
printer port and Lattice provides free windows based programming 
software. Their web site http://www.latticesemi.com

Ed
Article: 5292
Subject: HELP: Signed Arithmetic in Behavioral Verilog
From: Elliot Waingold <elliotw@lcs.mit.edu>
Date: Tue, 04 Feb 1997 16:06:20 -0500
Links: << >>  << T >>  << A >>
Does anybody have an easy way to perform signed integer arithmetic on
values in registers of arbitrary width?  If possible, please respond via
email.

Thanks,
Elliot

-- 

Elliot Waingold			elliotw@lcs.mit.edu
3 Ames Street Box 170		http://www.cag.lcs.mit.edu/~elliotw
Cambridge, MA 02142		(617)225-6133
Article: 5293
Subject: Robust Applications with FPGAs
From: sundberg jeffrey r <sundberg@uiuc.edu>
Date: Tue, 04 Feb 1997 20:49:44 -0600
Links: << >>  << T >>  << A >>
I am working on a solar powered car for the University of Illinois'
Sunrayce '97 entry, an need to imprelement a cruise control/engine
control block of logic.  Because the logic must be mounted in our
vehicle, the application must be robust and able to withstand several
days of competetive driving during summer across the interstate
highways.  
	My question is: what is the best target device platform to implement
the design on, and where can I find more resource information on that
platform?
	Thanks much,
	Jeffrey Sundberg
Article: 5294
Subject: Re: Altera BitBlaster
From: moby@kcbbs.gen.nz (Mike Diack)
Date: 5 Feb 97 03:53:38 GMT
Links: << >>  << T >>  << A >>
In message <<32F1173E.43A8@tisc.com>> Steve Schossow <ss@tisc.com> writes:
> things that bugged me was the cost of the BitBlaster.  $200 for a little
> box (with an Altera FPGA in it no less) just to download the parts.
> 
> So I dabble in programming and wrote a short program to wiggle a couple
> of bits on the printer port to download my 81188 and 10K50 parts.
> 
> It works great and is at least as fast as the BitBlaster.  It reads the
> design's .ttf file created when you do place and route.
> 
> Any interest?  I'll e-mail or post depending on how many responses I
> get.


You would be doing humanity in general and me in particular a great
service if you posted this info.
cheers
Mike
Article: 5295
Subject: Final Notice: FPGA'97 is next week
From: hauck@eecs.nwu.edu (Scott A. Hauck)
Date: Tue, 04 Feb 1997 23:01:46 -0600
Links: << >>  << T >>  << A >>
-------------------------------------------------------------------------------
                 Advance Program

             1997 ACM/SIGDA Fifth International Symposium on 
            Field-Programmable Gate Arrays (FPGA'97)

   Sponsored by ACM SIGDA, with support from Altera, Xilinx, and Actel 

         Monterey Beach Hotel, Monterey, California
                February 9-11, 1997
          (Web page: http://www.ece.nwu.edu/~hauck/fpga97)

------------------------------------------------------------------------------
Welcome to the 1997 ACM/SIGDA International Symposium on Field-Programmable 
Gate Arrays (FPGA'97).  This annual symposium is the premier forum for 
presentation of advances in all areas related to FPGA technology, and 
also provides a relaxed atmosphere for exchanging ideas and stimulating
discussions for future research and development in this exciting new field.

This year's symposium sees a strong increase of interest in FPGA
technology, with over 20% increase in paper submissions.  The technical 
program consists of 20 regular papers, 35 poster papers, an evening panel,
and an invited session.   The technical papers present the latest results
on advances in FPGA architectures, new CAD algorithms and tools for FPGA 
designs, and novel applications of FPGAs.  The Monday evening panel
will debate whether reconfigurable computing is commercially viable.
The invited session on Tuesday morning addresses the challenges for 
architecture development, CAD tools, and circuit design of 
one million-gate FPGAs and beyond.

We hope that you find the symposium informative, stimulating, and enjoyable.

Carl Ebeling, General Chair   
Jason Cong, Technical Program Chair
------------------------------------------------------------------------------

SYMPOSIUM PROGRAM

Sunday February 9, 1997

6:00pm  Registration

7:00pm  Welcoming Reception,
        Monterey Beach Hotel, Monterey

Monday February 10, 1997

7:30am  Continental Breakfast/Registration

8:20am  Welcome and Opening Remarks

Session 1:  FPGA Architectures
Session Chair:  Rob Rutenbar, Carnegie Mellon Univ. 
Time:     8:30 - 9:30am

1.1   "Architecture Issues and Solutions for a High-Capacity FPGA",
      S. Trimberger, K. Duong, B. Conn, Xilinx, Inc. 

1.2   "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory 
      Arrays", 
      Steven J.E. Wilton, J. Rose, Z.G. Vranesic, University of Toronto

1.3   "Laser Correcting Defects to Create Transparent Routing for Large Area 
      FPGAs", 
      G.H. Chapman, B. Bufort, Simon Fraser University

Poster Session 1: Analysis and Design of New FPGA Architectures
Session Chair:  Tim Southgate, Altera, Inc.
Time:     9:30 - 10:30am (including coffee break)

Session 2:  FPGA Partitioning and Synthesis
Session Chair:  Richard Rudell, Synopsys, Inc. 
Time:     10:30 - 11:30am

2.1  "I/O and Performance Tradeoffs with the FunctionBus during Multi-FPGA 
     Partitioning", 
     F. Vahid, University of California, Riverside

2.2  "Partially-Dependent Functional Decomposition with Applications in FPGA
     Synthesis and Mapping", 
     J. Cong, Y. Hwang, Univ. of California, Los Angeles

2.3  "General Modeling and Technology-Mapping Technique for LUT-based FPGAs",
     A. Chowdhary, J.P. Hayes, University of Michigan

Poster Session 2:  Logic Optimization for FPGAs
Session Chair: Martine Schlag, Univ. of California, Santa Cruz
Time:     11:30 - 12noon

Lunch:    noon - 1:30pm

Session 3:  Rapid Prototyping and Emulation
Session Chair:  Carl Ebeling, Univ. of Washington
Time:     1:30 - 2:30pm

3.1  "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System",
     D.M. Lewis, D.R. Galloway, M. V. Ierssel, J. Rose, P. Chow, 
     University of Toronto

3.2  "Signal Processing at 250 MHz using High-Performance Pipelined FPGA's",
     Brian Von Herzen, Rapid Prototypes, Inc. 

3.3  "Module Generation of Complex Macros for Logic-Emulation Applications",
     Wen-Jong Fang, Allen C.H. Wu, Duan-Ping Chen, Tsinghua University

Poster Session 3: Novel FPGA Applications
Session Chair:  Brad Hutchings, Brigham Young Univ.
Time:     2:30 - 3:30pm (including coffee break)

Session 4:  Reconfigurable Computing
Session Chair:  Jonathan Rose, Univ. of Toronto
Time:     3:30 - 4:30pm 

4.1  "Wormhole Run-time Reconfiguration", 
     R. Bittner, P. Athanas, Virginia Polytechnic Institute

4.2  "Improving Computational Efficiency Through Run-Time Constant 
     Propagation",
     M.J. Wirthlin, B.L. Hutchings, Brigham Young University

4.3  "YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data 
     Processing",
     A. Tsutsui, T. Miyazaki, NTT Optical Network System Lab.

Poster Session 4:  Reconfigurable Systems
Session Chair: Scott Hauck, Northwestern Univ.
Time:     4:30 - 5:30pm

Dinner:   6:00 - 7:30pm

Evening Panel: Is reconfigurable computing commercially viable?
Moderator: Herman Schmit, Carnegie Mellon Univ.
Time:     7:30 - 9:00pm

Panelists: 
Steve Casselman: President, Virtual Computer Corp.
Daryl Eigen: President, Metalithic Systems, Inc.
Robert Parker: Deputy Director, ITO, DARPA
Peter Athanas: Assistant Professor, Virginia Polytechnic Institute
Robert Colwell: Pentium Pro Architecture Manager, Intel Corp.

In this panel session, we will try to address the questions of whether
there will be a mass-market for FPGA-based computing solutions.  Are
there large sets of applications whose performance requirements far
exceed that offered by microprocessors but which are only
occasionally executed?  Where are these applications?  Does the
ability to reconfigure during execution change the cost and
performance benefits of reconfigurable hardware significantly?  What
are the key challenges to making reconfigurable computing a reality,
and what can PLD manufacturers, system houses, government, and
academia do to overcome these obstacles?

Session 5:  FPGA Floorplanning and Routing
Session Chair:  Dwight Hill, Synopsys, Inc.
Time:     8:30 - 9:30am

5.1  "Synthesis and Floorplanning for Large Hierarchical FPGAs",
     H. Krupnova, C. Rabedaoro, G. Saucier, Institut National Polytechnique de 
     Grenoble/CSI

5.2  "Performance Driven Floorplanning for FPGA Based Designs",
     J. Shi, Dinesh Bhatia, University of Cincinnati

5.3  "FPGA Routing and Routability Estimation Via Boolean Satisfiability",
     R.G. Wood, R.A. Rutenbar, Carnegie Mellon University

Poster Session 5: High level Synthesis and Module Generation for FPGAs 
Session Chair:  Martin Wong,  Univ. of Texas at Austin
Time:     9:30 - 10:30am (including coffee break)

Session 6 (Invited):  Challenges for 1 Million-Gate FPGAs and Beyond
Session Chair:  Jason Cong, Univ. of California, Los Angeles
Time:     10:30am - noon

Process technology advances tell us that the one million gate FPGA will soon
be here, and larger devices shortly after that.  Current architectures
will not extend easily to this scale because of process characteristics and
because new opportunities are presented by the increase in available
transistors.  In addition, such large FPGAs will also present significant
challenges to the computer-aided design tools and methods.
Two invited papers address these issues.

6.1  "Architectural and Physical Design Challenges for One Million Gate FPGAs 
     and Beyond", 
     Jonathan Rose, University of Toronto, Dwight Hill, Synopsys, Inc.

6.2. "Challenges in CAD for the One Million-Plus Gate FPGA",
      Kurt Keutzer, Synopsys, Inc.

Lunch:    noon - 1:30pm

Session 7:  Studies of New FPGA Architectures 
Session Chair:  Steve Trimberger, Xilinx, Inc.
Time:     1:30 - 2:30pm

7.1  "A CMOS Continuous-time Field Programmable Analog Array",
     C.A. Looby, C. Lyden, National Microelectronics Research Center

7.2  "Combinational Logic on Dynamically Reconfigurable FPGAs",
     D. Chang, M. Marek-Sadowska, Univ. of California, Santa Barbara

7.3  "Generation of Synthetic Sequential Benchmark Circuits",
     M. Hutton, J. Rose, D. Corneil, University of Toronto

Poster Session 6:  FPGA Testing
Session Chair:  Sinan Kaptanoglu, Actel, Inc.
Time:     2:30 - 3:30pm (including coffee break)

Session 8:  Novel Design and Applications
Session Chair:  Pak Chan, Univ. of California, Santa Cruz
Time:     3:30 - 4:10pm

8.1  "Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency 
     Independent of Counter Size", 
     A.F. Tenca, M. D. Ercegovac,  Univ. of California, Los Angeles

8.2  "A FPGA-based Implementation of a Fault Tolerant Neural Architecture for 
     Photon Identification"
     M. Alderight, E.L. Gummati, V. Piuri, G.R. Sechi, Consiglio Nazionale delle
     Ricerche, Universita degli Studi di Milano, Politecnico di Milano

4:30pm Symposium Ends.

-------------------------------------------------------------------------------
Organizing Committee:

General Chair:    Carl Ebeling, University of Washington
Program Chair:    Jason Cong, UCLA
Publicity Chair:  Scott Hauck, Northwestern University
Finance Chair:    Jonathan Rose, University of Toronto
Local Chair:      Pak Chan, UC Santa Cruz 

Program Committee:

Michael Butts, Quickturn                   Pak Chan, UCSC
Jason Cong, UCLA                           Carl Ebeling, U. Washington         
Masahiro Fujita, Fujitsu Labs              Scott Hauck, Northwestern Univ.
Dwight Hill, Synopsys                      Brad Hutchings, BYU
Sinan Kaptanoglu, Actel                    David Lewis, U. Toronto
Jonathan Rose, U. Toronto                  Richard Rudell, Synopsys
Rob Rutenbar, CMU                          Gabriele Saucier, Imag
Martine Schlag, UCSC                       Tim Southgate, Altera
Steve Trimberger, Xilinx                   Martin Wong, UT Austin
Nam-Sung Woo, Lucent Technologies
-------------------------------------------------------------------------------

Hotel Information

FPGA'97 will be held at the Monterey Beach Hotel, 2600 Sand Dunes Dr.,
Monterey, CA 93940 USA.  The phone number for room reservations is
1-800-242-8627 (from USA or Canada) or +1-408-394-3321 (fax: +1-408-393-1912).  
Reservations must be made before January 10, 1997. Identify yourself with 
the group: ACM/FPGA'97 to receive the special rates of US$75 single/double 
for Gardenside and US$105 single/double for Oceanside (additional person 
in the room is $10), plus applicable state and local taxes.

Reservations may be canceled or modified up to 72 hours prior to arrival
without a penalty.  If the cancellation is made within 72 hours of arrival,
or you fail to show up, first nights room and tax will be charged.  If a
modification is made within 72 hours of arrival (i.e., postpones arrival or
departs earlier than reserved) the actual nights of your stay will be charged
at the quoted rack rate for the room occupied.
Check-in time is 4:00 pm, and check-out time is 12:00 noon.

Directions by car:  From San Jose (1.5 hours) or San Francisco Airport (2.5
hours) take Hwy 101 South to Hwy 156 West to Hwy 1 South.  From Hwy 1 South,
take Seaside/Del Rey Oaks exit. The hotel is at this exit on the ocean side.

You can also fly directly to Monterey Airport, which is served by United,
American and other airlines with at least 8 flights per day.

Monterey Area

The Monterey Peninsula is famous for its many attractions and recreational
activities, such as John Steinbeck's famous Cannery Row and the Monterey Bay
Aquarium.  Also, play one of 19 championship golf courses.  Charter fishing
is available right at Firsherman's Wharf. Monterey is renowned worldwide for
its spectacular coastline, including Big Sur and the Seventeen Mile Drive.
Recreational activities, shopping opportunities and restaurants abound.
-------------------------------------------------------------------------------

Registration Information:

The Symposium registration fee includes a copy of the symposium proceedings,
a reception on Sunday evening, February 9, coffee breaks, lunch on both days,
and dinner on Monday evening, February 10.

First Name:_____________________Last Name:_________________________________

Title/Job Function:________________________________________________________

Company/Institution:_______________________________________________________

Address:___________________________________________________________________

City:___________________________State:_____________________________________

Postal Code:____________________Country:___________________________________

E-mail:_________________________ACM Member #:______________________________

Phone:__________________________Fax:_______________________________________

Circle Fee           Before January 22, 1997      After January 22, 1997  

ACM/SIGDA Member      US$300                    US$370
*Non-Member           US$400            US$470
Student               US$ 90 (does not include reception or banquet, 
                     available for US$15 and US$55 respectively) 

Guest Reception Tickets:   # Tickets _____x US$15 = ______
Guest Banquet Tickets:     # Tickets _____x US$55 = _______

Total Fees: _________________ (Make checks payable to ACM/FPGA'97)

Payment included (circle one): American Express  MasterCard  Visa  Check

Credit Card # :_______________________  Expiration Date:________

Signature:______________________________________________________

Send Registration, including payment in full, to:

FPGA'97, Meeting Hall, Inc., 
571 Dunbar Hill Rd., 
Hamden, CT 06514 USA
Phone/fax: +1 203 287 9555

For registration information contact Debbie Hall via e-mail at 
halldeb@aol.com. Cancellations must be in writing and received 
by Meeting Hall, Inc. before January 22, 1997.
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of ECE                        Voice: (847) 467-1849                |
|  Northwestern University             FAX: (847) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@ece.nwu.edu             |
|  Evanston, IL  60208                 WWW: http://www.ece.nwu.edu/~hauck   |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 5296
Subject: Re: What Does ASIC Stand For?
From: convidat@upvnet.upv.es (Usuario Invitado)
Date: 5 Feb 1997 08:22:38 GMT
Links: << >>  << T >>  << A >>
In article <32E6A349.8E7@cat.com>, Chuck Morrill <morrica@cat.com> wrote:
>Interesting.  What's that in English?

In short:
ASIC: Application-Specific Integrated Circuit. 

Enrique
Valencia, Spain.
Article: 5297
Subject: Re: Safety Critical Apps -> Xilinx Checker.
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 5 Feb 1997 09:50:44 GMT
Links: << >>  << T >>  << A >>
In article <5d5gjt$165b@watnews1.watson.ibm.com> kgold@watson.ibm.com (K Goldman) writes:
>
>fliptron@netcom.com (Philip Freidin) writes:
>|> Brian reminds us that the XC4K readback includes a CRC, and by setting 
>|> the appropriate option, and not using the CLB RAM capability, the CRC 
>|> value will be constant, and can be read back continuously, using only 
>|> internal resources. The compare need only be done between the readback 
>|> CRC, and a constant copy kept somewhere else.
>|> 
>|> He goes on to suggest that the compare (and I assume the reference copy 
>|> of the CRC) might also be done on chip. I have thought about this for a 
>|> few years, and I suspect but can not prove, that this is not possible. 
>|> The reason is that the storing of a reference CRC value on chip will 
>|> permute the calculated CRC. If you then change the reference value to the 
>|> new value, it will just permute again. I suspect you may be able to play 
>|> this silly game forever. 
>|> 
>|> Reference: Patent 5,321,704
>|> 
>|> Recomendation: Store the reference CRC outside the FPGA.
>
>If a lurker may barge in ...
>
>There are ways to append a generated CRC to a serial bit stream such
>that, when the receiver checks the total CRC including the generated
>CRC, a _constant_ magic number results when there are no errors.
>
>See, for example, C Programmer's Guide to Serial Communications"
>by Joe Campbell, for details.
>
>-- 
>Ken Goldman   kgold@watson.ibm.com   914-945-1466

This wont work in this case because the adding of the check value to the
logic in the FPGA will permute the CRC so it will not match. There is no
facility for adding a check value that does not cause this permutation to
take place. Really. If you want to check the bitstreams this way, you will
have to store the calculated CRC outside the FPGA. The actual compare 
logic, and the timing and counting logic can be in the FPGA.

Philip.

Article: 5298
Subject: US-GA-ATL- ASIC DESIGN ENGINEER
From: anthony_dozier@systemone.com (Anthony Dozier)
Date: Wed, 05 Feb 1997 14:53:17 GMT
Links: << >>  << T >>  << A >>
Job Title:  ASIC DESIGN ENGINEER

Job/Skill Requirements: 
BSEE or MSEE.
Must have 2+ years experience with ASIC design, 
Should have experience with Synopsis and Verilog or VHDL.
FPGA experience is a plus, 
Knowledge of C/C++, MPEG2, or ATM is a plus.

Job Description:
Development, design, modification, & verification of 
complex digital integrated circuits and FPGA’s for 
video & data services.
Product architecture, development of design methodology,
circuit design & prototype debugging.

Compensation:  45k to 70k, depending on experience
 
Duration:  Permanent

Jobsite location:  Atlanta, GA

Start date:  ASAP

For the above position, please respond by telephone & fax resume to:

NOTE:  To ensure receipt of your resume, it must be ASCII format


__ Anthony Dozier  _________________
    (Placement Specialist)


Internet:  anthony_dozier@systemone.com

Fax:  404-252-0073

Phone:  404 255-5004 x105

System One Technical
5775 Peachtree Dunwoody Rd
Suite B220
Atlanta, GA  30342


Article: 5299
Subject: CFP: Int. Workshop on Logic Synthesis, 97 (Deadline Extended)
From: sharad@new-delhi.Princeton.EDU (Sharad Malik)
Date: 5 Feb 1997 15:11:21 GMT
Links: << >>  << T >>  << A >>
           1997 IEEE/ACM International Workshop on Logic Synthesis

		http://www.ee.princeton.edu/iwls97.html

                 Granlibakken Resort, Lake Tahoe, California

                              May 18-21 , 1997


                           Call for Participation

		Submission Deadline extended to March 1, 1997

(Papers submitted to IWLS are eligible for submission to ICCAD.)

Contents

  1. Synopsis
  2. Benchmarks
  3. About IWLS
  4. About Granlibakken
  5. Executive Committee
  6. Technical Program Committee
  7. Sponsored by...

Synopsis

Logic Synthesis has traditionally focused on optimization techniques for
combinational and sequential circuits through the manipulation of Boolean
equations and state machines. IWLS '97, the sixth workshop in this series,
seeks presentations both on these topics and on new directions in
synthesis-based design methodology. Topics of interest include:

   Area, timing, power optimization              Logic synthesis systems

   CMOS, ECL, GaAS Optimization       Designer Experiences with Synthesis

   Two-level Logic Optimization          Interaction with physical design

   Multi-level Logic Optimization       Incremental Synthesis/ECO Support

   FSM Optimization                          Asynchronous Logic Synthesis

   Sequential Circuit Optimization                    Formal Verification

   Retiming and resynthesis                 Optimization at the RTL Level

   Technology Mapping                                 Timing Verification

   FPGA and PLD Synthesis                  Testing and Synthesis for test

   Don't-Cares and Boolean Relations   Interaction with module generators

   Symbolic Synthesis                Use of synthesis in new applications

   Synthesis in FPGA-Based Emulation                  Applications of SAT

Authors may submit extended abstracts for their proposed presentation. These
must be no less than 1000 words and no more than 2500 words. These abstracts
are not intended to be complete papers, but rather should convey the main
ideas of the proposed presentation. We encourage submissions in the early
stages of research which may highlight important new problems without
necessarily providing complete solutions. The abstracts may be submitted by
e-mailing self-contained Postscript files to iwls-submit@ee.princeton.edu by
March 1, 1997.  Acceptance notices will be sent by March 31, 1997. A set
of workshop notes will be distributed at the conference. There will be no
published proceedings.

Benchmarks

A benchmark set is being assembled by the CAD Benchmarking Laboratory. To
contribute new benchmarks, or to obtain information about the existing
suite, please write: benchmarks@cbl.ncsu.edu.

About IWLS

IWLS '93 and IWLS '95 introduced a number of format changes from previous
workshops, which the committee tentatively intends to maintain for IWLS '97.
These include an open program with high acceptance rate, heavy use of
posters and short talks for presentation, and large amounts of time in the
schedule for poster presentations. In addition, IWLS '97 will emphasize open
discussions and ongoing research which are not provided by the traditional
conference format.

About Granlibakken

The Granlibakken Conference Center is located in Tahoe City on the west
shore of Lake Tahoe, 180 miles east of San Francisco. It boasts 160 rooms,
clustered into two- and three-bedroom condominiums. Each bedroom is an
attractive hotel room with private bath. Many of the clusters share a
kitchen, living room and dining room -- a miniature lobby for private
meetings. Organizations sending several people to the workshop may wish to
rent entire two- and three-bedroom townhouses.

The Granlibakken management has reserved space on Thursday, May 22 for
organizations who wish to hold private, one-day workshops immediately
preceding IWLS, and have agreed to charge organizations the IWLS conference
rate for these meetings. Contact Mary Brown at Granlibakken sales
(1-800-552-4494) for details. Granlibakken is within 10 minutes' drive of
the West's premier ski resorts: Alpine Meadows and Squaw Valley USA. When
California enjoys high snowfall, both areas remain open until Memorial Day.
A wealth of hiking trails snake through the area. Weather permitting,
Granlibakken's tennis courts and pool will be open for use.

The weather in late May is variable; warm, sunny days and cool clear nights
are the rule.

Getting There

Granlibakken is easily reached from either the San Francisco Bay Area or
Reno, NV. Take Interstate 80 to Truckee. From there, follow State Route 89
south to Tahoe City. Turn right at the stop light in Tahoe City. After 1/4
mile, turn right on Granlibakken road and proceed to the end.

Contacts/Executive Committee

 General Chair   Rick     Cadence       mcgeer@cadence.com      (408)
                 McGeer   Berkeley Labs                         428-5325
 Tech. Program   Sharad   Princeton                             (609)
 Chair           Malik    University    sharad@ee.princeton.edu 258-4625
 Benchmark       Franc                                          (919)
 Chair           Brglez   NCSU          brglez@cbl.ncsu.edu     248-1925
 Conference      Kris     Cadence                               (408)
 Coordinator     Lamanno  Berkeley Labs krisl@cadence.com       894-2479

Technical Program Committee

      Pranav Ashar         NEC
      Michel Berkelaar     TU-Eindhoven
      Robert K. Brayton    UC Berkeley
      Franc Brglez         NCSU
      Giovanni de Micheli  Stanford
      Srinivas Devadas     MIT
      Ewald Detjens        Mentor Graphics
      Antun Domic          Cadence
      Masahiro Fujita      Fujitsu Laboratories of America
      Wolfgang Kunz        University of Potsdam
      Luciano Lavagno      Politecnico di Torino/Cadence Berkeley Labs
      Ken McElvain         Synplicity
      Rick McGeer          Cadence Berkeley Labs
      Sharad Malik (chair) Princeton University
      Shin-ichi Minato     NTT
      Massoud Pedram       USC
      Richard Rudell       Synopsys
      Tsutomu Sasao        Kysushu Institute of Technology
      Gabriele Saucier     INPG
      Ellen Sentovich      Cadence Berkeley Labs
      Fabio Somenzi        University of Colorado
      Leon Stok            IBM TJ Watson Research Center

Sponsor

Sponsored by the IEEE Computer Society, Technical Committee on VLSI. In
co-operation sponsoship by ACM/SIGDA is being sought.
-- 
Sharad Malik                            sharad@ee.princeton.edu
Associate Profesor                      609-258-4625
Dept. of Electrical Engineering         609-258-3745 Fax
Princeton University                    http://www.ee.princeton.edu/~sharad


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