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Messages from 5200

Article: 5200
Subject: Re: FPGA Lab.
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 30 Jan 1997 18:56:50 GMT
Links: << >>  << T >>  << A >>


Tim Hubberstey <tim_hubberstey@mindlink.bc.ca> wrote in article
<tim_hubberstey.95.32F030CF@mindlink.bc.ca>...
> I recommend that you look at the Synopsys FPGA compiler for the PC (I
can't 
> remember the exact name). We do our design work in VHDL and until
recently had 
> been using Viewlogic but we found it to be such a pain to work with (both

> Windows and Unix versions!) that we dumped it completely and switched (at

> great expense) to Synopsys. Our gate counts immediately dropped by at
least 
> 30% and the timing improved by a similar margin. 
> 
The PC equivalent of the Synopsys FPGA compiler is called FPGA Express. 
You can find out more information at:

http://www.synopsys.com/products/fpga_pc/fpga_pc.html

Synopsys is quite liberal with demo CD-ROMs and it's definitely worth a
look.  For us non-university folks, it about $13,000 list price with one
language supported and one device optimizer.
-- 
Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic
Article: 5201
Subject: Reconfigurable Logic Query
From: Ed Vogel <epv@pcsi.cirrus.com>
Date: Thu, 30 Jan 1997 11:43:15 -0800
Links: << >>  << T >>  << A >>
I am considering the design of a dynamically reconfigurable logic 
platform. It is more in line with tinkering than a serious product 
application. Has anyone else tried to build an in circuit programmable 
interface inside an FPGA or CPLD? 

  I realize that Lattice offers something of this sort(pseudo JTAG port) 
but I want to go one step further; to make connections between "user 
defined" muxes surrounding "user defined" logic blocks. In short I want 
to waste the resources provided for me by the chip manufacturer and third 
party tool designers to functionally design and program an FPGA or CPLD 
in favor of using those resources to build a "scaffolding" inside to 
facilitate the construction of dynamically reconfigurable logic. I 
realize this is wasteful. I want control over routing delays and 
repeatability without consulting a third party. It also would allow 
greater flexibility in interfacing to C compiler outputs. Just curious. . 
.
Article: 5202
Subject: Re: Reconfigurable Logic Query
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 30 Jan 1997 13:42:45 -0700
Links: << >>  << T >>  << A >>
It is not clear to me what this posting really means, but I might point
out that all Xilinx FPGAs are configured by loading bits into latches,
and they can therefore be re-configured on the board within milliseconds
and an unlimited number of times. 
Also, the XACT development system ( you need it, at least the simplest
and cheapest version of it) allows you to tinker with the available
resources to your heart's content. Any feature that the silicon is able
to do is also available to you.
For detailed product information, look at our web site ( www.xilinx.com
)

Peter Alfke, Xilinx Applications
Article: 5203
Subject: Altera BitBlaster
From: Steve Schossow <ss@tisc.com>
Date: Thu, 30 Jan 1997 13:48:46 -0800
Links: << >>  << T >>  << A >>
I've been using the Altera FPGAs for 6 months or so and one of the first
things that bugged me was the cost of the BitBlaster.  $200 for a little
box (with an Altera FPGA in it no less) just to download the parts.

So I dabble in programming and wrote a short program to wiggle a couple
of bits on the printer port to download my 81188 and 10K50 parts.

It works great and is at least as fast as the BitBlaster.  It reads the
design's .ttf file created when you do place and route.

Any interest?  I'll e-mail or post depending on how many responses I
get.
Article: 5204
Subject: Re: Altera support better than Xilinx
From: zx80@dgiserve.com (Peter)
Date: Thu, 30 Jan 1997 22:31:13 GMT
Links: << >>  << T >>  << A >>

>And bye-bye to support if you need it, since most companies don't want to 
>support old versions of software when bugs have been fixed in later versions.

This applies to all software eventually. The stuff you buy today will
be unsupported in say 4 years' time, just like the stuff you bought 4
years ago is unsupported now. Nothing ever changes.

Is comes down to a financial and time decision: do you want to keep
paying the annual "maintenance" to always have the latest, and do you
then want to put in the time to learn of the changes, discover new
bugs - even when the work you do may not need the latest version.

But this is an old argument...


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5205
Subject: Re: Xilinx/Synario question
From: Brian Philofsky <brianp@xilinx.com>
Date: Thu, 30 Jan 1997 14:40:45 -0800
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> Also: Do any of you Xilinx users out there know where I can get a
> description of the XNF file syntax ? Or is this still a deep dark
> secret?

The xnf spec version 6.1 is on our FTP site at :

ftp://ftp.xilinx.com/pub/documentation/xnfspec.pdf

And the 7K and 9K family addendum which sound like what you are
interested in :

ftp://ftp.xilinx.com/pub/documentation/xnf61_7k.pdf

Finally, postscript versions of these files are at :

ftp://ftp.xilinx.com/pub/documentation/xnfspecs_61.tar.Z

-- 
----------------------------------------------------------------------------
 / 7\'7 Brian Philofsky   (brian.philofsky@xilinx.com)
 \ \ `  Xilinx Technical Applications Engineer   hotline@xilinx.com
 / /    2100 Logic Drive                         1-800-255-7778
(toll-free)
 \_\/.\ San Jose, California 95124-3450          1-408-879-5199 
----------------------------------------------------------------------------
Article: 5206
Subject: Re: Reconfigurable Logic Query
From: Steve Casselman <sc@vcc.com>
Date: Thu, 30 Jan 1997 23:58:45 GMT
Links: << >>  << T >>  << A >>
Ed Vogel wrote:
> 
> I am considering the design of a dynamically reconfigurable logic
> platform. It is more in line with tinkering than a serious product
> application. Has anyone else tried to build an in circuit programmable
> interface inside an FPGA or CPLD?
> 
>   I realize that Lattice offers something of this sort(pseudo JTAG port)
> but I want to go one step further; to make connections between "user
> defined" muxes surrounding "user defined" logic blocks. In short I want
> to waste the resources provided for me by the chip manufacturer and third
> party tool designers to functionally design and program an FPGA or CPLD
> in favor of using those resources to build a "scaffolding" inside to
> facilitate the construction of dynamically reconfigurable logic. I
> realize this is wasteful. I want control over routing delays and
> repeatability without consulting a third party. It also would allow
> greater flexibility in interfacing to C compiler outputs. Just curious. .
> .
Well....:) I just read a simular paper where the design was
reconfigurable
switches and 2-bit processors. You want to prototype a FPGA in an FPGA.
Sounds
very feasible for a small device. Now if you wanted to emulate an
emulator 
that might be a different story.

You might look to my newest most favorite page 
http://dec.bournemouth.ac.uk/dec_ind/decind6/drhw_page.html
For all you old timers: check this page out it is really very good.

Steve Casselman
http://www.vcc.com/hotann.html  
The IBM PC of Reconfigurable Computing (TM)
Article: 5207
Subject: What is the different between FPGA and CPLD?
From: man cheng <m.cheung@auckland.ac.nz>
Date: Fri, 31 Jan 1997 13:14:49 +1300
Links: << >>  << T >>  << A >>
Dear everybody,

Can any expect here tell me what is the different between FPGA and CPLD?
Thanks
-- 
Thank you for your kind attention.                  
 
SAM CHENG
Article: 5208
Subject: DES Challenge
From: Steve Casselman <sc@vcc.com>
Date: Fri, 31 Jan 1997 01:40:00 GMT
Links: << >>  << T >>  << A >>
Whould the person who last posted the address of Michael J. Wieners
paper "Efficient DES Key Search" please post the address of that
paper. I have a printout of hte paper but no address to let others
know where to pick it up. The Challenge is on and the 40-bit key
has been broken ($1,000) The next key is 48-bits. The paper has a
gate level schematic in it and says it takes 2500 registers for a
fully pipelined version.

Steve Casselman
Article: 5209
Subject: Re: FPGA Lab.
From: yeller4505@aol.com (Yeller4505)
Date: 31 Jan 1997 05:29:29 GMT
Links: << >>  << T >>  << A >>
I think you should also look at Exemplar's Galileo. it's VITAL compliant
and is integrated with timing analysis and MTI's V-System simulator. It
supports all the major programmalbe vendors. University deals are
available. See their web page at www.exemplar.com
Article: 5210
Subject: Re: Altera support better than Xilinx
From: garyk@svpal.svpal.org (George Noten)
Date: 31 Jan 1997 06:26:29 GMT
Links: << >>  << T >>  << A >>
Peter (zx80@dgiserve.com) wrote:

: >  Orcad with Xilinx library and Xact

: Interesting. Was this SDT/386? And how did you manage with simulation?

 I did not.

: The main reason I am keeping the ancient Viewlogic stuff is that it
: has a good simulator. My experience of VST was very bad.

 I knew it and did not even try.  I switched to ViewLogic about 4 years
 ago.

	George.
Article: 5211
Subject: Re: Altera support better than Xilinx
From: garyk@svpal.svpal.org (George Noten)
Date: 31 Jan 1997 06:51:06 GMT
Links: << >>  << T >>  << A >>
Wayne Turner (waynet@goodnet.com) wrote:

: WRONG!!!!!  There is NO receptionist at the Altera help-line, at least in the 
: United States.  You will be on hold until someone is available
 
 Excellent!!  Just 5 or 10 or 20 minutes on hold and that's it.

: and the person who comes on the line is an applications engineer, NOT a 
: receptionist.

 And then he plays the usual routine : "Please-send-me-your-code-and-
 I-will-take-a-look-at-it".  Why waste time?  I can do it before he asks.
 In my experience email is more effective than phone calls provided the
 customer support uses it properly.  Last time I checked (about a year
 ago) Xilinx did it better.  BTW another company that gave me very good
 support by email was Atmel.  They have much less resources than Altera
 or Xilinx but they did their best.


: What is their option?  Build a fab to make FlashLogic?  They are put in the 
: same situation as you are.  Obsolescence happens.

 They could absorb part of the costs.  Or think twice before they bought
 the part.  Or think three times before they converted it from EPROM to
 FLASH.


: > Yes, but this part never got out of "preliminary" category and there are
: > no customers that were using it for years.

: Does it matter how long people were using it?  

 Yes.  The longer the part is available the more designs are utilizing it.

: If it does, how long had people 
: been using FLASHlogic, considering it has only been around for a few years 
: (and owned by Altera for less than two)?
 
 For our company it was long enough to use it in about half of our products.
 
: No, it wasn't.  If your wafer supplier won't make the wafer anymore, what can 
: you do if they are the only fab with that technology?

 Don't make customers pay for it.  Especially if there are so few of them as
 we are being told.

	George.
Article: 5212
Subject: Re: What is the different between FPGA and CPLD?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 30 Jan 1997 22:59:08 -0800
Links: << >>  << T >>  << A >>
man cheng wrote:
> 
> Dear everybody,
> 
> Can any expect here tell me what is the different between FPGA and CPLD?
> Thanks
> --
> Thank you for your kind attention.
> 
> SAM CHENG
Simplistically speaking, the difference is in the architecture.  An FPGA
is an array of relatively simple configurable logic cells. The smallest
arrays are about 8 x 8 cell matrices. Each cell in the FPGA typically
has a small number of inputs (2 to 9 depending on the device) and
somewhat limited routing between cells.  Each cell has typically has at
least one flip flop (there is an exception that uses a combination of
two adjacent cells to construct a flip-flop).  The resulting
architecture is rich in registers, but is not well suited for wide high
speed combinatorial stuff.  In contrast, the CPLD structure is generally
more like that of a traditional PAL, where each "macrocell" consists of
a register and some form of an and-or logic array.  The number of
macro-cells is small compared to the number of logic cells in an FPGA,
but the cells can handle fairly wide combinatorial functions with no
speed penalty.  The macrocells are usually interconnected with some form
of global routing resource.  

Hope the short answer is helpful.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 5213
Subject: Steven K. Knapp - no such article
From: Aage Farstad <aage.farstad@ffi.no>
Date: Fri, 31 Jan 1997 09:51:09 +0100
Links: << >>  << T >>  << A >>
Hi all,

Can anybody give me a hint of what's wrong with my newsreader? Every
time I try to open a message from this guy, my newsreader (netscape3.0)
says: No Such article, Perhaps the article has expired! He is the only
one treated this way!

Best Regards Aage Farstad

aage.farstad@ffi.no
Article: 5214
Subject: Re: What is the different between FPGA and CPLD?
From: rick@camden.algor.co.uk (Rick Filipkiewicz)
Date: 31 Jan 1997 10:49:29 GMT
Links: << >>  << T >>  << A >>
Ray Andraka (randraka@ids.net) wrote:
: man cheng wrote:
: > 
: > Dear everybody,
: > 
: > Can any expect here tell me what is the different between FPGA and CPLD?
: > Thanks
: > --
: > Thank you for your kind attention.
: > 
: > SAM CHENG
: Simplistically speaking, the difference is in the architecture.  An FPGA
: is an array of relatively simple configurable logic cells. The smallest
: arrays are about 8 x 8 cell matrices. Each cell in the FPGA typically
: has a small number of inputs (2 to 9 depending on the device) and
: somewhat limited routing between cells.  Each cell has typically has at
: least one flip flop (there is an exception that uses a combination of
: two adjacent cells to construct a flip-flop).  The resulting
: architecture is rich in registers, but is not well suited for wide high
: speed combinatorial stuff.  In contrast, the CPLD structure is generally
: more like that of a traditional PAL, where each "macrocell" consists of
: a register and some form of an and-or logic array.  The number of
: macro-cells is small compared to the number of logic cells in an FPGA,
: but the cells can handle fairly wide combinatorial functions with no
: speed penalty.  The macrocells are usually interconnected with some form
: of global routing resource.  

: Hope the short answer is helpful.

: -Ray Andraka, P.E.
: Chairman, the Andraka Consulting Group
: 401/884-7930     Fax 401/884-7950
: email randraka@ids.net
: http://www.ids.net/~randraka

Probably the major difference between the two types is that CPLDs, or
``fat PALs'', have very simple and predicatable pin-to-pin
timing. This means that, within fairly tight bounds, recompiling &
rerouting a design won't cause speed varitions in the resulting
device. FPGAs on the other hand have a large amount of internal
resource and variable routing delays. Keeping a given performance
level over design changes can be difficult and is highly dependent on
the efficacy of the vendor's floor planning and place/route tools.

I think a rule of thumb might be to use FPGAs for ``rigid'' devices
like data paths, arithmetic units etc. or for non-speed critical bits
of random logic. CPLDs are better suited to the high clock rate
control logic that might have to be rebuilt frequently during the
prototype phase.

CPLDs are also a lot cheaper!

 _________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England
Article: 5215
Subject: Newbie Q about Viewlogic and Altera tools
From: richard.young@crc.doc.ca (Richard Young)
Date: 31 Jan 1997 13:29:12 GMT
Links: << >>  << T >>  << A >>
I'm planning to jump into the programmable logic design arena in order to 
implement DSP and FEC algorithms that surpass the capability of programmable 
DSPs.  I'm going to follow the Altera family of devices and have ordered their 
development tools (MAX-II Plus): graphic entry, VHDL input option, compiler, 
simulator, timing analyzer etc.  

I've seen from this newsgroup that a large number of people use a tool called 
Viewlogic.  What is the difference between the tools offered by Altera and 
those from Viewlogic.

Thanks.

Richard Young
Signal Processing Engineer
Communications Research Centre,
Ottawa, Canada
richard.young@crc.doc.ca

Article: 5216
Subject: Re: DES Challenge
From: Christophe Beaumont <beaumont@univ-brest.fr>
Date: Fri, 31 Jan 1997 14:45:14 +0100
Links: << >>  << T >>  << A >>
Hi Steve,

I'm not sure it is the easiest way of getting a copy of this paper,
but I just downloaded the 107 kBytes gzipped postscript file from 
Japan at the following address:

http://www.aist-nara.ac.jp/Security/doc/paper/wiener.deskeysearch.ps.gz

Sure this will help!

Salut

Chris.
-- 
Christophe Beaumont ( http://ubolib.univ-brest.fr/~beaumont )
Laboratoire d'Informatique de Brest
Projet ArMen        ( http://ubolib.univ-brest.fr/ )
Article: 5217
Subject: US-GA-ATL- ASIC DESIGN ENGINEER
From: anthony_dozier@systemone.com (Anthony Dozier)
Date: Fri, 31 Jan 1997 13:58:40 GMT
Links: << >>  << T >>  << A >>
Job Title:  ASIC DESIGN ENGINEER

Job/Skill Requirements: 
BSEE or MSEE.
Must have 2+ years experience with ASIC design, 
Should have experience with Synopsis and Verilog or VHDL.
FPGA experience is a plus, 
Knowledge of C/C++, MPEG2, or ATM is a plus.

Job Description:
Development, design, modification, & verification of 
complex digital integrated circuits and FPGA’s for 
video & data services.
Product architecture, development of design methodology,
circuit design & prototype debugging.

Compensation:  45k to 70k, depending on experience
 
Duration:  Permanent

Jobsite location:  Atlanta, GA

Start date:  ASAP

For the above position, please respond by telephone & fax resume to:

NOTE:  To ensure receipt of your resume, it must be ASCII format


__ Anthony Dozier  _________________
    (Placement Specialist)


Internet:  anthony_dozier@systemone.com

Fax:  404-252-0073

Phone:  404 255-5004 x105

System One Technical
5775 Peachtree Dunwoody Rd
Suite B220
Atlanta, GA  30342


Article: 5218
Subject: Re: Altera BitBlaster
From: waynet@goodnet.com (Wayne Turner)
Date: Fri, 31 Jan 97 14:56:33 GMT
Links: << >>  << T >>  << A >>
In article <32F1173E.43A8@tisc.com>, Steve Schossow <ss@tisc.com> wrote:
>I've been using the Altera FPGAs for 6 months or so and one of the first
>things that bugged me was the cost of the BitBlaster.  $200 for a little
>box (with an Altera FPGA in it no less) just to download the parts.
>
>So I dabble in programming and wrote a short program to wiggle a couple
>of bits on the printer port to download my 81188 and 10K50 parts.
>
>It works great and is at least as fast as the BitBlaster.  It reads the
>design's .ttf file created when you do place and route.
>
>Any interest?  I'll e-mail or post depending on how many responses I
>get.

Altera now has a ByteBlaster that does the same thing.  It is (and yours 
should be as well) quite a bit faster than the BitBlaster since the BitBlaster 
was limited by the UART in your PC/workstation, which is quite a bit slower 
than a parallel port.  They still charge you $150 for the ByteBlaster though, 
just so you know where yours might fit in.

Wayne
Article: 5219
Subject: Re: Altera support better than Xilinx
From: waynet@goodnet.com (Wayne Turner)
Date: Fri, 31 Jan 97 14:57:32 GMT
Links: << >>  << T >>  << A >>
In article <32f7f5b2.24840008@news.alt.net>, zx80@dgiserve.com (Peter) wrote:
>
>>And bye-bye to support if you need it, since most companies don't want to 
>>support old versions of software when bugs have been fixed in later versions.
>
>This applies to all software eventually. The stuff you buy today will
>be unsupported in say 4 years' time, just like the stuff you bought 4
>years ago is unsupported now. Nothing ever changes.
>
>Is comes down to a financial and time decision: do you want to keep
>paying the annual "maintenance" to always have the latest, and do you
>then want to put in the time to learn of the changes, discover new
>bugs - even when the work you do may not need the latest version.
>
>But this is an old argument...

True. Both what you said at the beginning AND the fact that it is an old 
argument ;)

Wayne
Article: 5220
Subject: Re: Altera support better than Xilinx
From: waynet@goodnet.com (Wayne Turner)
Date: Fri, 31 Jan 97 15:10:10 GMT
Links: << >>  << T >>  << A >>
In article <5cs4oq$cf5@borg.svpal.org>, garyk@svpal.svpal.org (George Noten) wrote:
>Wayne Turner (waynet@goodnet.com) wrote:
>
>: WRONG!!!!!  There is NO receptionist at the Altera help-line, at least in the
> 
>: United States.  You will be on hold until someone is available
> 
> Excellent!!  Just 5 or 10 or 20 minutes on hold and that's it.

My experience has been less than five minutes.  And by the way, what happened 
to your "receptionist" claim?

>: and the person who comes on the line is an applications engineer, NOT a 
>: receptionist.
>
> And then he plays the usual routine : "Please-send-me-your-code-and-
> I-will-take-a-look-at-it".  Why waste time?  I can do it before he asks.
> In my experience email is more effective than phone calls provided the
> customer support uses it properly.  Last time I checked (about a year
> ago) Xilinx did it better.  BTW another company that gave me very good
> support by email was Atmel.  They have much less resources than Altera
> or Xilinx but they did their best.

The point of the help desk is not tell you how to write code; go to college 
for that.  The point is to help people with specific issues in using the tools 
or devices.  If you have code that is crashing the software, then they want it 
so they can fix it for next release.  Most of the issues I had to call about 
were resolved over the phone at the time that I called.

>: What is their option?  Build a fab to make FlashLogic?  They are put in the 
>: same situation as you are.  Obsolescence happens.
>
> They could absorb part of the costs.  Or think twice before they bought
> the part.  Or think three times before they converted it from EPROM to
> FLASH.

1.  They are absorbing part of the costs by making a large end-of-life buy on 
wafers.

2.  Do you think they would have bought the part if they knew 2 years down the 
road that Sharp wasn't going to want to make it anymore?

3.  Converted?  What the hell are you talking about?  It was FLASH when Intel 
owned it, it was just called FlexLogic.  When Altera bought it they had to 
change the name because they already had the FLEX 8000 family and didn't want 
it to be confused.  So they named the part according to what it really was: 
FLASH.  Hence the name FlashLogic.

Perhaps you should come back after you've read up a bit.

>: > Yes, but this part never got out of "preliminary" category and there are
>: > no customers that were using it for years.
>
>: Does it matter how long people were using it?  
>
> Yes.  The longer the part is available the more designs are utilizing it.

And how long was it out?

>: If it does, how long had people 
>: been using FLASHlogic, considering it has only been around for a few years 
>: (and owned by Altera for less than two)?
> 
> For our company it was long enough to use it in about half of our products.

What is the product life?  The parts will be available to be shipped for 
another year and a half.  Is that not long enough notice?
 
>: No, it wasn't.  If your wafer supplier won't make the wafer anymore, what can
>: you do if they are the only fab with that technology?
>
> Don't make customers pay for it.  Especially if there are so few of them as
> we are being told.

You didn't answer the question.

Wayne
Article: 5221
Subject: Altera designers - look here!
From: Rune Baeverrud <r@acte.no>
Date: Fri, 31 Jan 1997 16:24:03 +0100
Links: << >>  << T >>  << A >>
Hello all Altera designers!

I would like to promote the idea of a FreeCore Library. The FreeCore
Library consists of free, parameterizable building blocks for Altera
programmable logic that can be used in your design for absolutely free!

My first contribution is the parameterizable Compact UART. This is a
simple, complete and compact UART. An 8-bit UART may consume as little
as 63 logic cells in a FLEX 8000 or FLEX 10K architecture, including
transmitter, receiver and baud rate generator.

The documentation and download page is available at:

http://www.geocities.com/SiliconValley/Lakes/3656/

Please give me your feedback on the FreeCore philosophy. I plan to set
up a FreeCore site soon, and I hope that you, the designers and
application guys, would like to contribute to the library.

What kind of functions would you like to see in the FreeCore library? 

I'm planning my next release soon: A single master I2C (I squared C)
controller.

NOTE:
Although I work as a Field Application Engineer for one of the Altera
distributors, I would like to state that this is totally my personal
initiative. Altera is not involved in any way.
Article: 5222
Subject: Altera designers - look here!
From: Rune Baeverrud <r@acte.no>
Date: Fri, 31 Jan 1997 16:42:57 +0100
Links: << >>  << T >>  << A >>
Hello all Altera designers!

I would like to promote the idea of a FreeCore Library. The FreeCore
Library consists of free, parameterizable building blocks for Altera
programmable logic that can be used in your design for absolutely free!

My first contribution is the parameterizable Compact UART. This is a
simple, complete and compact UART. An 8-bit UART may consume as little
as 63 logic cells in a FLEX 8000 or FLEX 10K architecture, including
transmitter, receiver and baud rate generator.

The documentation and download page is available at:

http://www.geocities.com/SiliconValley/Lakes/3656/

Please give me your feedback on the FreeCore philosophy. I plan to set
up a FreeCore site soon, and I hope that you, the designers and
application guys, would like to contribute to the library.

What kind of functions would you like to see in the FreeCore library? 

I'm planning my next release soon: A single master I2C (I squared C)
controller.

NOTE:
Although I work as a Field Application Engineer for one of the Altera
distributors, I would like to state that this is totally my personal
initiative. Altera is not involved in any way.
Article: 5223
Subject: Re: Steven K. Knapp - no such article
From: "R. T. Wurth" <rwurth@att.com>
Date: Fri, 31 Jan 1997 12:36:32 -0500
Links: << >>  << T >>  << A >>
=?iso-8859-1?Q?Bj=F8rn?= B. Larsen wrote:
> 
> Aage Farstad wrote:
> >
> > Can anybody give me a hint of what's wrong with my newsreader? Every
> > time I try to open a message from this guy, my newsreader (netscape3.0)
> > says: No Such article, Perhaps the article has expired! He is the only
> > one treated this way!
> 
> The same happens to me!
> 
> I am also using Netscape 3.0 now.
> 
> Bjørn BL.
>


I noticed it too, with netscape 2.?.  I did manage to see one of his 
articles using trn on a UNIX box, and it has a special character in 
the message-id field.  (No, I don't recall exactly what:  perhaps one 
of {#$%}).  I could tell that was the problem, because the netscape 
error message indicated the message-id, and the indicated message-id 
was truncated starting with the offending character.  

So, Steve, if you want Netscape users to read your messages, see if you 
can somehow get your software and/or ISP to provide a message-id.  I 
suspect that somewhere there is an Internet RFC specifying the grammar 
for parsing this field, that most newsreader-writers decided to be 
generous in accepting errors, and that Netscape is being technically 
correct (but wrong from a software engineering viewpoint) in rejecting 
them.

Perhaps this should be further considered somewhere in the 
news.software.*, or news.admin.* hierarchies.

-- 
   R. T. Wurth / (w) Holmdel, NJ / (h) Rumson, NJ
   rwurth@att.com
   
   
Article: 5224
Subject: cisco 4500 problem
From: Travis Terry <tterry@csu.edu.au>
Date: Fri, 31 Jan 1997 09:42:22 -0800
Links: << >>  << T >>  << A >>
Any suggestions to a problem I have would be appreciated,
>
> I support a LAN with an FDDI backbone, connected by 4 ESXMINs around the campus. We have a cisco 4500 series router which has an FDDI port but 
is not directly connected to the backbone at the moment. The router 
routes IP, and bridges IPX and Appletalk. The routing protocols we are 
using areRIP and OSPF but would like to solely use OSPF eventually. My 
problem is
> I want to connect the router directly into the FDDI backbone, but when I do it will not bridge the appletalk over the backbone, although there 
are no problems with the IP and IPX.

-- 
Travis Terry
Network Support Officer
Charles Sturt University
Ph:(069) 332817
Fax:(069)332454
email:tterry@csu.edu.au
homepage:http://golum.riv.csu.edu.au/~tterry/


Do we seek advice to confirm what we have already
decided?.......


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