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Messages from 10525

Article: 10525
Subject: Altera 10k pin function ??
From: Nicolas Matringe <nicolas.matringe@dotcom.fr>
Date: Wed, 27 May 1998 17:17:04 +0200
Links: << >>  << T >>  << A >>
I'm using Altera products for the first time and there are some pins
that remain
quite mysterious :

clkusr
cs
/cs
dev_clr
dev_oe
init_done (well, I suppose this one is quite obvious :-)
rdy_/bsy
/rs
/ws

Some of them must be used for parallel programming, but I didn't find
any info about
it in the data book.

I also wonder what is the "user mode" (and what are the other modes)...

thanks

Nicolas MATRINGE                   DotCom SA
Développement électronique         16 rue du Moulin des Bruyères
Tel: 00 33 1 46 67 51 00           92400 COURBEVOIE
Fax: 00 33 1 46 67 51 01           FRANCE
Article: 10526
Subject: Altera 10k pin function ??
From: Nicolas Matringe <nicolas.matringe@dotcom.fr>
Date: Wed, 27 May 1998 17:18:48 +0200
Links: << >>  << T >>  << A >>
I'm using Altera products for the first time and there are some pins
that remain
quite mysterious :

clkusr
cs
/cs
dev_clr
dev_oe
init_done (well, I suppose this one is quite obvious :-)
rdy_/bsy
/rs
/ws

Some of them must be used for parallel programming, but I didn't find
any info about
it in the data book.

I also wonder what is the "user mode" (and what are the other modes)...

thanks

Nicolas MATRINGE                   DotCom SA
Développement électronique         16 rue du Moulin des Bruyères
Tel: 00 33 1 46 67 51 00           92400 COURBEVOIE
Fax: 00 33 1 46 67 51 01           FRANCE
Article: 10527
Subject: Re: Altera 10k pin function ??
From: "Michael Hodson" <mikeh@Spamless.sdve.co.uk>
Date: Wed, 27 May 1998 16:40:11 +0100
Links: << >>  << T >>  << A >>

Nicolas Matringe wrote in message <356C2C57.751D950D@dotcom.fr>...
>I'm using Altera products for the first time and there are some pins
>that remain
>quite mysterious :


Nicolas, I think you need to download the Application Notes on
configuring 6K, 8K, 10K devices from the Altera website. These
cover the functions of the pins to which you are referring.

<http://www.altera.com/html/literature/lan.html>

Mike H.



Article: 10528
Subject: Re: Xilinx BootProm ignores everything
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 27 May 1998 09:46:46 -0700
Links: << >>  << T >>  << A >>
Thilo Thiessenhusen wrote:

> Hello,
>
> I am trying to boot a Spartan 10 from a XC17128D PRom.
>
> * PRom data is correctly programmed, as verified by the
>   PRom-programmer.
>
> * Reset polarity is not correctly programmed, since there
>   is a bug in the programmer. I added a CMOS-HC04 inverter
>   to modify the FPGA's init_ -pin to Reset-H, OE-L to adapt
>   to the standard behavior of a 'fresh' Prom.
>
> * Every input to the Prom behaves as expected. CCLK is
>   there, CE_ is permanently Low, Reset jumps H->L and
>   is successfully controlled by the PROGRAM_ input,
>   supplies and VPP ok.
>
> * No matter whether I use the inverter or not for
>   Reset/OE, the data pin shows the typical signs
>   of being High-Tristate. The FPGA doesn't boot.
>
> I think I am missing something, but what? Do
> Spartans require the Spartan series Proms?
>
> Please help me, I am under time pressure.
>
> Thilo

 Your problem seems to be entirely located in the SPROM.
Luckily it has only eight pins.

Pin 7 and 8 must be at 5 V,
pin 6 is a don't care output
pin 5 must be ground
pin 4 must be Low or at ground
pin 3 must first be an active RESET, then change to Output Enable.
pin 2 must be a full-swing CCLK signal of about 1 MHz
pin 1 will then be the data output, definitely not 3-stated

If this doesn't work, you have programmed the SPROM wrong.
Spartan has no different technical requirement from XC4000E or any other
5-V Xilinx FPGA, except XC6200.

Peter Alfke, Xilinx Applications
 

Article: 10529
Subject: Sorry (was:Altera 10k pin function ??)
From: Nicolas Matringe <nicolas.matringe@dotcom.fr>
Date: Wed, 27 May 1998 19:18:05 +0200
Links: << >>  << T >>  << A >>
Sorry for having posted this 4 times. We had some problems with our news
server...

And next time, I'll read more carefully the app notes (I had, but a bit
too fast)

Nicolas MATRINGE                   DotCom SA
Développement électronique         16 rue du Moulin des Bruyères
Tel: 00 33 1 46 67 51 00           92400 COURBEVOIE
Fax: 00 33 1 46 67 51 01
Article: 10530
Subject: SpeedWave Problem
From: "John Huang" <hungi@tpts4.seed.net.tw>
Date: 28 May 1998 06:59:57 GMT
Links: << >>  << T >>  << A >>
Hi all

	I get a problem in ViewLogic's SpeedWave, the message
shown when I execute a command file, 

ex test.cmd
| Clearing all clocks.
| Fatal Error: Restart failed for VHDL, checkpoint directory doesn't exist.
| Reinitializing waveforms.
| Simulation time rolled back to 0.0ns.
| Open wave streams: Asic.vcd
| Simulation stopped at 40.0ns.

What's the error meaning? 

	Please tell me, Thanks!


	John Huang
Article: 10531
Subject: Re: Altera 10k pin function ??
From: vic@alpha.podol.khmelnitskiy.ua (Victor Levandovsky)
Date: Thu, 28 May 1998 07:26:38 GMT
Links: << >>  << T >>  << A >>
On Wed, 27 May 1998 16:40:11 +0100, "Michael Hodson"
<mikeh@Spamless.sdve.co.uk> wrote:

See Application Note 59 (Configuring FLEX10K dev.) p.18-19


>
>Nicolas Matringe wrote in message <356C2C57.751D950D@dotcom.fr>...
>>I'm using Altera products for the first time and there are some pins
>>that remain
>>quite mysterious :
>
>
>Nicolas, I think you need to download the Application Notes on
>configuring 6K, 8K, 10K devices from the Altera website. These
>cover the functions of the pins to which you are referring.
>
><http://www.altera.com/html/literature/lan.html>
>
>Mike H.
>
>
>

Sincerelly,
   Victor Levandovsky
   PLD application instructor
   Technological University op Podillia
   Ukraine

   vic@NSalpha.podol.khmelnitskiy.ua
   remove@NS.for.email.me
Article: 10532
Subject: SpeedWave problem
From: "John Huang" <hungi@tpts4.seed.net.tw>
Date: 28 May 1998 08:23:30 GMT
Links: << >>  << T >>  << A >>

Hi all

I get a problem when I execute a command file for SpeedWave
and then an ERROR message shown

ex test.cmd
| Clearing all clocks.
| Fatal Error: Restart failed for VHDL, checkpoint directory doesn't exist.
| Reinitializing waveforms.
| Simulation time rolled back to 0.0ns.
| Open wave streams: Asic.vcd
| Simulation stopped at 40.0ns.

What's the checkpoint mean?

And how do I resolve this error, 

Thanks!

John Huang

Article: 10533
Subject: Altera FLEX8k configuration problem
From: Felip Vicedo Roman <feviro@eug.upv.es>
Date: Thu, 28 May 1998 11:36:39 +0200
Links: << >>  << T >>  << A >>
Hi all:

I've use altera EPF8282ALC84-4 in my design, but when I use the
BYTEBlaster to download the .sof file, MAXPLUSII gives me this message  
"configuration failure: SRAM load unsuccessful ".

The connections I have in my design only are:
- nStatus, DCLK, Data0, nConfig, CONF_DONE are connected trough a  
pull-up resistor to Vcc, nSP and MSEL0 to ground and MSEL1 to Vcc.
- All the GND and VCCINT pines are well connected.

We are using the schematic, which appear in "Byteblaster Parallel port
download cable data sheet" (pp. 305, Fig. 5, FLEX8000).
 
We scope the configuration signals and confirm that they correspond to
the given waveforms. The only signal that does not work well is
CONF_DONE. It is always down. (It should be high all the time less when
configuration is being done). Why is it happening?

Could I forget some connection?
Could you help me?
 
Thanks
--

**************************************************
** 	Felip Vicedo Roman			**
** 	Ingenyeria Tècnica en Telecom.		**
**	Escola Universitaria de Gandia		**
**	Universitat Politècnica de València	**
**	feviro@eug.upv.es  ó vroman@mediaweb.es	**			
**************************************************
Article: 10534
Subject: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
From: tim@BITS.bris.ac.uk (Tim Tyler)
Date: Thu, 28 May 1998 10:32:44 GMT
Links: << >>  << T >>  << A >>
Terje Mathisen (Terje.Mathisen@hda.hydro.com) wrote:
: Bruce Hoult wrote:
: > 
: > mpa@comlab.ox.ac.uk (Matt Aubury) writes:
: > > Terje Mathisen wrote:
: > > > This could be solved with runtime code generation as well, compiling an
: > > > optimized set of binary logic ops on the fly, or (much simpler), by
: > > > embedding the cell rules in lookup tables.
: > >
: > > I think you're going to have a problem there: the total state coming
: > > into the lookup table is going to be the eight neighbours plus the
: > > central cell, each with four bits of state, so thats 36 bits of input
: > > data to 4 bits of output. A 32 GB lookup table might be a touch
: > > cumbersome! :-)

: Actually, it isn't quite so bad: Since the output is just 4 bits, I'd
: pack two of them into a single byte, so my table would be "only" 16GB.
: :-)

Number of bits required = 2^Inputs * Outputs
                        = 2^36     * 4
                        = 2^38 bits
                        = 2^35 bytes
2^30 bytes = 1GB.  2^5 = 32 - thus the table required is 32GB as stated
originally...?

Using a lookup table of either size in a FPGA is impractical anyway.
-- 
__________
 |im |yler The Mandala Centre http://www.mandala.co.uk tt@cryogen.com
Article: 10535
Subject: Re: Altera FLEX8k configuration problem
From: "Michael Hodson" <mikeh@Spamless.sdve.co.uk>
Date: Thu, 28 May 1998 12:11:53 +0100
Links: << >>  << T >>  << A >>
Felip Vicedo Roman wrote in message <356D3027.C45C7E5B@eug.upv.es>...
>Hi all:
>
>I've use altera EPF8282ALC84-4 in my design, but when I use the
>BYTEBlaster to download the .sof file, MAXPLUSII gives me this message
>"configuration failure: SRAM load unsuccessful ".
>


Felip, have you checked the settings during your design compilation, in the
Assign -> Global Project Device Options menu? Make sure you have the
correct configuration scheme set up (passive serial, I think).

Mike H.




Article: 10536
Subject: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
From: Terje Mathisen <Terje.Mathisen@hda.hydro.com>
Date: Thu, 28 May 1998 14:21:43 +0200
Links: << >>  << T >>  << A >>
Tim Tyler wrote:
> 
> Terje Mathisen (Terje.Mathisen@hda.hydro.com) wrote:
[snip]
> : Actually, it isn't quite so bad: Since the output is just 4 bits, I'd
> : pack two of them into a single byte, so my table would be "only" 16GB.
> : :-)
> 
> Number of bits required = 2^Inputs * Outputs
>                         = 2^36     * 4
>                         = 2^38 bits
>                         = 2^35 bytes
> 2^30 bytes = 1GB.  2^5 = 32 - thus the table required is 32GB as stated
> originally...?

You're absolutely right, I just saw the 32GB number and 'intuitively'
knew that that meant 1 byte/entry, without bothering to check my
assumption.

Anyway, as you also state:

> Using a lookup table of either size in a FPGA is impractical anyway.

Very impractical indeed. :-)

I assume that the best (smallest) possible implementation of a table on
an FPGA cannot be simpler than a DRAM cell, so it would have been quite
a breakthrough to be able to put a 32GB table on a chip. :-)

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
Using self-discipline, see http://www.eiffel.com/discipline
"almost all programming can be viewed as an exercise in caching"
Article: 10537
Subject: Re: Partitioning an a large design in Altera's Max+Plus II
From: Carl Christensen <carl@philipsdvs.com>
Date: Thu, 28 May 1998 08:56:42 -0600
Links: << >>  << T >>  << A >>


Robert L. Hamilton wrote:

> Our internal customer desires to use an emulation of our current ASIC
> design implemented in programmable logic.  In order to keep the same
> hierarchy, assure fidelity, reduce engineering time, ... for the ASIC
> and the CPLD implementations, I wish perform partitioning of the design
> within the Max+Plus II tool.  (We're using Synopsys (VHDL) and passing
> Max+Plus II hierachical EDIF.) I'm in contact with Altera design
> support, but I'd like independent verification that the partitioner is
> usable. Does anyone have any experience (good or bad) with the tool?
>
> Robert Hamilton


I use to do a lot of ASIC emulation in FPGAs (Mostly Xilinx)  A couple of
thoughts.

1. Experiance with Altera tool .....  We once gave an edif net list of an
ASIC that was already emulated in a bunch of Xilinx parts to an  Altera FAE
he was going to prove that their partionier could automatically do the
chore.  It didn't work.
2. Advise..... Do the partitioning by hand.
3.  Other options.  You might want to talk to the people at Aptix.  They
sell ASIC emulation systems build out of a reprogramable circuit board and
FPGAs.  I know they had an automatic partitioning program that was not too
bad, two years ago.   I'm not sure what they have done with it since then.

Good Luck
Carl Christensen

Article: 10538
Subject: Re: Altera FLEX8k configuration problem
From: "Lev Razamat" <lrazamat@netvision.net.il>
Date: Thu, 28 May 1998 20:33:51 +0300
Links: << >>  << T >>  << A >>
Hi Felip

Once I met same problem
This happen when on the dedicated inputs  of FPGA on downloading time was
clock from
other part of my schematic
When I disable this incoming clocks on downloading time (bitwice and with
config/done)
everything become OK
This affect I have only with EPF8000, with 10k no problem
Regards




Article: 10539
Subject: Compiling a HLL to FPGA
From: guy@orion.math.tau.ac.il (Guy Laden)
Date: 28 May 1998 17:34:21 GMT
Links: << >>  << T >>  << A >>
For fun, I'd like to purchase an FPGA and experiment with compiling
from my own HLL directly to the FPGA. I know a bit about compilers but 
am totally new to reconfigurable computing and am seeking advice regarding
what I need to purchase. Can anybody recommend a cheap PC card with an 
FPGA that I could use for this? Are there any software tools I need
that don't usually come with the card? Do these cards usually ship
with all the documentation one would need to accomplish what I want?
Finally, any pointers to similar work would be appreciated.
Thanks for any advice.
Regards,
Guy
Article: 10540
Subject: make PADS software run on fast computers
From: info@taotech.com
Date: Thu, 28 May 1998 23:27:55 GMT
Links: << >>  << T >>  << A >>
Interface device available to allow old PADS PCB layout software to
run with security key on pentium class (120MHZ ----->)  fast
computers. Costs $94.95 + $5.00 handling and shipping. If it doesn't
work on you computer, we'll refund you money. We are currently running
PADS WORK 7.01 on our 233MHZ PC.  To order, send request for order
form to padsfix@taotech.com 

Article: 10541
Subject: make PADS software run on fast computers
From: info@taotech.com
Date: Thu, 28 May 1998 23:32:51 GMT
Links: << >>  << T >>  << A >>
Interface device available to allow old PADS PCB layout software to
run with security key on pentium class (120MHZ ----->)  fast
computers. Costs $94.95 + $5.00 handling and shipping. If it doesn't
work on you computer, we'll refund you money. We are currently running
PADS WORK 7.01 on our 233MHZ PC.  To order, send request for order
form to padsfix@taotech.com 

Article: 10542
Subject: Re: Compiling a HLL to FPGA
From: "Ian St. John" <istjohn@sprint.ca>
Date: Thu, 28 May 1998 19:44:13 -0400
Links: << >>  << T >>  << A >>

Try www.associatedpro.com. They have low cost x84 boards, and lot's of help
files and tutorials.


Guy Laden wrote in message <6kk76t$n82$1@goethe.tau.ac.il>...
>For fun, I'd like to purchase an FPGA and experiment with compiling
>from my own HLL directly to the FPGA. I know a bit about compilers but
>am totally new to reconfigurable computing and am seeking advice regarding
>what I need to purchase. Can anybody recommend a cheap PC card with an
>FPGA that I could use for this? Are there any software tools I need
>that don't usually come with the card? Do these cards usually ship
>with all the documentation one would need to accomplish what I want?
>Finally, any pointers to similar work would be appreciated.
>Thanks for any advice.
>Regards,
>Guy


Article: 10543
Subject: Xilinx 5200 - XACT 6.0.1 vs. M1.4
From: sam@palmnet.net (Steve Mitchell)
Date: 29 May 1998 03:37:07 GMT
Links: << >>  << T >>  << A >>
I seem to recall that a while back there was a thread going on about
the problems people were having with the Xilinx M1 tools and their
5200 family designs.  Well, I just received my Foundation Base Express
M1.4 package, and I'm running into (probably) the same problems.

I have a 5210 design that is currently on a production PCB that I
developed with the old Foundation/Metamor/XACT 6.0.1 tools.  As it
is on a production PCB, the pinout is fixed.  When I tried to run the
same design through Foundation Express and M1.4 Design Manager, the
design wouldn't map since Express assigned CLKIOB's to some signals
whose pins (fixed) didn't contain CLKIOB's.  Unfortunately, the Base
Express package doesn't allow the user to edit constraints in Express,
so I have no backward compatibility route with the M1.4 tools.

Also, when I removed the pin locking constraints, I could map the design,
but it wouldn't route, indicating that I should use the next larger
package.  However, the same XNF netlist routed with no problems in XACT
6.0.1.

I could go on, but I'm not here to whine.  What I'd like to know is if
anyone has resolved their problems with the M1 tools and their 5200 designs,
and what Xilinx has to say about them.  I've had my case open with their
tech support for over a week, with no acceptable resolution.

Thanks guys/gals.

Steve Mitchell

Article: 10544
Subject: Re: Altera FLEX8k configuration problem
From: "Changho Bae" <asic@shinbiro.com>
Date: Fri, 29 May 1998 12:45:50 +0900
Links: << >>  << T >>  << A >>
Hi
I don't understand what does that mean,
so could you explain it more detail, please.

have a good day.


Article: 10545
Subject: Re: Compiling a HLL to FPGA
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Thu, 28 May 1998 22:59:17 -0700
Links: << >>  << T >>  << A >>
The Programmable Logic Jump Station maintains a fairly comprehensive list of
programmable logic boards (http://www.optimagic.com/boards.html).

You will need the FPGA back-end tools, including place and route and netlist
import.  Some of these are available at little or no cost at
http://www.optimagic.com/lowcost.html.

A good one-stop shopping place for such a board is APS
(http://www.associatedpro.com/).

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Guy Laden wrote in message <6kk76t$n82$1@goethe.tau.ac.il>...
>For fun, I'd like to purchase an FPGA and experiment with compiling
>from my own HLL directly to the FPGA. I know a bit about compilers but
>am totally new to reconfigurable computing and am seeking advice regarding
>what I need to purchase. Can anybody recommend a cheap PC card with an
>FPGA that I could use for this? Are there any software tools I need
>that don't usually come with the card? Do these cards usually ship
>with all the documentation one would need to accomplish what I want?
>Finally, any pointers to similar work would be appreciated.
>Thanks for any advice.
>Regards,
>Guy


Article: 10546
(removed)


Article: 10547
Subject: VHDL, Processor Design, 3D Graphics, to 35k, Cambridge, UK - ECM
From: ECM Selection Ltd <vanessa@ecmsel.demon.co.uk>
Date: Fri, 29 May 1998 11:55:35 +0100
Links: << >>  << T >>  << A >>
Subject: Ref:n.8682 - VHDL, Processor Design, 3D Graphics, to35k,
Cambridge, UK

This innovative company develops state of the art 3D Graphics
technology, recently producing the worlds first ray-tracing hardware.

This is an opportunity for a high calibre Lead Chip Designers to work
on new 3D Graphics Hardware Design.

With a good degree you will have at least 3 years real word experience
and skills in:

Processor Design
VHDL
400K+ gates sub 0.8 micron

 

For further information on ECM and to search our ONLINE VACANCY DATABASE 
visit  http://www.ecmsel.co.uk.

Please contact us by Email: topjob@ecmsel.co.uk.

Alternatively Snail, Fax or Phone:
ECM Selection Ltd, The Maltings, Burwell, Cambridge, CB5 0HB
Phone: 01638 742244                             Fax: 01638 743066
Article: 10548
Subject: VHDL, 3D Graphics, Embedded Systems, to 35k, Cambridge, UK - ECM
From: ECM Selection Ltd <vanessa@ecmsel.demon.co.uk>
Date: Fri, 29 May 1998 11:57:20 +0100
Links: << >>  << T >>  << A >>
Subject: Ref:n.8683 - VHDL, 3D Graphics, Embedded Systems, to35k,
Cambridge, UK

This innovative company develops state of the art 3D graphics
technology, recently producing the world's first ray-tracing
hardware.

This is a new position for an OEM Product Developer/Hardware Engineer
to work with external consultants on the design of new products using
the company's 3D Hardware products.

With a good degree you will have skills in

- high performance computing
- embedded product design
- VHDL circuit simulation
- motherboard design
- experience of managing/working with external consultants
- 3+ years real world experience

 

For further information on ECM and to search our ONLINE VACANCY DATABASE 
visit  http://www.ecmsel.co.uk.

Please contact us by Email: topjob@ecmsel.co.uk.

Alternatively Snail, Fax or Phone:
ECM Selection Ltd, The Maltings, Burwell, Cambridge, CB5 0HB
Phone: 01638 742244                             Fax: 01638 743066
Article: 10549
Subject: Re: Altera FLEX8k configuration problem
From: moc.lis@elyalp (Mike Playle)
Date: Fri, 29 May 1998 11:17:17 GMT
Links: << >>  << T >>  << A >>
On Thu, 28 May 1998 11:36:39 +0200, Felip Vicedo Roman
<feviro@eug.upv.es> wrote:

>Hi all:
>
>I've use altera EPF8282ALC84-4 in my design, but when I use the
>BYTEBlaster to download the .sof file, MAXPLUSII gives me this message  
>"configuration failure: SRAM load unsuccessful ".
>
>The connections I have in my design only are:
>- nStatus, DCLK, Data0, nConfig, CONF_DONE are connected trough a  
>pull-up resistor to Vcc, nSP and MSEL0 to ground and MSEL1 to Vcc.
>- All the GND and VCCINT pines are well connected.

I've got no experience of Altera FLEX 8K devices, but my experience
with FLEX 10K devices has shown that they are very fussy about the
quality of the DCLK signal - it doesn't take much in the way of
overshoot, ringing etc. to make the configuration process very
unreliable. Ensure the clock is square and has fast and clean rising
and falling edges.



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