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Messages from 10600

Article: 10600
Subject: minimalist FPGA - C API for FPGA
From: Ed_Peschko@csgsystems.com
Date: Fri, 05 Jun 1998 00:20:05 GMT
Links: << >>  << T >>  << A >>
All:

I'm a bit new to this field, and I was interested in experimenting in using
genetic algorithms to program FPGA. I've done some GA work, but the article
in discover (last week) was the first I've ever heard of FPGA and wanted a
(cheap) way to play around with the technology....

So - I was wondering. Are there FPGA chips that:

1) hook up to a PC's PCI slot (or DEC Alpha, or Sun Workstation)
2) have a C API to directly configure the programmable component of the chip,
   to do that programming and to pass inputs into the chip itself, as well as
   receive outputs.
3) are as I said, relatively cheap...

The way I figure it, what I plan to do wouldn't involve a lot of upfront,
logical design and hence an expensive setup would be unnecessary.

Any help on this would be appreciated...

Ed

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 10601
Subject: TESTBENCH
From: "John Huang" <hungi@tpts4.seed.net.tw>
Date: 5 Jun 1998 05:03:55 GMT
Links: << >>  << T >>  << A >>
Hi all:
	I got some questions about Viewlogic/Speedwave,
	I have a design that use VHDL for a FPGA.
	1. Can I use VHDL testbench in the speedwave, if
	   it is YES, how will I do?
	2. What simulaors support the VHDL testbench?
	3. Would you please give me an example for
	   write testbench?

	Thanks

	John Huang




Article: 10602
Subject: Re: TESTBENCH
From: hamish@moffatt.nu (Hamish Moffatt)
Date: 5 Jun 1998 07:01:09 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga John Huang <hungi@tpts4.seed.net.tw> wrote:
> 	I got some questions about Viewlogic/Speedwave,
> 	I have a design that use VHDL for a FPGA.
> 	1. Can I use VHDL testbench in the speedwave, if
> 	   it is YES, how will I do?
> 	2. What simulaors support the VHDL testbench?

Aldec's ActiveVHDL seems to run them nicely.

> 	3. Would you please give me an example for
> 	   write testbench?

Best to grab a book eg Skahill's VHDL for Programmable Logic,
it has a whole chapter on it. Aldec's also has a thing for generating
test benches for you, I haven't tried it.


Hamish
-- 
Hamish Moffatt, StudIEAust              hamish@debian.org, hamish@moffatt.nu
Student, computer science & computer systems engineering.    4th year, RMIT.
http://hamish.home.ml.org/ (PGP key here)             CPOM: [******    ] 67%
Matter cannot be created or destroyed, nor returned without a receipt.
Article: 10603
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: mlankenau@yahoo.com (Marcus Lankenau)
Date: Fri, 05 Jun 1998 11:54:01 GMT
Links: << >>  << T >>  << A >>
z80@ds1.com (Peter) wrote:

>
>Assuming you can write software at all, you don't need a code example.
>Have a look at the slave serial mode in the Xilinx data book, and
>implement that. It is trivial.
>
>>Hello all,
>>    I am trying to program the xilinx fpga  in a serial slave mode with
>>an 8051. Anyone knows where I can get an example of the 8051 codes that
>>read the Xilinx configuration data from the 8051's eprom and program the
>>Xilinx fpga ?
>
>
>Peter.
>
>Return address is invalid to help stop junk mail.
>E-mail replies to zX80@digiYserve.com but
>remove the X and the Y.

Where is the adventage in using the 8051 for the configuration of the
fpga instead of using an eeprom? 



Marcus
Article: 10604
Subject: Atmel AT40K
From: mlankenau@yahoo.com (Marcus Lankenau)
Date: Fri, 05 Jun 1998 11:54:08 GMT
Links: << >>  << T >>  << A >>



How dows the new Atmel AT40K compare to Xilinx XC4000 in price and
function?




Marcus Lankenau
Article: 10605
Subject: Re: minimalist FPGA - C API for FPGA
From: "Ian St. John" <istjohn@high-sense.com>
Date: Fri, 5 Jun 1998 09:03:58 -0400
Links: << >>  << T >>  << A >>

Ed_Peschko@csgsystems.com wrote in message
<6l7djk$s8c$1@nnrp1.dejanews.com>...
>All:
>
>I'm a bit new to this field, and I was interested in experimenting in using
>genetic algorithms to program FPGA. I've done some GA work, but the article
>in discover (last week) was the first I've ever heard of FPGA and wanted a
>(cheap) way to play around with the technology....
>
>So - I was wondering. Are there FPGA chips that:
>
>1) hook up to a PC's PCI slot (or DEC Alpha, or Sun Workstation)
>2) have a C API to directly configure the programmable component of the
chip,
>   to do that programming and to pass inputs into the chip itself, as well
as
>   receive outputs.
>3) are as I said, relatively cheap...
>
>The way I figure it, what I plan to do wouldn't involve a lot of upfront,
>logical design and hence an expensive setup would be unnecessary.
>
>Any help on this would be appreciated...


You might want to look at www.vcc.com and their cheap ( $995.00 )
configurable computer card. As I understand it, they map the sram
configuration of the Xilinx 6200 into memory, so you can modify the design
in realtime from c programs. Card uses a Xilinx 4013 FPGA for PCI bus core
logic.

Just modify the mapped memory with a new configuration and you have
reprogrammed the chip. You can even do it by sections. Note: Xilinx has
dropped support for the 6200, but it is to be continued with the original
designers with Xilinxs blessing...

Of course cheap is a relative term, and I have heard some disparagement of
the programming support for the chip... I think you might also be able to
reprogram the unused portions of the 4013, but I can't be sure of that.


Article: 10606
Subject: Re: minimalist FPGA - C API for FPGA
From: tim@BITS.bris.ac.uk (Tim Tyler)
Date: Fri, 5 Jun 1998 13:05:23 GMT
Links: << >>  << T >>  << A >>
Ed_Peschko@csgsystems.com wrote:

: I'm a bit new to this field, and I was interested in experimenting in using
: genetic algorithms to program FPGA.

There are a few other prople doing this.  Notably, perhaps are Moshe Sipper,
with his Firefly, Dr Hugo de Garis, Adrian Thompson and friends at Sussex, 
and the EvolvaWare group, who apply GAs to VDHL before blowing it onto FPGAs.

[snip]

: So - I was wondering. Are there FPGA chips that:

: 1) hook up to a PC's PCI slot (or DEC Alpha, or Sun Workstation)
: 2) have a C API to directly configure the programmable component of the chip,
:    to do that programming and to pass inputs into the chip itself, as well as
:    receive outputs.
: 3) are as I said, relatively cheap...

In order, yes, I don't know and yes, relatively.

I don't know about C APIs.  Most vendors appear to be supplying custom tools 
and ones based on VDHL.  However, no doubt the answer is 'yes', in spirit as
you will be able to configure the CLB's lookup tables from external programs.

Whether a minimal, low-level C API is actually what you want is another 
question.
-- 
__________
 |im |yler The Mandala Centre http://www.mandala.co.uk tt@cryogen.com
Article: 10607
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: "Jeff Tucker" <nobody@no.spam.com>
Date: Fri, 5 Jun 1998 12:11:37 -0400
Links: << >>  << T >>  << A >>
Presumably you already have a ROM to store the code for the 8051,
so you save the cost of a part.

Also, the Xilinx code becomes part of your 8051 source code, so it
can be updated in the same fashion as your 8051. If you have some
provision for in-circuit firmware updates, the Xilinx will get updated, too,
instead of having to write a separate update for the EEPROM.
And, if as your code changes you end up using the Xilinx slightly
differently,
i.e. needing another signal or wanting something to work a little
differently,
it's simpler to make sure that the firmware and the Xilinx programming
are in sync.

JT


Marcus Lankenau wrote in message <3577a070.2918311@news.nordkom.de>...
>Where is the adventage in using the 8051 for the configuration of the
>fpga instead of using an eeprom?
>
>
>
>Marcus


Article: 10608
Subject: Is there tiling software?
From: "Prof. Vitit Kantabutra" <kantviti@isu.edu>
Date: Fri, 05 Jun 1998 11:10:43 -0600
Links: << >>  << T >>  << A >>
I'm designing a fairly large circuit, but only have a letter-sized
printer, and want to be able to tile my printouts on several pages.  Is
there software anywhere that does that?  Xilinx Foundation tiles your
output, but the scales of the pages are not 100% equal, leading to a
very annoying-looking output.  Also, when I design using ViewLogic,
tiling doesn't seem to be available at all.  Using screen capture
programs is sort of possible, but very inconvenient.  Any suggestions? 
Thanks in advance.
Article: 10609
Subject: Re: Non-periodic clock
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Fri, 05 Jun 1998 10:25:47 -0700
Links: << >>  << T >>  << A >>
I would call this a strobe, rather than a clock. As described, it
just synchronously flags changes on the data bits. I'm not sure what
you intend to do with the bits, but using this signal as a master
clock would restrict your logic to whatever you could accomplish
combinatorially in 50 ns minus setup times for your state registers.
Which might be all you need - plus dynamic power consumption would
be very low if the logic was clocked only when necessary.

You could not, for example, pipeline your logic or set off a sequence of
state changes in response to a single input change.

If you have access to the raw 20 MHz clock, then you could treat this
strobe/clock as just another input to your state machine (indicating
data validity) and do whatever you want.

If by "does it matter" you were referring instead to the electrical
aspects of the clock waveform- not much. There are no clock duty cycle
restrictions on Xilinx parts except maybe for the config clock.
The only issues I can think of for non-50% clocks are avoiding AC
termination and capacitive/transformer coupling.

Hope this helps -

regards, tom   

Andy Peters wrote:
> 
> Gang:
> 
> I have to design a board that talks to a pre-existing processor
> board.  It's actually pretty simple, if sorta wacky: the processor
> board outputs a bunch of discrete bits, a clock, and various clock
> enables.  If a clock enable is asserted, the bits it controls are
> registered. Since there's a whole bunch of these bits, I'm going to
> put the whole mess into a Xilinx part (probably a 9500 series) of
> appropriate size, write fifteen or twenty lines of VHDL, and I'll be
> done.  This is all pretty standard.
> 
> With the following exception:
> 
> The clock doesn't run all the time: it is only asserted when some
> bits are output and we need to latch them.
> 
> A little more detail: all of these bits, the enables and this clock
> are generated from a state machine that has a 50ns tick.  For
> example, if a 1 needs to be stored in one of these registers, the
> hardware puts out a 1 on that data line.  50ns later, the clock line
> is asserted for 50ns.  These outputs are registered to a 20MHz clock.
> 
> The question: does it really matter if the clock is aperiodic like
> this?
> 
> --
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatories
> apeters@noao.edu.NOSPAM

-- 
-----------
Tom Burgess

National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

Email:        tom.burgess@hia.nrc.ca
Office:       (250) 490-4360 
Switch Board: (250) 493-2277
Fax:          (250) 493-7767
Article: 10610
Subject: Re: LATTICE 2032 problems
From: nick toop <nick@cortexco.demon.co.uk>
Date: Fri, 5 Jun 1998 18:26:06 +0100
Links: << >>  << T >>  << A >>
In article <3576532E.412E587D@ihr.mrc.ac.uk>, John Chambers
<johnc@ihr.mrc.ac.uk> writes
>I've recently had a problem with Lattice ispLSI2032-80LJ parts no
>programming correctly.  I could program them but not verify them. 
>Changing for a 1016 or a different speed 2032 solved the problem.  Has
>anyone else had trouble?

I have occasionally had problems with programming 1016 devices on breadboards.
The problem seems to relate to a clock being present on the Y0 input when the
grounding is not very good.

It is very important to have a 10nF cap on the -ISPEN input.

-- 
nick toop
Article: 10611
Subject: Re: Non-periodic clock
From: Tim Warland <twarlandSPAM@nortel.ca>
Date: Fri, 05 Jun 1998 14:38:44 -0400
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> 
> Gang:
<snip> 
> 
> The question: does it really matter if the clock is aperiodic like
> this?
> 
No it doesn't matter.  Treat the device as if it were (almost) 
asynchronous, you've got lots of time to work with.  One possible
gotta is if you declare your non-periodic clock as a clock, it
may be assigned to a clock buffer with a built in PLL. This depends
on the architecture of the pld/fpga

Tim.
-- 
Strong words softly spoken.

My opinions != Nortel's opinion.
Article: 10612
Subject: Re: Non-periodic clock
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: 5 Jun 1998 21:44:29 GMT
Links: << >>  << T >>  << A >>
Tom Burgess <tom.burgess@hia.nrc.ca> wrote in article
<35782A1B.2E6318D7@hia.nrc.ca>...

> I would call this a strobe, rather than a clock. As described, it
> just synchronously flags changes on the data bits. I'm not sure
what

Yes, it acts as a strobe.

> you intend to do with the bits, but using this signal as a master
> clock would restrict your logic to whatever you could accomplish
> combinatorially in 50 ns minus setup times for your state
registers.
> Which might be all you need - plus dynamic power consumption would
> be very low if the logic was clocked only when necessary.

Basically, the bits are set to a state until changed later.  The only
other logic is gating the clock enable with another signal (a board
enable).  Not much more than an AND gate delay there, that's all.
 
> You could not, for example, pipeline your logic or set off a
sequence of
> state changes in response to a single input change.

Not necessary.  The bits are intended to be static set and forget.
 
> If you have access to the raw 20 MHz clock, then you could treat
this
> strobe/clock as just another input to your state machine
(indicating
> data validity) and do whatever you want.

I *do* have access to that clock.  I was just wondering whether the
simple approach I described is "good."  I originally outlined the
problem on paper using the 20 MHz clock to drive the clock inputs to
the registers, and creating clock enables by ANDing the clock-strobe
and the clock enables generated by the processor board.  I think I
got concerned about setup times and all that.

> If by "does it matter" you were referring instead to the electrical
> aspects of the clock waveform- not much. There are no clock duty
cycle
> restrictions on Xilinx parts except maybe for the config clock.
> The only issues I can think of for non-50% clocks are avoiding AC
> termination and capacitive/transformer coupling.

Yes, that is what I was worried about.

thanks!

-andy

-- 
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
apeters@noao.edu.NOSPAM

Article: 10613
Subject: Re: Non-periodic clock
From: murray@pa.dec.com (Hal Murray)
Date: 5 Jun 1998 22:58:57 GMT
Links: << >>  << T >>  << A >>
In article <01bd9016$a68360b0$4601fc8c@shootingstar>, "Andy Peters" <apeters@noao.edu.NOSPAM> writes:
[snip]
> A little more detail: all of these bits, the enables and this clock
> are generated from a state machine that has a 50ns tick.  For
> example, if a 1 needs to be stored in one of these registers, the
> hardware puts out a 1 on that data line.  50ns later, the clock line
> is asserted for 50ns.  These outputs are registered to a 20MHz clock.
> 
> The question: does it really matter if the clock is aperiodic like
> this?

I don't see any obvious problems if your logic doesn't need
a clock for anything else.  It feels like a standard hack to
save power or make a simple interface with available PIO pins.

If the outputs you are capturing don't have any timing restrictions,
say they are driving LEDs, then what you propose will work fine.


You are getting into clock skew so you are justified in being suspicious.

Suppose you bring one of these outputs back into the system.  The clock
to out time doesn't start when the normal clock ticks.  It gets delayed
until the "clock" signal gets out of the first chip and over to your
9500.  Some software may not be able to account for that complication.

-- 
These are my opinions, not necessarily my employers.
Article: 10614
Subject: Re: minimalist FPGA - C API for FPGA
From: Ed_Peschko@csgsystems.com
Date: Fri, 05 Jun 1998 23:26:56 GMT
Links: << >>  << T >>  << A >>
In article <897051960.544307@BITS.bris.ac.uk>,
  tt@cryogen.com wrote:
>
> Ed_Peschko@csgsystems.com wrote:
>
> : I'm a bit new to this field, and I was interested in experimenting in using
> : genetic algorithms to program FPGA.
>
> There are a few other prople doing this.  Notably, perhaps are Moshe Sipper,
> with his Firefly, Dr Hugo de Garis, Adrian Thompson and friends at Sussex,
> and the EvolvaWare group, who apply GAs to VDHL before blowing it onto FPGAs.

Well, of course there people are doing it. Any experiment that is worth
pursuing has its proponents and its research teams.  I happen to think that
making evolvable VHDL is the wrong way to go, since VHDL is a higher-level
language and what is right for human designers is not necessarily right for
evolution.

Still I'm interested. Do you know a source to any white papers to their work
that I can take a look at?

> I don't know about C APIs.  Most vendors appear to be supplying custom tools
> and ones based on VDHL.  However, no doubt the answer is 'yes', in spirit as
> you will be able to configure the CLB's lookup tables from external programs.
>
> Whether a minimal, low-level C API is actually what you want is another
> question.
> --

Considering that the faster the API, the quicker the evolutionary cycle and
the faster the results, yes I probably do... Also considering that there are
several public domain GA packages written in C, a C-API would make the
simulation creation a lot easier as well.

Ed

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 10615
Subject: Re: minimalist FPGA - C API for FPGA
From: Ed_Peschko@csgsystems.com
Date: Sat, 06 Jun 1998 00:23:45 GMT
Links: << >>  << T >>  << A >>
In article <897051960.544307@BITS.bris.ac.uk>,
  tt@cryogen.com wrote:
>
> Ed_Peschko@csgsystems.com wrote:
>
> : I'm a bit new to this field, and I was interested in experimenting in using
> : genetic algorithms to program FPGA.
>
> There are a few other prople doing this.  Notably, perhaps are Moshe Sipper,
> with his Firefly, Dr Hugo de Garis, Adrian Thompson and friends at Sussex,
> and the EvolvaWare group, who apply GAs to VDHL before blowing it onto FPGAs.

Well, of course there people are doing it. Any experiment that is worth
pursuing has its proponents and its research teams.  I happen to think that
making evolvable VHDL is the wrong way to go, since VHDL is a higher-level
language and what is right for human designers is not necessarily right for
evolution.

Still I'm interested. Do you know a source to any white papers to their work
that I can take a look at?

> I don't know about C APIs.  Most vendors appear to be supplying custom tools
> and ones based on VDHL.  However, no doubt the answer is 'yes', in spirit as
> you will be able to configure the CLB's lookup tables from external programs.
>
> Whether a minimal, low-level C API is actually what you want is another
> question.
> --

Considering that the faster the API, the quicker the evolutionary cycle and
the faster the results, yes I probably do... Also considering that there are
several public domain GA packages written in C, a C-API would make the
simulation creation a lot easier as well.

Ed

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10616
Subject: Write to XC17S20 fail
From: basaro@yumenet.com (Tadaaki Koyama)
Date: Sat, 06 Jun 1998 04:51:41 GMT
Links: << >>  << T >>  << A >>
Hello 

I want to write data to XC17S20 using HW-130 writer, but it is failed.
I use HW130w32 program on windows NT,and this program got from XILINX
ftp site and program date is 04-07-98 

Why can't write it?

This program can write XC17256D . 

                                 T.Koyama
Article: 10617
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: z80@ds1.com (Peter)
Date: Sat, 06 Jun 1998 08:21:34 GMT
Links: << >>  << T >>  << A >>

>Where is the adventage in using the 8051 for the configuration of the
>fpga instead of using an eeprom? 

In addition to the other reply post: can can use a) a serial eprom or
b) a parallel eprom.

With a) it means more money and yet another device to program; very
few programmers support these devices. With b) one can share an EPROM
with the CPU, but unless you have some extra logic, the FPGA code will
have to sit on an easy address boundary, e.g. A14=1 or similar, and
this can waste a big chunk of your EPROM.

Getting the CPU to do the upload is much nicer.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 10618
Subject: Re: minimalist FPGA - C API for FPGA
From: tim@BITS.bris.ac.uk (Tim Tyler)
Date: Sat, 6 Jun 1998 11:22:24 GMT
Links: << >>  << T >>  << A >>
Ed_Peschko@csgsystems.com wrote:
: In article <897051960.544307@BITS.bris.ac.uk>,
:   tt@cryogen.com wrote:
: > Ed_Peschko@csgsystems.com wrote:
: >
: > : I'm a bit new to this field, and I was interested in experimenting in 
: > : using genetic algorithms to program FPGA.
: >
: > There are a few other prople doing this.  Notably, perhaps are Moshe Sipper,
: > with his Firefly, Dr Hugo de Garis, Adrian Thompson and friends at Sussex,
: > and the EvolvaWare group, who apply GAs to VDHL before blowing it onto 
: > FPGAs.

: Well, of course there people are doing it. Any experiment that is worth
: pursuing has its proponents and its research teams.

;-)

: I happen to think that making evolvable VHDL is the wrong way to go, 

I agree completely.

: Still I'm interested. Do you know a source to any white papers to their work
: that I can take a look at?

Certainly:

The VHDL evolvers (EvolvaWare) are at
 http://asd.bbn.com/evolvaware/index.htm

Moshe Sipper (author of 'Evolvolution of Parallel Cellular Machines'):
 http://lslwww.epfl.ch/~moshes/

Dr Hugo de Garis, 'Japan's Brain Builder':
 http://www.hip.atr.co.jp/~degaris/

Sussex (EHW links):
 http://www.cogs.susx.ac.uk/users/adrianth/EHW_groups.html

International Conference on Evolvable Systems 1998:
 http://lslwww.epfl.ch/ices98/

[snip C APIs?]

: > Whether a minimal, low-level C API is actually what you want is another
: > question.

: Considering that the faster the API, the quicker the evolutionary cycle and
: the faster the results, yes I probably do...

If possible, I'd recommend that you blow your evolutionary world onto an 
FPGA and then let it run.  Uniform CAs are useful for this.

Of course dynamically programming the FPGA with different programs is
possible - indeed, I'm under the impression that this is what most people do.

The size of the immediate penalty for this approach depends on whether the 
reprogramming time is significant compared to the time taken to evaluate 
a generation's fitness.

: Also considering that there are several public domain GA packages 
: written in C, a C-API would make the simulation creation a lot easier 
: as well.

My original comment was a little cryptic.  There typically isn't a good
relationship between what you want to evolve and the way in which it is
implemented on the chip.  This is, in part, because FPGAs are sparsely
connected: routing and optimisation are usually done by complicated software.

You probably want to use the work done on this level, rather than trying to
access the card more directly.

Lastly, another stab at cheap cards:

http://www.xess.com/FPGA/ are as cheap as I have seen for a basic small
experimental unit.  These aren't PCI, but run over the printer port (they
have sockets for breadboarding them that would be out of place if the cards
were orthodox PCI).  I can't comment on the cards as I've not used them.
-- 
__________
 |im |yler The Mandala Centre http://www.mandala.co.uk tt@cryogen.com
Article: 10619
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: Luthfi Kisbiono Arif <luthfi@FreeBSD.id.org>
Date: Sat, 6 Jun 1998 18:46:22 +0700
Links: << >>  << T >>  << A >>
On Wed, 3 Jun 1998, damon wrote:

> Hello all,
>     I am trying to program the xilinx fpga  in a serial slave mode with
> an 8051. Anyone knows where I can get an example of the 8051 codes that
> read the Xilinx configuration data from the 8051's eprom and program the
> Xilinx fpga ?

If you have xilinx XS9500/XS4000 board, you may find the file to convert
Xilinx configs data to 8051 eprom format.

-Luthfi K. Arif-



Article: 10620
Subject: Re: Is there tiling software?
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Sat, 06 Jun 1998 12:40:26 GMT
Links: << >>  << T >>  << A >>
On Fri, 05 Jun 1998 11:10:43 -0600, "Prof. Vitit Kantabutra"
<kantviti@isu.edu> wrote:

>I'm designing a fairly large circuit, but only have a letter-sized
>printer, and want to be able to tile my printouts on several pages.  Is
>there software anywhere that does that?  

A cheap A3 printer (color inkjet) would be a help (B-size to you
Americans) like the Canon 4650. I saw the obsolescent 4550 for about
$200 recently, it would do fine.

- Brian
Article: 10621
Subject: Q: XILINX Foundation - how to minimize project archive?
From: Alexander Sherstuk <Sherstuk@amsd.com>
Date: Sat, 6 Jun 1998 22:55:01 +0400
Links: << >>  << T >>  << A >>
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------ =_NextPart_001_01BD917C.9BD5387A
Content-Type: text/plain

Hi ALL,

The problem, which I am trying to solve - how to keep
reasonable size of an archive for the LCA design created with
XILINX Foundation M1.4.

I revealed that Foundation creates a number of intermediate files, 
which need not be remembered for successful reconstruction of 
the project. An existing FOUNDATION "Archive" feature does 
not solve the problem - it just PKZIPs everything, without any
attempt of minimization.

My question is:

  Which file extensions must be remembered when archiving Foundation
project?

Thanks in advance for any Foundation experience,

  Alex Sherstuk
    sherstuk@amsd.com


------ =_NextPart_001_01BD917C.9BD5387A
Content-Type: text/html

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=us-ascii">
<META NAME="Generator" CONTENT="MS Exchange Server version 5.5.1960.3">
<TITLE>Q: XILINX Foundation - how to minimize project archive?</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=2 FACE="Arial CYR">Hi ALL,</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial CYR">The problem, which I am trying to solve - how to keep</FONT>
<BR><FONT SIZE=2 FACE="Arial CYR">reasonable size of an archive for the LCA design created with</FONT>
<BR><FONT SIZE=2 FACE="Arial CYR">XILINX Foundation M1.4.</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial CYR">I revealed that Foundation creates a number of intermediate files, </FONT>
<BR><FONT SIZE=2 FACE="Arial CYR">which need not be remembered for successful reconstruction of </FONT>
<BR><FONT SIZE=2 FACE="Arial CYR">the project. An existing FOUNDATION &quot;Archive&quot; feature does </FONT>
<BR><FONT SIZE=2 FACE="Arial CYR">not solve the problem - it just PKZIPs everything, without any</FONT>
<BR><FONT SIZE=2 FACE="Arial CYR">attempt of minimization.</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial CYR">My question is:</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial CYR">&nbsp; Which file extensions must be remembered when archiving Foundation project?</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial CYR">Thanks in advance for any Foundation experience,</FONT>
</P>

<P><FONT SIZE=2 FACE="Arial CYR">&nbsp; Alex Sherstuk</FONT>
<BR><FONT SIZE=2 FACE="Arial CYR">&nbsp;&nbsp;&nbsp; sherstuk@amsd.com</FONT>
</P>

</BODY>
</HTML>
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Article: 10622
Subject: Re: Evolutionary FPGAs
From: Steve Casselman <sc@vcc.com>
Date: Sat, 06 Jun 1998 13:38:08 -0700
Links: << >>  << T >>  << A >>
We have lots of customers working on evolvable
hardware. Many people are interested in the method
and the 6200 is the only device that allows one to
do this.


> On the June issue of Discover Magazine, the cover story reports of two
>
> computer scientists, Inman Harvey and Adrian Thompson, applying
> evolution
> to program a Xilinx XC6216ES.
>
> One of the things they did was evolved the FGPA to distinguish a 1KHz
> input from a 10KHz input. This was done with using only 100 CLBs of
> the
> XC6216, and no clock input. After two weeks and 5000 generations, the
> chip
> evolved to work great --with one drawback, it's not robust. If
> programmed
> to different chips or if input/output pins were reassigned, it
> wouldn't
> work. Also, slightly temperature variations have big effects.
>
> Is there anybody that applied Thompson's method of programming a FPGA?
>
> More information can be found at http://www.discover.com



--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 10623
Subject: Re: minimalist FPGA - C API for FPGA
From: Steve Casselman <sc@vcc.com>
Date: Sat, 06 Jun 1998 13:39:40 -0700
Links: << >>  << T >>  << A >>
Check out our web site for more info on the HOT works.
6200 development package.



Ed_Peschko@csgsystems.com wrote:

> All:
>
> I'm a bit new to this field, and I was interested in experimenting in
> using
> genetic algorithms to program FPGA. I've done some GA work, but the
> article
> in discover (last week) was the first I've ever heard of FPGA and
> wanted a
> (cheap) way to play around with the technology....
>
> So - I was wondering. Are there FPGA chips that:
>
> 1) hook up to a PC's PCI slot (or DEC Alpha, or Sun Workstation)
> 2) have a C API to directly configure the programmable component of
> the chip,
>    to do that programming and to pass inputs into the chip itself, as
> well as
>    receive outputs.
> 3) are as I said, relatively cheap...
>
> The way I figure it, what I plan to do wouldn't involve a lot of
> upfront,
> logical design and hence an expensive setup would be unnecessary.
>
> Any help on this would be appreciated...
>
> Ed
>
> -----== Posted via Deja News, The Leader in Internet Discussion
> ==-----
> http://www.dejanews.com/   Now offering spam-free web-based
> newsreading



--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 10624
Subject: Re: minimalist FPGA - C API for FPGA
From: Steve Casselman <sc@vcc.com>
Date: Sat, 06 Jun 1998 13:47:13 -0700
Links: << >>  << T >>  << A >>
Tim Tyler wrote:

> Ed_Peschko@csgsystems.com wrote:
>
> : I'm a bit new to this field, and I was interested in experimenting
> in using
> : genetic algorithms to program FPGA.
>
> There are a few other prople doing this.  Notably, perhaps are Moshe
> Sipper,
> with his Firefly, Dr Hugo de Garis, Adrian Thompson and friends at
> Sussex,
> and the EvolvaWare group, who apply GAs to VDHL before blowing it onto
> FPGAs.
>
> [snip]
>
> : So - I was wondering. Are there FPGA chips that:
>
> : 1) hook up to a PC's PCI slot (or DEC Alpha, or Sun Workstation)
> : 2) have a C API to directly configure the programmable component of
> the chip,
> :    to do that programming and to pass inputs into the chip itself,
> as well as
> :    receive outputs.
> : 3) are as I said, relatively cheap...
>
> In order, yes, I don't know and yes, relatively.
>
> I don't know about C APIs.  Most vendors appear to be supplying custom
> tools
> and ones based on VDHL.  However, no doubt the answer is 'yes', in
> spirit as
> you will be able to configure the CLB's lookup tables from external
> programs.
>
> Whether a minimal, low-level C API is actually what you want is
> another
> question.
> --

Yes it helps to have a C  API for the 6200. There are commands
like rcol and wcol for reading and writing to the mirco-p map
and lot of other functions as well. For example there is the ral
libraries that allow you to give a name to a gate on a schematic
or an instance of a gate in VHDL and then call out that gate
by name in your C code and then change it on the fly.

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com




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