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Messages from 17125

Article: 17125
Subject: Re: ALTERA GDF to VHDL QUESTION
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 01 Jul 1999 14:39:47 -0400
Links: << >>  << T >>  << A >>
Jaya Rajesh wrote:
> 
> I don't think it is possible with altera maxplusII. After finishing the
> VHDL files, I'm using Orcad Capture for creating the top level block
> diagram and VHDL file.
> 
> Regards,
> Jaya Rajesh.

Jaya,

You are the first person I have heard from who is designing an FPGA
using Orcad and VHDL. I attempted this a year ago using version 7.1. The
software worked so poorly and Orcad support was so unhelpful that I
finally gave up and bought the Xilinx Foundation package to finish the
design. 

How far have you gotten? Are you using the new release 9 software or the
older version 7? Are you having any problems with the VHDL synthesis and
simulation? 

I liked the fact that I could do a VHDL simulation of my entire design
including the schematic portions. I didn't like the fact that I couldn't
simulate anything because the simulator would crash every third time I
ran it. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 17126
Subject: Re: FW: Xilinx Acquisition of CoolRunners
From: Ray Andraka <randraka@ids.net>
Date: Thu, 01 Jul 1999 15:10:21 -0400
Links: << >>  << T >>  << A >>
What about Atmel?  They sure aren't paying the bills with AT40K sales.


>  Here are the other big companies that have thrown in the towel:
> Intel, TI, Motorola, AMD, National Semi, and now Philips.  Except for Lucent, all
> PLD suppliers are now "pure players", with nothing else to distract their
> attention and no other product lines to subsidize or be subsidized by.
>
> I know how to spell, even if the finger sometimes slips on the keyboard :-)
>
> Peter Alfke



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17127
Subject: ABL-Problem (XILINX CPLD)
From: Martin Maurer <maurerm@informatik.tu-muenchen.de>
Date: Thu, 01 Jul 1999 19:24:23 +0000
Links: << >>  << T >>  << A >>
Hello,

i use the following code fragment in one of my abel-programmes for
XILINX-CPLD 95108. I have a 18 Bit Counter. When MODE_MONITOR is 1,
i want to select (WITH SEL1248 == 1,2,3 or 4) different clocks. If the
counter reaches the top (A17 goes to 1), the counter should stop.
In the other mode (MODE_MONITOR == 0), i want to increment the counter
by SEL_BYTE (no stop).

(RAM_ADDRESS is an array of 'reg', RAM_A17 is 'com'
 SEL1248 are 2 'reg' and MONITOR_ALWAYS is also 'reg')

I have 2 problems:
1) In MODE_MONITOR == 1 it doesn't stop ! I see the RAM_A17 toggling,
   but counter doesn't stop.
2) In manual mode (MODE_MONITOR == 0) i toggle SEL_BYTE, but counter
   doesn't move...For debugging reasons i have copied the SEL_BYTE
   to an output pin, the pin is toggling fine.

Here is my code fragment:

WHEN (MODE_MONITOR & SEL1248 == 0) & (!RAM_A17 # MONITOR_ALWAYS)
THEN RAM_ADDRESS.CLK = !TT3;
ELSE
WHEN (MODE_MONITOR & SEL1248 == 1) & (!RAM_A17 # MONITOR_ALWAYS)
THEN RAM_ADDRESS.CLK = !TT2;
ELSE
WHEN (MODE_MONITOR & SEL1248 == 2) & (!RAM_A17 # MONITOR_ALWAYS)
THEN RAM_ADDRESS.CLK = !TT1;
ELSE
WHEN (MODE_MONITOR & SEL1248 == 3) & (!RAM_A17 # MONITOR_ALWAYS)
THEN RAM_ADDRESS.CLK = !TT0;
ELSE
WHEN !MODE_MONITOR
THEN RAM_ADDRESS.CLK = !SEL_BYTE;
ELSE RAM_ADDRESS = 0;

RAM_ADDRESS := RAM_ADRESS + 1;
RAM_ADDRESS.AR = WANT_REWS;
LPT_READY = RAM_A17;

Greetings,

    Martin Maurer (maurerm@in.tum.de)

Article: 17128
Subject: Re: Altera 10K prices
From: bob elkind <eteam@aracnet.com>
Date: Thu, 01 Jul 1999 12:26:50 -0700
Links: << >>  << T >>  << A >>
Go to a distributor website (e.g. www.arrow.com) to check prices and availability of components.

-- Bob Elkind

Karim LIMAM wrote:
> 
> Hi,
> 
> I'm looking for the prices of the Altera Flex 10K (10K40 .. 10K130E). Has
> somebody an idea ?
> 
> Thanks.
> 
> kerim el imem
Article: 17129
Subject: Altera, JTAG, and FPGAs WAS: Virtex JTAG readback
From: bob elkind <eteam@aracnet.com>
Date: Thu, 01 Jul 1999 12:36:25 -0700
Links: << >>  << T >>  << A >>
With Altera SRAM-based FPGAs (and this probably applies to Xilinx FPGAs as well), the device's FPGA functions don't come alive
until the device is configured.  What do you do when the device is yet unconfigured, especially when there are multiple devices
on the same JTAG chain (specific case, ISP CPLDs and/or config ROMs on the same chain) ?

Altera (and Xilinx as well, it appears) has anticipated this problem.  A solution is to hold the CONFIG* pin low.  This forces
the on-chip JTAG facilities to be active.  This is a state where the programmed presence of the JTAG facilities is moot, so they
are enabled.

Keep this in mind, if you're counting on JTAG/TAPI ports to initially program and/or test a board.

-- Bob Elkind

Article: 17130
Subject: Re: FW: Xilinx Acquisition of CoolRunners
From: mma@netwiz.net (Mark Aaldering)
Date: Thu, 01 Jul 1999 19:37:30 GMT
Links: << >>  << T >>  << A >>
On Thu, 01 Jul 1999 10:06:33 -0700, Aliens from the 3rd dimension made
Peter Alfke <peter@xilinx.com> write:
>WildBeach wrote:
>
>>
>>
>> So, a PLD family designed by people who don't "understand programmable logic",
>> bought by people who were silly enough to purchase something designed by
>> (claimed) incompentents, and supported by people that don't know how to spell.
>>
>> Sorry, couldn't resist :-), you left yourself too open.

I've tried to stay away from commenting...but now I must utter a few
words. The CoolRunner family was designed by very competent folks who,
in fact, were there designing the very first PLDs (PLAs) way back when
Signetics was a brand (ie pre-MMI).

The primary issue that makes this a win for my former colleagues in
the CoolRunner group *and* a win for Xilinx is the relative marketing
and sales strengths of the two companies. Philips has a broad
portfolio of products that are both easier to sell to a mass market,
and far more difficult to sell to targeted accounts. Bottom Line:
CPLDs were given a time slice by the average Philips sales guy that
was no where near 100%. The CoolRunner group, in a company like
Xilinx, will have a sales force that is 100% dedicated to selling only
programmable logic, and will promote the product that makes sense to
each customer.

It is my understanding that the 3rd generation of the CoolRunner
family is going to market with Xilinx's support (the press release
went out last week) - so I fully believe that they want to make this
group a successful part of their portfolio. So I don't believe that
it's 'Goodbye CoolRunner'. Interestingly enough, XPLA3 features full
PLAs - I can't help to think that they've "Gone Back to the Future"
and I wish all of them great success in this endeavor.

- Mark Aaldering

(I pitched the original business plan to the CEO of Philips
Semiconductors. However I speak only for myself, and none of the above
statements are (or should be construed to be) statements of my
employer.)
Mark Aaldering
Mark.Aaldering@ieee.org

Article: 17131
Subject: neuron logic
From: jhallen@world.std.com (Joseph H Allen)
Date: Thu, 1 Jul 1999 19:56:21 GMT
Links: << >>  << T >>  << A >>
Has anyone tried to design logic with neurons?  Here is a summary of what
neurons do:

They are running integrators with sloop- the "resting" potential is -90mV. 
When a threshold of -60mV is reached, the neuron fires giving an "action
potential"- a +50mV pulse of about 1ms in duration.  These pulses are always
the same no matter how strong the input is.  Inputs are ignored during the
pulse, and following the pulse the integrator is reset to about -110mV, so
greater than normal input is needed to fire the neuron for the following 3ms
or 4ms, until the value returns to the resting potential.

There are several types of input synapses that neurons can have.  The most
common "many-to-one" inputs have weights of relatively small magnitudes- one
input pulse can change the value of the integrator by only -2mV - 2mV. 
However, synapses can have a behaviour called facilitation, where successive
pulses each have greater effect- up to a maximum magnitude of about +/-10mV
per pulse.  Facilitation dies away in 20ms or so if there are no input
pulses.  When the neuron fires, the facilitation is not effected (it's
strictly a property of the synaps).

Over longer period of times (seconds) synapses get tired (they run out of
neurotransmitter), and become less sensitive.

There are also one-to-one inputs, which cause the neuron to fire one pulse
for any input and one-to-many inputs, which cause the neuron to fire a burst
of pulses for one inputs pulse.  These synapses are much less common and
tend to be in specialized nerons (muscles have one-to-one inputs, and
certain spinal cord neurons have one-to-many neurons).

Pulses travel at about 50 meters/second.  Each input has a delay of about
.5ms.  The highest pulse frequency is about 1000Hz, but 10-30Hz is more
common.  Neurons typically have 100 inputs, but they may have as low as 10
or as many as 1000.  The typical small dimension for a neuron is
10-100microns.  The cerebral cortex is about 600cm^3- so it has perhaps 20
billion neurons.  It's speed is something like 100T 7-bit adds per second-
about 10,000 pentium IIIs.  On the other hand, if you consider each synaps
to be a memory byte, the memory bandwidth is something like 100T bytes per
second, or something like 50,000 AGP slots operating at full blast in
parallel.

Anyway, the interesting thing about trying to implement logic in them is the
question of how to represent state.  In a "one hot bit" design, I'm guessing
that you want two neurons in feedback configuration.  A "1" is indicated
when they are oscillating.  You could then make a shift-register counter
pretty easily: send a pulse train in to all of these currently off "bits",
only the LSB is sensitive enough to start oscillating.  These cause the
second bit to precharge enough so that the next bit is triggered on the next
pulse train.  This second bit sends inhibitory signals to the first bit to
clear it.

I'm not sure if you can make a simpler representation scheme.  It would be
nice if you could use the charge in the neuron to represent a bit, but it
would have to be refreshed, and on top of that, reading is destructive.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 17132
Subject: Re: OrCAD (was "Re: ALTERA GDF to VHDL QUESTION")
From: mench@mench.com
Date: 1 Jul 1999 16:53:33 -0400
Links: << >>  << T >>  << A >>
On Thu, 01 Jul 1999 14:39:47 -0400, in comp.lang.vhdl Rickman
<spamgoeshere4@yahoo.com> wrote in article
<377BB5F3.6DB0AE98@yahoo.com>:
> Jaya Rajesh wrote:
>> I don't think it is possible with altera maxplusII. After finishing the
>> VHDL files, I'm using Orcad Capture for creating the top level block
>> diagram and VHDL file.
>
> [snip]
>
> How far have you gotten? Are you using the new release 9 software or
> the older version 7? Are you having any problems with the VHDL
> synthesis and simulation?

I'd be interested in hearing, too....

> I liked the fact that I could do a VHDL simulation of my entire
> design including the schematic portions. I didn't like the fact that
> I couldn't simulate anything because the simulator would crash every
> third time I ran it.

Well, if I do say so myself, version 9 is *much* better when it comes
to both performance, compliance, and lack of bugs than 7.1.

Rick, I hope you'll try again when you next need to simulate including
schematics.  Try the free demo version on the web page whenever you're
ready.

Paul


-- 
Paul Menchini          | mench@mench.com |"The last thing I want to do is
OrCAD                  | www.orcad.com   | spread fear, uncertainty and
P.O. Box 71767         | 919-479-1670[v] | doubt in the users' minds."
Durham, NC  27722-1767 | 919-479-1671[f] |  --Don Jones, MS's Y2K Product Mgr

Article: 17133
Subject: Re: newbie -- What's the best way to get started?
From: Barry Gershenfeld <barryg@centercomm.com>
Date: Thu, 01 Jul 1999 14:10:51 -0700
Links: << >>  << T >>  << A >>
Steven K. Knapp wrote:
> 
> There are several companies that provide free or low-cost software for FPGAs
> and CPLDs.  Check out The Programmable Logic Jump Station at
> http://www.optimagic.com/lowcost.shmtl.  The site also has links to 
                                    ^^^
                                   shtml

Moral: NEVER type a URL--paste it!

:-)  Barry

Article: 17134
Subject: Re: FGPA Servo Motor Controller
From: tryggvem@my-deja.com
Date: Thu, 01 Jul 1999 23:28:30 GMT
Links: << >>  << T >>  << A >>
In article <7l8ou8$4eo@dfw-ixnews17.ix.netcom.com>,
  "EKC" <NOSPAMalpha3.1@ix.netcom.com> wrote:
>     I am attempting to build a PWM Servo Motor Controller card based on an
> FPGA. I was wondering if anyone had any pointers to literature or other
> information sources that could help me design such a system. I haven't
> decided which FPGA vendor I will be using, so I would appreciate any
> suggestions.

.... Hello! We have been implementing this in some FPGA's! Together with our
partners we have products running at customers. To make the control even more
dynamic, you can add a soft cpu core to perform some of the calculations, but
the improvement/possibility depends on sample rate and precision of the
regulation for the overall system.
-----------------------------------------------------------------------------
---------------------- Both the DC Motor Behavioural and its implementation
can easy be modeled in VHDL. The behavioural model of the motor can form a
useful test-bench in the hardware design process. The VHDL components of the
system are parameterized, which means that their values can be changed
according to the operating conditions, or if the control strategy is changed
in some extent then there is no need to change the hardware. This even
implies additional axis and/or number of phases.
-----------------------------------------------------------------------------
---------------------- Control of a servomotor requires the main frame of the
motor, angle and angular velocity detectors,  current and voltage detectors,
a transistor PWM inverter, and a semiconductor power converter. In addition,
the motor driver requires current, velocity  and position controllers. The
control system consists of  an inner feedback loop to control the current
(and hence torque), an outer loop to control speed, and a further outer loop
to control position.

A trajectory generator produces a linear speed slope, which corresponds to an
S-shaped position slope. Hereby all discontinious setpoint behaviour is
avoided, allowing a stiff servo with constant parameters although soft start
and stop is supported.

To reduce the need of sensors a current estimator model and a velocity
estimator model of the motor system can be introduced. The rotational angle
of the motor is calculated by counting the pulses coming from the position
encoder, a speed estimate is also obtained by counting the number of pulses
per time unit. The position regulator get it reference from the trajectory
generator that optimizes the motor movment, and the position counter feedback
for the actual position. The velocity regulator, the velocity estimator value
and the difference between the reference position and  the position feedback
quantities (including the speed feed_forward value) are used as the current
command,  this current value is compared with the current estimator and
further modulated by the PWM. The current estimator get feedback values from
the velocity estimator, the actual current and limiter reference current
comparator. If the servo motor is a one phase dc motor the PWM is directly
connected to the motor.
-----------------------------------------------------------------------------
---------------------- For further information, (some part of our SMCS
library could be given to you as shareware/GPL) contact me !

Tryggve Mathiesen
ASIC/FPGA Consultant
Enator Elektroniksystem Sweden
Member of Xilinx XPERTs
mail: tryggvem@my-deja.com


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.

Article: 17135
Subject: Re: FGPA Servo Motor Controller
From: sja@gte.net (Steven J. Ackerman)
Date: Fri, 02 Jul 1999 01:26:58 GMT
Links: << >>  << T >>  << A >>
On Wed, 30 Jun 1999 00:00:48 GMT, jhallen@world.std.com (Joseph H
Allen) wrote:

>In article <7l8ou8$4eo@dfw-ixnews17.ix.netcom.com>,
>EKC <NOSPAMalpha3.1@ix.netcom.com> wrote:
>>    I am attempting to build a PWM Servo Motor Controller card based on an
>>FPGA. I was wondering if anyone had any pointers to literature or other
>>information sources that could help me design such a system. I haven't
>>decided which FPGA vendor I will be using, so I would appreciate any
>>suggestions.
>
>National has a PID-compensated 32-bit PWM servo motor controller chip (but I
>can't remember the number, but it was quite expensive ($45 in singles)). 
>Anyway, it's a completely straightforward implementation of a PID
>compensator followed by a PWM modulator with quadrature inputs to measure
>the rotor angle.  It used a single difference for the D and the integrators
>(accumulators, really) had settable limits to prevent correction magnitudes
>from getting really out of hand.  The controlled variable was angle, but a
>ramp generator was provided to generate a constant speed (overflow is a
>non-issue if the word lengths are all the same).  It should be very easy to
>implement this in an FPGA since it doesn't have to be very fast- the most
>difficult circuit will be the multiplier or the sequencer.  The NS chips cut
>corners by only allowing limited ranges in some of the coefficients, so you
>should try to find the datasheet for these hints.  It might be possible to
>do this with a PIC, which would be easier unless you need the FPGA for other
>hardware.
>-- 
>/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
>int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
>+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
>]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Would this be the National LM628 / LM629 ?


--
Steven J. Ackerman, Consultant
ACS, Sarasota, FL
sja@gte.net
http://www.acscontrol.com

Article: 17136
Subject: Re: FGPA Servo Motor Controller
From: jhallen@world.std.com (Joseph H Allen)
Date: Fri, 2 Jul 1999 03:21:08 GMT
Links: << >>  << T >>  << A >>
In article <377c171b.46757519@news.gte.net>,
Steven J. Ackerman <sja@gte.net> wrote:

>Would this be the National LM628 / LM629 ?

That sounds right.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 17137
Subject: Re: ABL-Problem (XILINX CPLD)
From: Benedikt Huber <bhuber@brd.de>
Date: Fri, 02 Jul 1999 12:46:04 +0200
Links: << >>  << T >>  << A >>
Hi Martin, 

I tried (with a lattice device)
something like 

WHEN (MODE_MONITOR == 1) 
  THEN RAM_ADDRESS = RAM_ADRESS;

oder so and it worked

Tschau, Beni

Martin Maurer wrote:
> 
> Hello,
> 
> i use the following code fragment in one of my abel-programmes for
> XILINX-CPLD 95108. I have a 18 Bit Counter. When MODE_MONITOR is 1,
> i want to select (WITH SEL1248 == 1,2,3 or 4) different clocks. If the
> counter reaches the top (A17 goes to 1), the counter should stop.
> In the other mode (MODE_MONITOR == 0), i want to increment the counter
> by SEL_BYTE (no stop).
> 
> (RAM_ADDRESS is an array of 'reg', RAM_A17 is 'com'
>  SEL1248 are 2 'reg' and MONITOR_ALWAYS is also 'reg')
> 
> I have 2 problems:
> 1) In MODE_MONITOR == 1 it doesn't stop ! I see the RAM_A17 toggling,
>    but counter doesn't stop.
> 2) In manual mode (MODE_MONITOR == 0) i toggle SEL_BYTE, but counter
>    doesn't move...For debugging reasons i have copied the SEL_BYTE
>    to an output pin, the pin is toggling fine.
> 
> Here is my code fragment:
> 
> WHEN (MODE_MONITOR & SEL1248 == 0) & (!RAM_A17 # MONITOR_ALWAYS)
> THEN RAM_ADDRESS.CLK = !TT3;
> ELSE
> WHEN (MODE_MONITOR & SEL1248 == 1) & (!RAM_A17 # MONITOR_ALWAYS)
> THEN RAM_ADDRESS.CLK = !TT2;
> ELSE
> WHEN (MODE_MONITOR & SEL1248 == 2) & (!RAM_A17 # MONITOR_ALWAYS)
> THEN RAM_ADDRESS.CLK = !TT1;
> ELSE
> WHEN (MODE_MONITOR & SEL1248 == 3) & (!RAM_A17 # MONITOR_ALWAYS)
> THEN RAM_ADDRESS.CLK = !TT0;
> ELSE
> WHEN !MODE_MONITOR
> THEN RAM_ADDRESS.CLK = !SEL_BYTE;
> ELSE RAM_ADDRESS = 0;
> 
> RAM_ADDRESS := RAM_ADRESS + 1;
> RAM_ADDRESS.AR = WANT_REWS;
> LPT_READY = RAM_A17;
> 
> Greetings,
> 
>     Martin Maurer (maurerm@in.tum.de)
Article: 17138
Subject: Re: ALTERA GDF to VHDL QUESTION
From: Jaya Rajesh <raj@philabs.research.philips.com>
Date: Fri, 02 Jul 1999 09:44:20 -0400
Links: << >>  << T >>  << A >>


Rickman wrote:

> Jaya Rajesh wrote:
> >
> > I don't think it is possible with altera maxplusII. After finishing the
> > VHDL files, I'm using Orcad Capture for creating the top level block
> > diagram and VHDL file.
> >
> > Regards,
> > Jaya Rajesh.
>
> Jaya,
>
> You are the first person I have heard from who is designing an FPGA
> using Orcad and VHDL.

Rick,

I'm not designing an FPGA using Orcad.  Orcad is used just for creating a top
level DSN file equivalent to altera GDF. (If I have the vhdl files, it is
easy to make a dsn in Orcad.).  It creates a VHDL netlist so that I dont have
to type the componets and ports.(Actually that is the only step I'm gaining
and that was Asher's question I guess!) I have Orcad (version 9) in my PC for
Schematic Cpature.
Also, I'm not using ORcad for synthesis or simulation.(I don't think it's a
good idea! ) .I have Synplify and Modelsim for that.

Regards,
Jaya Rajesh.



> I attempted this a year ago using version 7.1. The
> software worked so poorly and Orcad support was so unhelpful that I
> finally gave up and bought the Xilinx Foundation package to finish the
> design.
>
> How far have you gotten? Are you using the new release 9 software or the
> older version 7? Are you having any problems with the VHDL synthesis and
> simulation?
>
> I liked the fact that I could do a VHDL simulation of my entire design
> including the schematic portions. I didn't like the fact that I couldn't
> simulate anything because the simulator would crash every third time I
> ran it.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

Article: 17139
Subject: Re: FW: Xilinx Acquisition of CoolRunners
From: Steven Casselman <sc@vcc.com>
Date: Fri, 02 Jul 1999 09:56:05 -0700
Links: << >>  << T >>  << A >>


WildBeach wrote:

> >Just the oppopsite:
> >Welcome Coolrunner, now you will  be supported by a company that understands
> >Programmable Logic.
> >
> >Peter Alfke
> >
>
> So, a PLD family designed by people who don't "understand programmable logic",
> bought by people who were silly enough to purchase something designed by
> (claimed) incompentents, and supported by people that don't know how to spell.
>
> Sorry, couldn't resist :-), you left yourself too open.

I think Peter met to say

"Welcome Coolrunner, now you will  be supported by a company that understands
the Programmable Logic market."

The PLD/FPGA market is wild. Prices are droping FAEs are
workin their butts off in the field. If a company can not work the
market and infiltrate the field it does not matter how good the
devices are that engineers design.

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 17140
Subject: Re: FW: Xilinx Acquisition of CoolRunners
From: Richard.Radix@XYBTinternet.com (Richard Dungan)
Date: Fri, 02 Jul 1999 17:13:06 GMT
Links: << >>  << T >>  << A >>
Brian Boorman <XZY.bboorman@harris.com> wrote:

>Dear Valued CoolRunner Customer,
>
>We are pleased to inform you of a change in ownership of the CoolRunner
>product
>family.  Philips Semiconductors has elected to sell its CoolRunner
>Programmable
>Logic business to Xilinx Inc.

[snip]

I think this is good news.

Philips, sadly, is characterized by excellent R&D but IMHO a sales and support
organization of mind-numbing incompetence. Xilinx cannot fail but to improve on
this.

Richard

------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
      Spamtrapped: Remove the XY
---------------------------------------

Article: 17141
Subject: Re: FW: Xilinx Acquisition of CoolRunners
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 02 Jul 1999 10:21:16 -0700
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> What about Atmel?  They sure aren't paying the bills with AT40K sales.
>

I forgot them completely, sorry.
So, Lucent and Atmel are now the only remaining  companies that handle their PLD
business as a sideline, deriving most of their revenues from other product lines. All
other PLD companies are "pure players".

Peter Alfke


Article: 17142
Subject: Re: 100 Billion operations per sec.!
From: Steven Casselman <sc@vcc.com>
Date: Fri, 02 Jul 1999 10:21:24 -0700
Links: << >>  << T >>  << A >>


Tom Kean wrote:

> > I think the above people did great work. However I don't think my paper
> > http://www.vcc.com/nsf1.html  (1987)
> > should be discounted just because I'm a commerical person
> > concerned about patent rights.
>
> I was not aware of this reference.  It is certainly very early for the
> FPGA based computing machines.  Did NSF or VCC publically disclose the
> full proposal or the abstract at the time it was submitted?

Yes if you look at the cover page you can see ( box number 6 from
the bottom) I've checked the "government may disclose abstract
if proposal does not win" box.

>
>
> > Also in the research I did
> > I found many comments like "one design per program." As
> > the goal. This was the main foucs of these groups up untill
> > the early 90's (correct me if I'm wrong).  In my final SBIR report
> > (jan 90) I cover runtime reconfiguration among other things
> > such as compiling from C or ADA.
>
> Run time reconfiguration is found in many early references.  Using
> multiple
> configurations for one design is not common.  I think I remember a
> patent
> from the mid 1980's which had this feature but I'd need to check.
>
> I would like to get a copy of your final SBIR report if that is possible
> (especially
> if it was published in 1990)

I'll scan in the 1988 paper I won my first SBIR with and
the final report adn put them up on the web.

> .
>
> > Look at
> > http://www.computer-museum.org/groups/Slide/114.html
> > Note the quote "instructions could be modified by the computer
> > as it went along". So John von Neumann invented the reconfigurable
> > computer.
> >
>
> That is arguable: his work on cellular automata is certainly closely
> related. I'm also not 100% convinced by Estrin since he used patch panels
> and
> plug in modules rather than electronic switches under memory control in the
>
> paper I read.  However, I have never put a lot of effort into answering the
>
> question 'who was first'. Prior art from the 70's is just as good as prior
> art
> from the 50's -- actually its usually better because it is easier to relate
> to
> the claim language in the more recent patents.
>

Well someone should find out who was first. Otherwise
the world will think Gilson did everything while the rest
of us just sat on our ass.

>
> >
> > Many will argue but I contend that modern reconfigurable
> > computers were not possible untill the invention of the FPGA
> > by Ross Freeman.
> >
>
> I would argue with that.  Its more like modern reconfigurable computers
> were not possible before CMOS technology got to a certain level of
> capability.  Ross Freeman's genius was building a team that could turn
> his idea into an industry and hitting the market just when process
> technology made the overhead of reconfiguration economically viable.
>
> Tom.

I certainly agree that Ross put together a great team.
But by that logic Jules Verne invented interplanetary
flight but did not have the team to make it happen.



--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 17143
Subject: Re: Synplify problem - is it just me?
From: ehiebert@my-deja.com
Date: Fri, 02 Jul 1999 21:55:26 GMT
Links: << >>  << T >>  << A >>
I spoke to Synplicity about this exact problem. I was trying to code a
div, and here is what they said.

"Division is only supported for compile time constants that can be
guarenteed to be a power of 2."

The key here is compile time. In order to do a division of vectors, I
had to write my own divide unit. The problem is, Synplify 5.1.4 has
problems synthesizing my divide unit. It is optimizing out the divisor
register that I have coded. no word back from Synplicity on this one
yet, except to say this is a new bug..... REALLY?!?!?

Eldon.

In article <376577f7.2542275@news.u-net.com>,
  jonathan@oxfordbromley.u-net.com wrote:
> Synplify version 5.1.1 (free with Actel Desktop) can't cope with the
> following code. A very old version of Synplify (2.5) processes it
> just fine;  FPGA Express has no problem.  The compiler blows up
> on the line indicated, but in fact the culprit is a couple of
> lines later:  if I make the divisor a hard-coded constant instead
> of the generic, all is well.  Before I whinge to Synplicity, has
> anyone come across this one?  BTW, I know that the generic 'span'
> has to be a power of 2;  in the real thing there's an assert to
> test that.  This example intentionally lobotomised.
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity accum is
>    generic (span: natural := 8);
>    port (
>       clk, rst, UpNotDown: in std_logic;
>       sigma: out integer range -span to span-1
>    );
> end accum;
>
> architecture counter of accum is
>    -- compiler blows up at the following line:
>    signal q: integer range -span*span to span*span-1;
> begin
>    sigma <= q/span;  -- change to "q/8" and all is OK
>    count_proc: process (clk, rst)
>    begin
>       if rst='1' then
>          q <= 0;
>       elsif rising_edge(clk) then
>          if UpNotDown='1' then
>             q <= q+1;
>          else
>             q <= q-1;
>          end if;
>       end if;
>    end process;
> end counter;
>
> Jonathan Bromley
>
>


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Article: 17144
Subject: Re: neuron logic
From: "Wade D. Peterson" <peter299@maroon.tc.umn.edu>
Date: Fri, 2 Jul 1999 17:35:03 -0500
Links: << >>  << T >>  << A >>
Joseph H Allen <jhallen@world.std.com> wrote in message
news:FE7JDx.G85@world.std.com...
> Has anyone tried to design logic with neurons?
[SNIP]

I believe that any information process, if described in sufficient detail, can
be replicated.  [At least I can't think of any exceptions to that].  If the
neuron really behaves like you say, then it should be possible to replicate it.
I guess that goes for the whole human brain as well.

You might want to take at neural networks.  They were really hot a few years
ago, and there were quite a few chips designed around that concept.

Wade Peterson
Silicore Corporation
http://www.silicore.net/


Article: 17145
Subject: Re: 100 Billion operations per sec.!
From: Tom Kean <tom@algotronix.com>
Date: Sat, 03 Jul 1999 00:44:35 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Transfer-Encoding: 7bit





> >
> > I would argue with that.  Its more like modern reconfigurable computers
> > were not possible before CMOS technology got to a certain level of
> > capability.  Ross Freeman's genius was building a team that could turn
> > his idea into an industry and hitting the market just when process
> > technology made the overhead of reconfiguration economically viable.
> >
> > Tom.
> 
> I certainly agree that Ross put together a great team.
> But by that logic Jules Verne invented interplanetary
> flight but did not have the team to make it happen.

I don't think thats a fair analogy: the guys in the 60's and 70's were
engineers
not science fiction writers and some of them built working
systems.  They published literaly hundreds of technical papers.  They
had configuration memory controlling programmable function units and
switches.  Their big problem was that their configuration memory was
shift registers
built from logic gates and their multiplexers were also built from logic
gates
and you did not get that many logic gates on a chip at that time.




Tom.
--------------F5BB4FEE477BAE41B9F48706
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begin:vcard 
n:Kean;Tom
tel;fax:UK +44 131 556 9247
tel;work:UK +44 131 556 9242
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org:Algotronix Ltd.
adr:;;P.O. Box 23116;Edinburgh;;EH8 8YB;Scotland
version:2.1
email;internet:tom@algotronix.com
title:Director
note:Web Site: www.algotronix.com
x-mozilla-cpt:;4768
fn:Tom Kean
end:vcard

--------------F5BB4FEE477BAE41B9F48706--

Article: 17146
Subject: Q: Floating point on fpga?
From: Roland Paterson-Jones <rolandpj@bigfoot.com>
Date: Sat, 03 Jul 1999 09:08:40 +0100
Links: << >>  << T >>  << A >>
Hi

It has been variously stated that fpga's are no good for floating point
operations. Why? As I see it, floating point operations are typically
just shifted integer operations. Is the bit-width problematic?

Thanks for any help/opinion
Roland

Article: 17147
Subject: Using Block SelectRAM+ in Virtex
From: ronak@hclt.com
Date: Sat, 03 Jul 1999 15:54:50 GMT
Links: << >>  << T >>  << A >>
Hi,

   Does anybody know how to use Virtex Block ram in Verilog
HDL based Synopsys synthesis flow. The datasheets and app
notes gives only info about architecture and symbols but
not about how to put it in HDL based flow.

Thanks in advance
-ronak


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Article: 17148
Subject: Re: Floating point on fpga, and serial FP adders
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Sat, 03 Jul 1999 17:44:03 GMT
Links: << >>  << T >>  << A >>
Roland Paterson-Jones wrote in message <377DC508.D5F1D048@bigfoot.com>...
>It has been variously stated that fpga's are no good for floating point
>operations. Why? As I see it, floating point operations are typically
>just shifted integer operations. Is the bit-width problematic?

For 16-bit floats with (say) 10 bit mantissas, FPGAs should be *great* for
floating point.  Indeed problems start with the wider bit-widths.  The
area-expensive (and worse than linear scaling) FP components are the barrel
shifters needed for pre-add mantissa operand alignment and post-add
normalization in the FP adder, and of course the FP multiplier array.

The FCCM papers on this subject include:

Ligon et al, A Re-evaluation of the practicality of floating-point
operations on FPGAs, FCCM 1998

Louca et al, Implementation of IEEE single precision floating point addition
and multiplication on FPGAs, FCCM 1996

Shirazi et al, Quantitative analysis of floating point arithmetic on FPGA
based custom computing machines, FCCM 1995

and the neat Leong paper on avoiding the problem entirely,

Leong et al, Automating floating to fixed point translation and its
application to post-rendering 3D warping, FCCM 1999


See the Ligon paper for a nice presentation of speed-area tradeoffs of
various implementation choices.  Ligon estimates their single-precision FP
adder resource use at between 563 and 629 LUTs -- 36-40% of a XC4020E.  Note
this group used a synthesis tool; a hand-mapped design could be smaller.

Put another way, that single precision FP adder is almost twice the area of
a pipelined 32-bit RISC datapath.  Ouch.


The rest of this article explores ideas for slower-but-smaller FP adders.

The two FP add barrel shifters are the problem.  They each need many LUTs
and much interconnect.  For example, a w-bit-wide barrel shifter is often
implemented as lg w stages of w-bit 2-1 muxes, optionally pipelined.

Example 1: single-precision in << s, w=24
  m0 = s[0] ? in[22:0] << 1 : in;
  m1 = s[1] ? m0[21:0] << 2: m0;
  m2 = s[2] ? m1[19:0] << 4 : m1;
  m3 = s[3] ? m2[15:0] << 8 : m2;  // 16 wires 8 high
  out = s[4] ? m3[7:0] << 16 : m3; // 8 wires 16 high
----
5*24 2-1 muxes = 120 LUTs

Example 2: double-precision in << s, w=53
  m0 = s[0] ? in[51:0] << 1 : in;
  m1 = s[1] ? m0[50:0] << 2: m0;
  m2 = s[2] ? m1[48:0] << 4 : m1;
  m3 = s[3] ? m2[44:0] << 8 : m2; // 45 wires 8 high
  m4 = s[4] ? m3[36:0] << 16 : m3; // 37 wires 16 high
  out = s[5] ? m4[20:0] << 32 : m4; // 21 wires 32 high
----
6*53 2-1 muxes = 318 LUTs

In a horizontally oriented datapath, the last few mux stages have many
vertical wires, each many LUTs high.  This is more vertical interconnect
than is available in one column of LUTs/CLBs, so the actual area can be much
worse than the LUT count indicates.


BUT we can of course avoid the barrel shifters, and do FP
denormalization/renormalization iteratively.

Idea #1: Replace the barrel shifters with early-out iterative shifters.  For
example, build a registered 4-1 mux: w = mux(in, w<<1, w<<3, w<<7).  Then an
arbitrary 24-bit shift can be done in 5 cycles or less in ~1/3 of the area.
For double precision, make it something like w = mux(in, w<<1, w<<4, w<<12),
giving an arbitrary 53-bit shift in 8 cycles.


Idea #2: (half baked and sketchy) Do FP addition in a bit- or nibble-serial
fashion.

To add A+B, you

1) compare exponents A.exp and B.exp;
2) serialize A.mant and B.mant, LSB first;
3) swap (using 2 2-1 muxes) lsb-serial(A.mant) and lsb-serial(B.mant) if
A.exp < B.exp
4) delay lsb-serial(A.mant) in a w-bit FIFO for abs(A.exp-B.exp) cycles;
5) bit-serial-add delay(lsb-serial(A.mant)) + lsb-serial(B.mant) for w
cycles
6) collect in a "sum.mant" shift register
7) shift up to w-1 cycles (until result mantissa is normalized).

It may be that steps 4 and 6 are quite cheap, using Virtex 4-LUTs in shift
register mode -- they're variable tap, right?

It is interesting to consider eliminating steps 2, 6, and 7, by keeping your
FP mantissa values in the serialized representation between operations,
counting clocks since last sum-1-bit seen, and then normalizing (exponent
adjustment only) and aligning *both* operands (via swap/delay) on input to
the next FP operation.  A big chained data computation might exploit many
serially interconnected serial FP adders and serial FP multipliers...

Is this approach better (throughput/area) than a traditional pipelined
word-oriented FP datapath?  Probably not, I don't know.  But if your FP
needs are modest (Mflops not 100 Mflops) this approach should permit quite
compact FP hardware.

(Philip Freidin and I discussed this at FCCM99.  Thanks Philip.)

Jan Gray



Article: 17149
Subject: Re: FW: Xilinx Acquisition of CoolRunners
From: jim granville <Jim.Granville@DesignTools.co.nz>
Date: Sun, 04 Jul 1999 09:05:17 +1200
Links: << >>  << T >>  << A >>
Mark Aaldering wrote:
> It is my understanding that the 3rd generation of the CoolRunner
> family is going to market with Xilinx's support (the press release
> went out last week) - so I fully believe that they want to make this
> group a successful part of their portfolio. So I don't believe that
> it's 'Goodbye CoolRunner'. Interestingly enough, XPLA3 features full
> PLAs - I can't help to think that they've "Gone Back to the Future"
> and I wish all of them great success in this endeavor.
> 
> - Mark Aaldering

 Is this Full PLA's something new, or just a spin on the std XPLA,
that actually delivers less  ?

 The 'old' XPLA has 36 In -> 32 PLA, and also 16 x 5 Dedicated OR array.
Seems this progress trading from 112 wide OR, to 48 wide or, and the
only design
it opens is one needing more than 37, and less than 48 OR terms.
 Conversely, any existing XPLA design with > 48 total OR terms ( average
3/cell )
will not fit in the new model ?

 The plus side will be these new devices can be smaller/cheaper than the
older ones


> The first family member (part number PZX3256) is a 256-macrocell device and will be followed
>  by 192, 128 and 64-macrocell devices.  The XPLA3 architecture consists of multiple logic blocks
>  interconnected by a single level ZIA (Zero power Interconnect Array).  Each logic block contains
>  a full 36 by 48 PLA, enabling the macrocell to use only the product terms it needs.
>  The PZX3256 Samples of the 256 macrocell CPLDs will be available early
>  Q4 '99.  Production pricing for the 256 Macrocell PZX3256 in high-volume quantities is $7.90.


 Does anyone have a number for the Sales of Coolrunner - one press
release
mentioned $10M - sounded low ?

 jg.
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