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Messages from 16975

Article: 16975
Subject: Re: FPGA in Wireless Designs
From: fliptron@netcom.com (Philip Freidin)
Date: Mon, 21 Jun 1999 19:50:56 GMT
Links: << >>  << T >>  << A >>
In article <7kljvu$mik$1@news.btv.ibm.com> "Anurag" <anurag@earthling.net> writes:
>Hi,
>Can a FPGA's be used in Wireless Telecom applications ( e.g.  3G wireless,
>software radios, wireless base-stations.....etc.) If yes, what specific
>functions could the FPGA perform in these designs ?

Yes. The FPGAs can be used for most of the DSP functions (in fact, many 
of the DSP functions you want to do will be beyond traditional DSP 
chips), as well as the normal system type stuff around the CPU chips, 
doing interface, data buffering, bus interface.

The DSP functions include modulation, filtering, tracking, interleaving,
CRC, Reed-Solomon, Viterbi, Spread spectrum encoding/decoding, test
pattern generation and checking, Signal acquisition, RSSI, etc.


Article: 16976
Subject: Question: Does FPGA Express 3.2 support RPMs?
From: Steve Charlwood <s.m.charlwood@bham.ac.uk>
Date: Mon, 21 Jun 1999 22:22:08 +0100
Links: << >>  << T >>  << A >>
Hi.

I'm currently using the Metamor synthesis tool for targetting Xilnix
XC4000-series devices, and I use the Xilinx system of
relationally-placed macros (RPMs) to get good density results. I also
use FPGA Express 3.0, which does not correctly support the generic
attribute passing necessary - does anyone know if this has been fixed
for version 3.2?

Regards,

Steve


_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/

Digital Systems & Vision Processing Group 
School of Electronic & Electrical Engineering
University of Birmingham, Edgbaston, Birmingham, B15 2TT 
e-mail: steve.charlwood@iname.com
tel: +44 (0)121-414-4340 (shared)/fax: +44 (0)121-414-4291

_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 16977
Subject: Request for information on discontinued Xilinx XC4000-series variants
From: Steve Charlwood <s.m.charlwood@bham.ac.uk>
Date: Mon, 21 Jun 1999 22:27:10 +0100
Links: << >>  << T >>  << A >>
Hi.

Does anyone have, or could direct me towards, datasheets or other
information on the following XC4000-series variants?

XC4000, XC4000A, XC4000D, XC4000H, XC4000L

I would like to be able to track the technological and architectural
changes made to the XC4000-series chronologically, and look at the
factors which influenced the changes. 

Any help would be appreciated.

Regards,

Steve


_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/

Digital Systems & Vision Processing Group 
School of Electronic & Electrical Engineering
University of Birmingham, Edgbaston, Birmingham, B15 2TT 
e-mail: s.m.charlwood@bham.ac.uk
tel: +44 (0)121-414-4340 (shared)/fax: +44 (0)121-414-4291

_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 16978
Subject: Re: FPGA in Wireless Designs
From: Jonathan Feifarek <feifarek@removethis.ieee.org>
Date: Mon, 21 Jun 1999 16:00:33 -0600
Links: << >>  << T >>  << A >>
Anurag,
All of the functions performed in the digital domain can hypothetically
be performed in an FPGA.  In actuality, the amount of processing
capability and frequency requirements may limit what you implement in
FPGAs.
FPGAs arranged in a symmetrical way with programmable interconnects (and
usually an interface to a 'conventional' computer form a Reconfigurable
Computer (also known as Configurable Computer or Custom Computing
Machine).  For information on using a Reconfigurable Computer to
implement wireless, please check into the following link at the Virginia
Tech University: http://sss-mag.com/mprgbrf.html .
Another academic link is from Stanford University, which addresses the
problems in mobile communications:
http://umunhum.stanford.edu/res_html/darpa/radio.html 
In the commercial world, check out this site for existing hardware
products: http://www.pentek.com/ .   You may find their tutorial on
Digital Receivers very useful.
Jonathan Feifarek

Anurag wrote:
> 
> Hi,
> Can a FPGA's be used in Wireless Telecom applications ( e.g.  3G wireless,
> software radios, wireless base-stations.....etc.) If yes, what specific
> functions could the FPGA perform in these designs ?
> 
> Any help/reference would be appreciated !
> Thanks in advance.........
> Anurag

-- 
Jonathan F. Feifarek
Consulting and design
Programmable logic solutions
Article: 16979
Subject: Re: Virtex Boards
From: Steven Casselman <sc@vcc.com>
Date: Mon, 21 Jun 1999 15:24:16 -0700
Links: << >>  << T >>  << A >>


"Pawe³ J. Rajda" wrote:

> Steven Casselman wrote:
>
> > The Virtex daughter board will be $4995 for a V800.
>
> How much will be daugter boards for a V300 (if any)?
>

If we do one it would be $2K.


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 16980
Subject: pdf files
From: kfrod@my-deja.com
Date: Mon, 21 Jun 1999 22:24:39 GMT
Links: << >>  << T >>  << A >>
I am trying to convert a microsoft publisher file (.pub) for a pdf file
so that I can take it to a printer...  Is there a way to do this with
buting adobe acrobat?

THANKS!!!!!!!!


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 16981
Subject: Re: Request for information on discontinued Xilinx XC4000-series
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 21 Jun 1999 16:40:08 -0700
Links: << >>  << T >>  << A >>
You can look these up in the 1993 Xilinx Data book, or you can ask me specific
questions.

Peter Alfke, Xilinx Applications
======================================
Steve Charlwood wrote:

> Hi.
>
> Does anyone have, or could direct me towards, datasheets or other
> information on the following XC4000-series variants?
>
> XC4000, XC4000A, XC4000D, XC4000H, XC4000L
>
> I would like to be able to track the technological and architectural
> changes made to the XC4000-series chronologically, and look at the
> factors which influenced the changes.
>
> Any help would be appreciated.
>
> Regards,
>
> Steve
>
> _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
>
> Digital Systems & Vision Processing Group
> School of Electronic & Electrical Engineering
> University of Birmingham, Edgbaston, Birmingham, B15 2TT
> e-mail: s.m.charlwood@bham.ac.uk
> tel: +44 (0)121-414-4340 (shared)/fax: +44 (0)121-414-4291
>
> _/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/

Article: 16982
Subject: Re: Question: Does FPGA Express 3.2 support RPMs?
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Tue, 22 Jun 1999 03:43:46 GMT
Links: << >>  << T >>  << A >>
>I'm currently using the Metamor synthesis tool for targetting Xilnix
>XC4000-series devices, and I use the Xilinx system of
>relationally-placed macros (RPMs) to get good density results. I also
>use FPGA Express 3.0, which does not correctly support the generic
>attribute passing necessary - does anyone know if this has been fixed
>for version 3.2?

You can apply RLOC and RLOC_ORIGIN attributes in HDL to RPMs defined
elsewhere.  See http://www.xilinx.com/techdocs/4392.htm.

However (version 3.1) you can't *create* RPMs of FMAPs in structural HDL,
because it ignores explicit FMAPs.  See
http://www.xilinx.com/techdocs/4395.htm and my comments
http://deja.com/getdoc.xp?AN=478287358.

(Above comments refer to the FPGA Express 3.1 download available to Xilinx
Foundation Express customers.)

Jan Gray



Article: 16983
Subject: Xilinx "Virtex Configuration Architecture Advanced Users' Guide" appears
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Tue, 22 Jun 1999 05:08:26 GMT
Links: << >>  << T >>  << A >>
It includes specs and detailed examples including reconfiguration of a LUT,
and readback scenarios.  Interesting stuff, yields insight into the
underlying device architecture.  Not trivial but seems straightforward
enough.

See http://www.xilinx.com/xapp/xapp151.pdf.

If one is to go whole hog and partially reconfigure not just LUT entries,
but some interconnect too, it appears necessary to assert "GHIGH_B" status
during reconfiguration.  Apparently this eliminates internal output
contention by forcing all CLB outputs and signals to 1.  But I wonder what
happens to all of your not-to-be-reconfigured state (flip-flops and
selectRAMs and block RAMs) when all clocks, clock enables, and DINs suddenly
go high.  Perhaps you must stop your clocks (park them high) before
asserting GHIGH_B?

Jan Gray



Article: 16984
Subject: Availability of Parts
From: Allan James Cantle <a.cantle@nallatech.com>
Date: Tue, 22 Jun 1999 09:35:18 +0100
Links: << >>  << T >>  << A >>
We are not having any great difficulty in getting parts now. There are
some significant shipments of commercial grade parts coming into the UK
on the 25th June. 

Also, I understand that Xilinx have a large amount of Engineering Sample
stock sat on the shelves in the US, if this is acceptable.

Allan Cantle
Nallatech Ltd

-----Original Message-----
From: dwb105@york.ac.uk [mailto:dwb105@york.ac.uk]On Behalf Of Daryl
Bradley
Posted At: 18 June 1999 10:42
Posted To: fpga
Conversation: Virtex Boards
Subject: Re: Virtex Boards


Yeah, I heard that there was a minor?!?!?!?!?! well oky, bit of a
nightmare
problem getting parts from Xilinx at the moment.



Steven Casselman wrote:

> Daryl Bradley wrote:
>
> > that was our initial plan as well until the VW came out. Not too
sure other
> > than I received a mail about a Hot III PCI board.
> >
> >
>
> Yes we are working on a HOTIII, board prices
> will range from $995 to $4995.  The Virtex daughter
> board was taken off the site because we were thinking
> of just offering the daughter board with the HOTIII.
> We have PCBs in house for the daughter boards and we will build some
just
> as soon as we get some !@#$%^&* parts.  The Virtex
> daughter board will be $4995 for a V800. The pricing on the
> HOTIII will be _something_ like $995 for V100
> $1995 for V300 and $4,995 for V800.  Of course
> all these boards have one meg configuration caches and use
> the high speed Virtex parallel configuration port (PCP).
> Each board has 4 meg of fast SRAM (15ns or faster).
>
> All the above is advanced information and subject to change
> at any time.
>
> Thanks
> --
> Steve Casselman, President
> Virtual Computer Corporation
> http://www.vcc.com

--

Bio-Inspired Architectures
Department of Electronics
University of York, UK
http://www-users.york.ac.uk/~dwb105


Article: 16985
Subject: Re: Simple PCI card prototyping.
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Tue, 22 Jun 1999 10:14:25 GMT
Links: << >>  << T >>  << A >>
On 21 Jun 1999 15:05:44 GMT, "Austin Franklin" <austin@darkr9oom.com>
wrote:

>> 
>> As a matter of interest, when running this Spartan PCI interface as a
>> PCI slave, i.e. no DMA capability (in a normal PC), what sort of I?I
>> bandwidth do you get?
>
>
>In PCI, there really is no DMA, just target and master....  DMA has
>traditionally been though of as you program a start address and a length,
>and tell it to 'go' and the data is transferred without the CPU doing it. 

argh, I'm sorry, I accidentally obfuscated the question.

So let me try to rephrase it.

Assuming my back-end supports burst transfers (which it will, up to say
64 kilobytes), what I/O bandwidth can I expect to achieve if I rely on
the bus-mastering of a typical (PII/PIII) PC? 
 
>> In other words, do you need the full bus-mastering DMA core to get
>> 100-120MB/second?

Anyone?

(I am assuming the PC supports burst transfers to its system memory as a
slave.)

>As I said above, 'full bus-mastering' and 'DMA' are two different things. 

This I understand. 

But I also understand - perhaps incorrectly - that the DMA channels on
the motherboard are not capable of generating high-bandwidth PCI
traffic. Nor do I know how well memory reads/writes from the CPU can
generate long bursts, and therefore how well it can communicate with a
slave that supports long bursts...

Or whether I would have to generate them myself.

Which would necessitate bus mastering, in order to generate PCI bus
traffic independently of the CPU. I'm sorry I called that traffic DMA to
confuse the issue.

The nearest I have found to an answer on the Xilinx web site is a paper
"Approaching PCI bandwidth limits with FPGA's" which emphasises the
importance of long bursts, but doesn't really answer the question.

- Brian

Article: 16986
Subject: Re: Simple PCI card prototyping.
From: "Austin Franklin" <austin@darkr9oom.com>
Date: 22 Jun 1999 13:38:34 GMT
Links: << >>  << T >>  << A >>
> >> As a matter of interest, when running this Spartan PCI interface as a
> >> PCI slave, i.e. no DMA capability (in a normal PC), what sort of I?I
> >> bandwidth do you get?
> >
> >
> >In PCI, there really is no DMA, just target and master....  DMA has
> >traditionally been though of as you program a start address and a
length,
> >and tell it to 'go' and the data is transferred without the CPU doing
it. 
> 
> argh, I'm sorry, I accidentally obfuscated the question.
> 
> So let me try to rephrase it.
> 
> Assuming my back-end supports burst transfers (which it will, up to say
> 64 kilobytes), what I/O bandwidth can I expect to achieve if I rely on
> the bus-mastering of a typical (PII/PIII) PC? 

It depends who the master is, and who the target is.  A typical PC, with
the CPU doing the PCI burst mastering only does a limited number of
transfers per, depending on the CPU.  You can check the Intel spec sheets
to figure out that.

> >> In other words, do you need the full bus-mastering DMA core to get
> >> 100-120MB/second?
> 
> Anyone?
> 
> (I am assuming the PC supports burst transfers to its system memory as a
> slave.)
> 
> >As I said above, 'full bus-mastering' and 'DMA' are two different
things. 
> 
> This I understand. 
> 
> But I also understand - perhaps incorrectly - that the DMA channels on
> the motherboard are not capable of generating high-bandwidth PCI
> traffic.

You are right, the 8259 is basically an ISA device, and runs at about
floppy speeds ;-)

> Nor do I know how well memory reads/writes from the CPU can
> generate long bursts, and therefore how well it can communicate with a
> slave that supports long bursts...

Is this the same that I said above?  Sounds like it....and it has caused
many an engineer a headache.  Intel should include a REAL PCI 'DMA' in the
chip set, it's not that much silicon...
 
> Or whether I would have to generate them myself.  Which would necessitate
bus mastering,
> in order to generate PCI bus
> traffic independently of the CPU. 

If you were relying on the CPU to be the bus master (which is the only PCI
bus master in a typical PC, that can do 'generic' PCI transfers), you may
fall short of your target.  If this is the case, you probably need to put
it in your PCI interface.
 
> The nearest I have found to an answer on the Xilinx web site is a paper
> "Approaching PCI bandwidth limits with FPGA's" which emphasises the
> importance of long bursts, but doesn't really answer the question.

There is also the issue of the PCI latency timer.  It is suggested you
allow the BIOS to setup your latency timer.  You don't have to, but the
penalty is some other device can get locked out of using the PCI bus, and
therefore, can potentially drop data.  If you KNOW you can do LONG
transfers, with no other device needing the PCI bus, then it's an OK thing
to do, but in regular desktop PCs, this is a bad thing to do...

Basically, sounds like you need a first party burst master on your
board.....

Austin

Article: 16987
Subject: Synopsys DC & FPGA Compiler
From: vermon1055@my-deja.com
Date: Tue, 22 Jun 1999 13:54:14 GMT
Links: << >>  << T >>  << A >>
Hi,
I am a beginner for the FPGA synthesis.
I would very much appreciate your comments and
experiences on the following
question.

The tools that we currently have is Synopsys DC
(design compiler)(UNIX)
and Altera MAX plus II (PC).

I am trying to  synthesis the verilog code by
using Synopsys DC targeting
to the library provided by Altera(flex10k.db,
max7000.db,....). And then
save it as an EDIF format for Altera to do the
place & route.

What is the difference if I use the Synopsys FPGA
compiler instead of the DC?
(in turns of speed and area)

Do we really need to have the Synopsys  FPGA
compiler to do the job?

Thanks!


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 16988
Subject: ProASIC
From: "AK" <ak@mail.ru>
Date: Tue, 22 Jun 1999 19:29:41 +0530
Links: << >>  << T >>  << A >>
Hi,
what all can a proASIC ( from Actel Corp.) do that a FPGA can't ?
(As claimed by Actel) can I use an ASIC core & compile it to a proASIC 
chip ?

thanks........

Article: 16989
Subject: Re: Virtex Boards
From: kip@remove.this.cs.tut.fi (Kalle Palomäki)
Date: Tue, 22 Jun 1999 17:09:58 +0300
Links: << >>  << T >>  << A >>
In article <37695D10.24EE061C@vcc.com>, sc@vcc.com says...
> 
> Yes we are working on a HOTIII, board prices
> 
> All the above is advanced information and subject to change
> at any time.
> 

Could you please tell somekind of a preliminary schedule for the HOT III 
and/or for those Virtex daughter cards that can be connected to HOT 2?

When are they planned to be on the market?

	BR, 
		Kalle Palomäki, Tampere University of Technology
Article: 16990
Subject: FPGA benchmarks
From: Bernd Schmidt <bes@aifb.uni-karlsruhe.de>
Date: Tue, 22 Jun 1999 20:26:10 +0200
Links: << >>  << T >>  << A >>
Hello,

I am searching for benchmarks of circuit designs for FPGAs. Does anybody
know where I could get such benchmark data?

The benchmarks will be analyzed in order to obtain statistical results
for my master thesis. My thesis is dealing with FPGA task arrangement.

Thanks for each proposal

cheers

Bernd


Article: 16991
Subject: Re: Simple PCI card prototyping.
From: Steven Casselman <sc@vcc.com>
Date: Tue, 22 Jun 1999 13:25:04 -0700
Links: << >>  << T >>  << A >>
A PCI target on an computer using an Intel PCI
bridge can expect 80MBytes/sec on transfers
going to a board and about 10-12MBytes/sec
comming from a board.

These numbers vary.

check out the work of Laurent Moll and Mark Shand
ftp://ftp.digital.com/pub/DEC/SRC/publications/shand/fccm97.pdf
It is one of the best papers on PCI performance out there.


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 16992
Subject: Re: UART Design
From: APS <resp@associatedpro.com>
Date: Tue, 22 Jun 1999 16:37:28 -0400
Links: << >>  << T >>  << A >>
There is a freeware example of a UART done by Ben Cohen. A link is
available from our latest newsletter.

See: http://www.associatedpro.com

Dan Oomkes wrote:

> I am looking for a simple UART design (without all of the handshaking
> features) in verilog for use in a Xilinx XCS20 device.  Does anybody
> know where I could download a  free design?

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 16993
Subject: Re: FPGA board for ISA bus wanted
From: APS <resp@associatedpro.com>
Date: Tue, 22 Jun 1999 16:43:53 -0400
Links: << >>  << T >>  << A >>
APS has 2 solutions that will work. The APS X208 has an interface FPGA with
very comprehensive software which totally tests and debugs design for you.
The software is available on line at our website.

The second solution is the APS-X240 PC104 card which has a full 16 bit
DMA/INT capability. The board can be purchased with an ISA carrier board
and can be stacked to get more FPGA horse power.

Both boards can be seen at http://www.associatedpro.com



Rickman wrote:

> I need to test a design that will interface directly to the PC ISA bus
> via an FPGA. I am looking for an off the shelf board that connects all
> of the ISA bus signals to the FPGA, or at least the subset needed for a
> standard IO card. Does anyone know of such a board?
>
> There were a number of posts on this recently, but most of them have
> expired from my server.
>
> I believe there were a few posts listing lists of FPGA boards. Can
> anyone repost them?
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 16994
Subject: Re: Altera/Synplicity TIMESTAMP?
From: "Jeff Kiser" <jkiser@best.com>
Date: Tue, 22 Jun 1999 13:44:21 -0700
Links: << >>  << T >>  << A >>
I have had this problem in the past.  The error seems to be totally
independent of the timestamp in the edif file itself.  A common reason for
this seems to be when you synthesize the edif on a different machine with a
date out of sync with the one you are running Maxplus2 on (or anything that
could make the timestamp appear to be in the future).  Nonetheless, if you
touch the edif file on the machine where you are running Maxplus2, that
should fix your problem.

Jeff





Article: 16995
Subject: Re: Simple PCI card prototyping.
From: APS <resp@associatedpro.com>
Date: Tue, 22 Jun 1999 16:48:39 -0400
Links: << >>  << T >>  << A >>
APS will soon release a PCI version of its X208 board. The PCI target chip
uses our own VHDL based target design in a spartan FPGA. The TEST FPGA is a
different FPGA (a socketed 208 pin QFP). The board has 128K SRAM, a Direct
Digital Sythesizer clock option, and comes with examples and a comprehensive
WIN NT/95/98 drivers. Not up on the website yet, but should be within the
month.

Steven Casselman wrote:

> Pete Zaitcev wrote:
>
> > >: Does PCI always need lots of interfacing, or, since I'm doing
> > >: simple, low-speed I/O is there a sort of 'PCI-lite' interface
> > >: specification for that sort of thing?
> >
> > Perhaps it's a dumb idea but what about a small FPGA (Xylinx Spartan)
> > with PCI Slave code? Helpful folks in comp.arch.fpga suggested me
> > several possible ways to obtain nearly free cores. Please check
> > with the Deajanews.
> >
> > When I asked them my application was different - I needed some space
> > in the FPGA, so that ISA bus is completely enclosed inside the chip,
> > and only demultiplexed signals go in and out. Still, if you have board
> > space I think if may be feasible to have a homemade PCI-to-ISA bridge,
> > slave only.
> >
> > --Pete
>
> Check out our page for the HOT2. It is $695 and
> you'll have to buy $100 programming package from
> Xilinx.
> http://www.vcc.com/Hotii.html
> picture
> http://www.vcc.com/photohtwk4.html
> This board of course is a reconfigurable computer with
> 128K of configuration cache (will store 3 chips in cache)
> Comes with a nice little API to talk to the board and reconfigure
> it at run time.
>
> Thanks
> --
> Steve Casselman, President
> Virtual Computer Corporation
> http://www.vcc.com

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 16996
Subject: Re: PLL for FPGA
From: APS <resp@associatedpro.com>
Date: Tue, 22 Jun 1999 16:50:09 -0400
Links: << >>  << T >>  << A >>
We are beginning a core design for an FPGA PLL design. Perhaps we could
help you out at the same time. Call me and let me know your
requirements.

DEEPAK KUMAR T wrote:

> Hi
>
> can anyone tell me how to design a
> Digital PLL for FPGA
> in verilog or VHDL.
>
> regards
> deeps
>
> --
> ****************************
> if hope has flown away
> In a night, or in a day,
> In a vision, or in none,
> Is it therefore the less gone?
> All that we see or seem
> Is but a dream within a dream.
> *****************************

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 16997
Subject: Re: combining multiple xilinx designs into one
From: Allen Middleton <allen@network.com>
Date: Tue, 22 Jun 1999 15:53:15 -0500
Links: << >>  << T >>  << A >>
Give up, get into the '90's, rewrite it in an HDL:-)

Actually, can't you just link the 3 .xnf files together?

-Allen Middleton
Storagtek (formerly known as Network Systems...)

Dan Kuechle wrote:

> I want to combine 3 xilinx designs (4005xl's) into a single 4013xl part.
> The 3 designs are all done in foundation schematic entry, and are "flat".
> Each design is about 5 pages of schematics.
> Can I do a hierarchial schematic for this large design by creating a macro
> for each of the 3 small designs and then connecting them all togeather on
> a top level schematic?  This would require creating a macro for each
> of the small designs from its multi-page schematic.  I have been able to
> create a macro from "the current schematic page", but have not been able
> to create a macro from a multi-page schematic (or add a schematic page
> to a macro).  Can someone help?
>
> Thanks
>    Dan

--
Allen C. Middleton
STK/Network Systems Group        allen@network.com
7600 Boone Ave MS-020               612-391-1163
Brooklyn Park, MN 55428       FAX:  612-391-1095



Article: 16998
Subject: QPSK Constellation Permutations Article in SIGTEK SOftware Radio
From: SIGTEK <rick@sigtek.com>
Date: Tue, 22 Jun 1999 17:04:24 -0400
Links: << >>  << T >>  << A >>
**************************************
* Software Radio Newsletter Released *
**************************************

Sigtek has released its Q2 Software Radio Newsletter.
The Newsletter is jam packed full of technical information,
including an article on QPSK Constellation Permutations.
Other topics include the following Tech Brief Releases:

  ST-102 Quarterly Tech Brief: Sliding Correlator Operation
  ST-105 Quarterly Tech Brief: Using Manual Gain Control
  ST-106 Quarterly Tech Brief: Data Overflow
  ST-108 Quarterly Tech Brief: Control Software Update
  ST-111 Quarterly Tech Brief: Burst Mode Operation
  ST-112 Quarterly Tech Brief: Control Software Update
  ST-114 Quarterly Tech Brief: Writing Code
  ST-130 Quarterly Tech Brief: Wideband Tuner
  ST-132 Quarterly Tech Brief: Bit Error Rate Testing
  ST-140 Quarterly Tech Brief: Software Radio Module
  ST-140 Quarterly Tech Brief: CDMA IS-95 Soft Core
  ST-212 Quarterly Tech Brief: Digital Demodulator System
  ST-515 Quarterly Tech Brief: Bulk Processing Features



The On-Line newsletter can be viewed at:


http://www.sigtek.com/newsletter/nlq299/sigteknlq299.html


All future newsletter releases will be through the LISTBOT
automated Newsletter server.


*****    YOU MUST SUBSCRIBE USING THE LISTBOT       *****
*****  if you wish to remain on the newsletter!!!   *****


The LISTBOT button is located on the left side of our homepage


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The LISTBOT button can also be accessed at the bottom of the newsletter.



Article: 16999
Subject: Re: combining multiple xilinx designs into one
From: Ray Andraka <randraka@ids.net>
Date: Tue, 22 Jun 1999 20:00:46 -0400
Links: << >>  << T >>  << A >>
One of the weaknesses of the foundation schematic capture is its poor handling
of hierarchy.  In viewlogic, you can easily encapsulate a design as a macro to
be used in a larger design.  As you've found out, it doesn't work very well in
foundation, although I thought it was fixed in the latest version (hearsay, I
haven't tried it).   Break each page into a macro with a symbol then create a
one page top level for each of the former devices.  Make each of those into a
macro and instantiate them in your new top level.

Allen Middleton wrote:

> Give up, get into the '90's, rewrite it in an HDL:-)
>
> Actually, can't you just link the 3 .xnf files together?
>
> -Allen Middleton
> Storagtek (formerly known as Network Systems...)
>
> Dan Kuechle wrote:
>
> > I want to combine 3 xilinx designs (4005xl's) into a single 4013xl part.
> > The 3 designs are all done in foundation schematic entry, and are "flat".
> > Each design is about 5 pages of schematics.
> > Can I do a hierarchial schematic for this large design by creating a macro
> > for each of the 3 small designs and then connecting them all togeather on
> > a top level schematic?  This would require creating a macro for each
> > of the small designs from its multi-page schematic.  I have been able to
> > create a macro from "the current schematic page", but have not been able
> > to create a macro from a multi-page schematic (or add a schematic page
> > to a macro).  Can someone help?
> >
> > Thanks
> >    Dan
>
> --
> Allen C. Middleton
> STK/Network Systems Group        allen@network.com
> 7600 Boone Ave MS-020               612-391-1163
> Brooklyn Park, MN 55428       FAX:  612-391-1095



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




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