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Messages from 59250

Article: 59250
Subject: Re: Nios Clock Frequency
From: "Kenneth Land" <kland1@neuralog1.com>
Date: Wed, 13 Aug 2003 06:17:15 -0500
Links: << >>  << T >>  << A >>
Hi Ben,

I'm new to the processor on FPGA world (been using Coldfire) and was only
lightly involved with the FPGA stuff on our previous designs.  (added a few
features and fixed a few bugs in an Altera 7000MAX)

Anyway, my question concerns your statement about "in the rest of the FPGA".
My understanding is/was that FPGA logic that is not specifically tied to
together in the FPGA runs independently.  For example I assume that I can
have two (or more) Nios processors running completely independently on the
same FPGA with little effect unless I choose to tie their logic together.

I appreciate your comments.

Ken

"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> wrote in message
news:xId_a.329146$nU.16149266@amsnews03.chello.com...
> Hi Ken,
>
> > We're about to start a Nios on Cyclone project and I'm expecting to get
at
> > least 50MHz operation.  Now I'm really curious!
> >
> > I'm troubled that Altera posts little or no performance information on
> Nios
> > whereas Xilinx posts 85MHz (Spartan3) and even gives benchmark scores
for
> > its MicroBlaze offering.
>
> It's fairly easy to reach 50MHz with a NIOS core on a Cyclone. The
standard
> 32-bit design, which is pretty dressed-up, easily meets this requirement.
> I've had fairly minimal systems run way over 75MHz (actually, 98MHz) on an
> EP1C6T144C7 (medium speed grade). Of course, if you have a big
nonpipelined
> multiplier or some other long combinatorial path in the rest of the FPGA,
> this is going to affect ytour clock speed as well.
>
> Best regards,
>
>
>
> Ben
>
>



Article: 59251
Subject: Re: Error please Help
From: "Jim Wu" <jimwu88NOOOOSPAM@yahoo.com>
Date: Wed, 13 Aug 2003 11:17:39 GMT
Links: << >>  << T >>  << A >>
If you're using ModelSim, you can change the iteration limit from the
Simuluation Options window. You can also change it in modelsim.ini file.

Jim Wu
jimwu88NOOOSPAM@yahoo.com


"Isaac" <fpga_uk@yahoo.co.uk> wrote in message
news:889eb3fb.0308130255.73ef0eda@posting.google.com...
> Hi Mates I am getting following errors when I start simulating my
> design.
>
> Delta count overflow - stopped. Try to increase the iterations limit
> in simulator preferences.
> # Fatal error occurred during simulation.
>
>
> How to remove this error ?
>
> Thanking you in advance .
>
> Isaac



Article: 59252
Subject: Performance of STAPL player on embedded systems
From: Rienk van der Scheer <R.van.der.Scheer@no.3t.spam.nl>
Date: Wed, 13 Aug 2003 13:28:52 +0200
Links: << >>  << T >>  << A >>
I there anyone who implemented Altera's STAPL bytecode player on an 
embedded system (say 16-bit microcontroller) to program large FPGAs and 
PROMs?

It seems that especially the bitshift operations are programmed very 
ineffiently, resulting in a performance worse than needed.
The .jbc files generated by Quartus 3 are reasonable efficient for FPGAs 
because they only execute a single DRSCAN operation. But the .jbc files 
generated for programming enhanced EPC devices seem to be terrible: many 
separate DRSCAN operations and bitshifts. Programming an EPC4 from a PC 
is done in less than 2 minutes, but programming it with our Coldfire 
5272 takes about 10 minutes.
Anyone with the same or other experiences?

Regards,

Rienk


Article: 59253
Subject: Re: Size does matter
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Wed, 13 Aug 2003 11:29:14 GMT
Links: << >>  << T >>  << A >>
> If a 50K gate FPGA (1,536 logic cells in the XC3S for example) could be
> put in a 48 pin TQFP, and include Flash on die, then that would be a
> great product!  I know that the chip designers would have a hard time
> figuring out how to do this, but it would be a CPLD killer!  I have

What I'm missing (besides a Flash) is memory! All this SOPC talk forgets
that for a decent CPU you need external memory. I don't need additional
single cycle, synchchronous, fast memory. Keep the block rams and add a
'slow' 128 kB block (perhaps only 8 bit port is ok) with let's say 30 ns
access time. This would also help for large FIFOs.
A summery for a 'dream' SOPC FPGA:

    3000 - 5000 LCs
    5 kByte block ram
    128 kB 'slow' async ram
    512 kB flash (for configuration AND user data)
    48 - 100 pin TQFP (with pad distance > 0.5mm => cheaper production)
    price below EP1C6 :-)

That would be REALLY cool

my 2c
Martin

----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/






Article: 59254
Subject: Re: Nios Clock Frequency
From: "Kenneth Land" <kland1@neuralog1.com>
Date: Wed, 13 Aug 2003 06:31:47 -0500
Links: << >>  << T >>  << A >>
Hi Jesse,

Thank you for your valuable info. I'm looking forward to tweaking my Nios to
the max.  The ability to add custom logic and instructions to achieve
desired performance is a major draw for us.

Are there any other forums that may be more Nios specific?  I could imagine
Nios and SOPC builder generating a lot of traffic on their own.

Ken



Article: 59255
Subject: Xilinx Platform flash prom price
From: atif@kics.edu.pk (Atif)
Date: 13 Aug 2003 05:50:09 -0700
Links: << >>  << T >>  << A >>
Can anyone please tell me what is the price of Xilinx platform Flash
PROM XCf01s? Is this available?
From where can I see its price and purchase it?

Regards
Atif

Article: 59256
Subject: Re: Error please Help
From: "Ian Poole" <ian.poole@doulos.com>
Date: Wed, 13 Aug 2003 14:35:50 +0100
Links: << >>  << T >>  << A >>
This is usually caused by an error in the original VHDL that results in an
infinite loop which consumes zero simulation time. Raising the maximum delta
limit is fairly pointless, since you probably have an infinite loop...

The usual error is a process with neither a sensitivity list nor a wait
statement eg:
process
begin
  if (Reset = '1') then
    sig <= '0';
  elsif (Rising_edge(Clk)) then
    sig <= D;
  end if;
end process;

Processes with feedback can cause errors. Try this concurrent statement and
see what happens!:
sig <= not sig;

Alternatively, you may have a process with wait statments inside a while
loop/if statement etc that means the wait is bypassed for some reason eg:

process
begin
  if (Ready = '1') then
    -- do something
    wait for 10 ns;
  end if;
end process;

What happens to this process if Ready /= '1' ???

Also test bench processes which are supposed to run only once and terminate,
but have a missing wait; at the end. This particular example won't give a
delta limit error, but illustrates what I mean:
stim:process
begin
  A <= "000";
  wait for 10 ns;
  A <= "010";
  wait for 10 ns;
  A <= "100";
  -- wait; -- this effectively stops this process
end process;

HTH

Ian


"Isaac" <fpga_uk@yahoo.co.uk> wrote in message
news:889eb3fb.0308130255.73ef0eda@posting.google.com...
> Hi Mates I am getting following errors when I start simulating my
> design.
>
> Delta count overflow - stopped. Try to increase the iterations limit
> in simulator preferences.
> # Fatal error occurred during simulation.
>
>
> How to remove this error ?
>
> Thanking you in advance .
>
> Isaac



Article: 59257
Subject: Re: Datasheet for National PAL20L10
From: "Valeria Dal Monte" <aaa@bbb.it>
Date: Wed, 13 Aug 2003 13:41:13 GMT
Links: << >>  << T >>  << A >>

"Colin Jackson" <jacksoncolin@yahoo.com> ha scritto nel messaggio
news:f_ydnYyhuIk3qaSiXTWJgA@comcast.com...
> Anyone have a datasheet for a National PAL20L10?

At www.freetradezone.com there is the AMD PAL20L10 data sheet
for free. The National version is available for the subscribers only.



Article: 59258
Subject: Re: Error please Help
From: "Egbert Molenkamp" <molenkam_remove_spam@cs.utwente.nl>
Date: Wed, 13 Aug 2003 15:58:20 +0200
Links: << >>  << T >>  << A >>
The given process will never stop executing but it will NOT generate the
delta count overflow.
(In the example the tool probably raised a warning missing wait statement
during compilation/analyzing).

A simple example that generates delta count is the following CONCURRENT
statement:
y <= NOT y;

In general increasing the upper limit of the delta count will not help.
Check the
VHDL description. If you can not find the 'loop' it maybe possible to
perform a
step by step simulation (in combination with a break), depending on your
simulation environment.

Egbert Molenkamp

>
> The usual error is a process with neither a sensitivity list nor a wait
> statement eg:
> process
> begin
>   if (Reset = '1') then
>     sig <= '0';
>   elsif (Rising_edge(Clk)) then
>     sig <= D;
>   end if;
> end process;
>




Article: 59259
Subject: Re: Datasheet for National PAL20L10
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 13 Aug 2003 14:02:48 +0000 (UTC)
Links: << >>  << T >>  << A >>
Valeria Dal Monte <aaa@bbb.it> wrote:

: "Colin Jackson" <jacksoncolin@yahoo.com> ha scritto nel messaggio
: news:f_ydnYyhuIk3qaSiXTWJgA@comcast.com...
:> Anyone have a datasheet for a National PAL20L10?

: At www.freetradezone.com there is the AMD PAL20L10 data sheet
: for free. The National version is available for the subscribers only.

Are you sure? I would guess that National has the datasheet for free...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 59260
Subject: Re: Xilinx Platform flash prom price
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 13 Aug 2003 14:05:46 +0000 (UTC)
Links: << >>  << T >>  << A >>
Atif <atif@kics.edu.pk> wrote:
: Can anyone please tell me what is the price of Xilinx platform Flash
: PROM XCf01s? Is this available?
: From where can I see its price and purchase it?

Enter "XCF" as search string at
"http://www.avnetmarshall.com/dynamic/search" or   www.nuhorizons.com.

I guess the XCF parts are only avaiable to selcted customers as engineering
samples. 

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 59261
Subject: Re: Error please Help
From: "Jim Wu" <jimwu88NOOOOSPAM@yahoo.com>
Date: Wed, 13 Aug 2003 14:22:25 GMT
Links: << >>  << T >>  << A >>

> This is usually caused by an error in the original VHDL that results in an
> infinite loop which consumes zero simulation time. Raising the maximum
delta
> limit is fairly pointless, since you probably have an infinite loop...

For Modelsim, even a not very big loop would cause the problem as the
default limit is 5000.

Jim Wu
jimwu88NOOOSPAM@yahoo.com



Article: 59262
Subject: Re: Datasheet for National PAL20L10
From: "Colin Jackson" <jacksoncolin@fake_yahoo.com>
Date: Wed, 13 Aug 2003 10:30:42 -0400
Links: << >>  << T >>  << A >>
Thanks, I had never heard of them.
Looks like a great service.

I emailed National directly without a responce.
A guess their too big for their customers!
If I operated like them I'd be on welfare.



"Valeria Dal Monte" <aaa@bbb.it> wrote in message
news:Zdr_a.241160$lK4.7357861@twister1.libero.it...
>
> "Colin Jackson"  ha scritto nel messaggio
> news:f_ydnYyhuIk3qaSiXTWJgA@comcast.com...
> > Anyone have a datasheet for a National PAL20L10?
>
> At www.freetradezone.com there is the AMD PAL20L10 data sheet
> for free. The National version is available for the subscribers only.
>
>



Article: 59263
Subject: Actel Core PCI
From: sarahshen2003@yahoo.ca (sarah)
Date: 13 Aug 2003 08:17:54 -0700
Links: << >>  << T >>  << A >>
Hi,

I have a problem when implementing PCI in Acte;l APA300. Does anybody
know the  very datailed information about ACTEL cORE pci?

Thank you very much.

Sarah

Article: 59264
Subject: XILINX FPGA project
From: "Davo" <dgwood@optushome.com.au>
Date: Thu, 14 Aug 2003 01:32:00 +1000
Links: << >>  << T >>  << A >>
I am required to design and demonastrate a project incorporating the XILINX
Field Programmable Gate Array Board already assembled by Digilent Inc.  The
circuit will require some extra components other than the XILINK chip but as
our knowledge is not in the advanced stages of PLA's yet, the project will
not need to be overly complex. Any ideas, pointers or common industry
practice for implementing the use of a FPGA to utilize and demonstrate its
benefits would be welcomed - just a point in the right direction.....

Regards

Dave



Article: 59265
Subject: Re: Can i trace client activity?
From: "Jack Seredyniecki" <jack_seredyniecki@hotmail.com>
Date: Wed, 13 Aug 2003 12:39:38 -0400
Links: << >>  << T >>  << A >>
In this case you want to look at the SMTP log.  If you see messages being
sent from your server to a domain (or IP range) that's not on your "allowed
relay" list then your server is an open relay.  You should change that
PRONTO!

"Sid" <sidbites@hotmail.com> wrote in message
news:OqUYZhWYDHA.2200@TK2MSFTNGP09.phx.gbl...
> It seems that it does not log activity wich uses Excheng server as relay.
>
> "Mark Fugatt [MVP]" <news@4mcts.com> kirjoitti viestissä
> news:%23SP49YWYDHA.1580@tk2msftngp13.phx.gbl...
> > You can enable logging on the Virtual Servers and then review the log
> files
> > generated.
> >
> > -- 
> > Mark Fugatt
> > Microsoft Exchange MVP
> > www.exchangetrainer.com
> > www.msexchange.org
> >
> > "Sid" <sidbites@hotmail.com> wrote in message
> > news:%23p1vGSWYDHA.888@TK2MSFTNGP10.phx.gbl...
> > > how i can trace computers wich use IMAP/SMTP/POP3/HTTP protocols on to
> > > Exchange 2000 server.
> > >
> > >
> > >
> >
> >
>
>



Article: 59266
Subject: Re: Upgrading OS or WebPack
From: Stephen Williams <spamtrap@icarus.com>
Date: Wed, 13 Aug 2003 09:51:24 -0700
Links: << >>  << T >>  << A >>
David Brown wrote:
> "Steve Lass" <lass@xilinx.com> wrote in message
> news:3F39816B.2060200@xilinx.com...
> 
>>rickman wrote:
>>
>>>Correct me if I am wrong, but this is not Linux exactly.  It is Redhat
>>>and only one specific version of Redhat if I am not mistaken.
>>>
>>
>>Redhat 7.3 and 8.0 will be officially supported.
>>
> 
> 
> Exactly - it will not officially support Linux, but only two particular
> versions of one distribution.

So they will just freak when I run it on SuSE Linux/AMD64:-)


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


Article: 59267
Subject: Re: Quartus II and fixing hold timing
From: vbetz@altera.com (Vaughn Betz)
Date: 13 Aug 2003 10:13:49 -0700
Links: << >>  << T >>  << A >>
kjaram_junk@cox.net (Ken Jaramillo) wrote in message news:<75cebfa6.0308071755.37541a3@posting.google.com>...
> I'm using Quartus II version 3.0 and am having trouble meeting setup
>  and hold timing. This is a large PCI design in the 
> Cyclone 12C device. The routing I'm getting is really bad so my
> setup time violations are pretty bad. I can fix the setup times by
> inserting 2 LCELL buffers on the PCI clock and placing the buffers
> in such a way to get a lot of clock insertion (around 8 ns). If I synthesize the 
> design without hold time fixing enabled then I can get Tsu and Tco
> to pass (just barely). I have the PCI logic back annotated (placement
> not routing). If I then synthesize while enabling hold time fixing 
> Quartus fixes most of the hold time violations but breaks the setup 
> timing even though the PCI logic is back annotated. I think Quartus
> must be pretty dumb as far as fixing hold timing. If the worst 
> case setup time is around 15 ns (8 ns clock insertion + 7 ns PCI setup
> time requirement) then those worst case paths should have no problem
> with hold times. If quartus just placed delays on the short paths
> it could fix hold timing. But I suspect that it's placing the delays
> around the pin and affecting both long and short paths.
> 
> Has anyone else seen this? Does anyone have any idea of how to fix hold
> timing while not breaking the setup paths?
> 
> Ken Jaramillo

Hi Ken,

The Optimize Hold Time algorithm in Quartus 3.0 is smart enough to
know where to add delay to fix Th without violating Tsu, if possible. 
So the behaviour you're seeing where fixing the hold violations causes
setup violations is not generally expected.

That said, there are cases where we cannot fix Th without causing
problems on Tsu.

1.  Your circuit is such that the connections to which we have to add
delay to fix a Th violation are also on another, Tsu-critical
connection.  If we add delay to resolve Th, we will violate Tsu.  The
only solution here is to re-work your circuit.

2.  A sub-case of #1 above:  the only part of a timing path to which
we could add delay to meet a Th constraint at a register, without
violating some Tsu constraint, is on the last LUT->reg connection on
the Th path.  If Quartus register packs this LUT and register together
into one logic cell, a dedicated routing connection is used to make
the connection from the LUT to the register, so we can't slow it down
by adding more routing.  The workaround to this is to set a constraint
to force the LUT & register to be kept in separate logic cells.  In
our in-house PCI core, we have to turn off register packing on two
banks of registers to allow the router the flexibility to fix the hold
time problem.  The constraint we set (in the <project.esf> file) is:

AUTO_PACKED_REGISTERS_STRATIX = OFF on low_ad_or_fb[] and
high_ad_or_fb[]

If your PCI core uses similar names / has a similar structure this may
give you an idea of what to register unpack.  Looking at whether or
not the registers at which you're having Tsu / Th problems were packed
with LUTs in the Quartus floorplan editor will also let you see what's
going on.

3.  The same as #2, but the register and LUT were packed together by
your synthesis tool.  Depending on your synthesis tool, you may be
able to tell it not to do this (but it'll be tool specific).

4.  I've never tested the optimize hold time algorithm in cases where
someone has inserted logic cells to slow down the clock (this isn't a
common technique).  It is possible Quartus is mis-estimating the delay
at the point where the algorithm kicks in, and hence Quartus thinks
it's OK on Tsu and Th, but is not.  If you send me your circuit, I can
see if this is the case, and if necessary upgrade Quartus to model
this better.

5.  You can buy Altera's PCI core.  It works with Cyclone, and there
are 32-bit and 64-bit versions.  You can try it out (instantiate,
simulate, place and route, timing analyze -- basically see that it
works) for free, but have to buy it to generate programming files. 
See the Interfaces & Peripherals category on
http://www.altera.com/products/ip/ipm-index.html

The best way for me to give you more guidance on what went wrong and
how you can fix it is for you to send a Quartus archive of your design
to me.  All such designs are treated as confidential -- we will use it
in house only as a test case to improve our software.

Regards,
Vaughn

Altera

Article: 59268
Subject: PCI on Virtex II Pro
From: tal@sangate.com (Tal Lachmann)
Date: 13 Aug 2003 10:30:20 -0700
Links: << >>  << T >>  << A >>
Hi,

 We are trying to implement the Xilinx 66/64 PCI core on a V2P-5.
Unfortunately, we just received a note from Xilinx that the -5 device
will not live up to the 66MHz requirement (despite the fact that they
had originally claimed that it _is_ on their "qualified" list).

 Does anyone have experience with this core? Has anyone managed to
implement a 66/64 PCI Master/Slave on a V2P-5 device? Any hints/input
will be highly appreciated.

 Thanks much in advance,
 Tal.

Article: 59269
Subject: PCI on Virtex II Pro (corrected)
From: tal@sangate.com (Tal Lachmann)
Date: 13 Aug 2003 10:35:02 -0700
Links: << >>  << T >>  << A >>
Sorry, I just had to add which V2P device I am referring to:

Hi,

 We are trying to implement the Xilinx 66/64 PCI core on a V2P20-5.
Unfortunately, we just received a note from Xilinx that the -5 device
will not live up to the 66MHz requirement (despite the fact that they
had originally claimed that it _is_ on their "qualified" list).

 Does anyone have experience with this core? Has anyone managed to
implement a 66/64 PCI Master/Slave on a V2P20-5 device? Any
hints/input will be highly appreciated.

 Thanks much in advance,
 Tal.

Article: 59270
Subject: Re: Cyclone's LVDS and Quartus II
From: sdatta@altera.com (Subroto Datta)
Date: 13 Aug 2003 10:38:48 -0700
Links: << >>  << T >>  << A >>
jonesky1@hotmail.com (Joona R) wrote in message news:<2f3990c3.0308111353.2d02e4fd@posting.google.com>...
> Hi!
> 
> I have wrote some VHDL and now I have tried to get some signals from
> Cyclone FPGA chip.
> But how to implement LVDS output or input for a signal with Quartus II?
> 
> I have tried these methods:
> 
> 1. Adding signal with Assign Pins-editor. I/O Standard set to lvds.
> Result:with Floorplan viewer I can see signal implemented, but it is not
> a LVDS, other side is missing (p vs n).
> 
> 2. I have produced megafunction altddio_in/out and its low and high signals
> connected to signals or pins (vectors for low's and another for high's).
> I/O Standard is set to lvds.
> Result: Quartus will give this error message:
> "Can't place pins assigned to pin location Pin_160 (IOC_X53_Y20_N1)
>  Pin test_lo[3] is assigned to pin location Pin_160 (IOC_X53_Y20_N1)
>  Pin test_hi[3](n) is assigned to pin location Pin_160 (IOC_X53_Y20_N1)"
> 
> 3. Same as in two, but I/O standard is set to 2.5V, then no error
> messages and viewing floorplan I can see signals correctly, but this
> is no lvds anymore?
> 
> 4. There is megafunction altlvds, but it is not supported by Cyclone.
> 
> 
> If someone knows how to do this correctly, I would appreciate a little help! =)
> 
> - Joona

Hi Joona,

  Without your actual design it is difficult to describe what the
exact problems are for 2 and 3. For 1 after making an LVDS assignment
to a pin, you will need to compile the design before you can see the p
and n pins in the Floorplanner.

The ALTLVDS function is applicable to device families which have an
inbuilt SERDES. Since Cyclone does not have a built in SERDES the
ALTLVDS function is not available. For examples how to roll your own
SERDES with LVDS for Cyclone see - Application Note AN:254,
"Implementing LVDS in Cyclone Devices". This Application Note provides
detailed information on the steps needed to design using LVDS and
covers placement and board guidelines also. You can access this from
http://www.altera.com/literature/lit-cyc.html
See Chapters 9 and 10.

To quickly analyze your design for I/O Placement issues, with Quartus
II 3.0 you can run Processing->Start->I/O Assignment Analysis.

- Subroto Datta
Altera Corp.

Article: 59271
Subject: Re: Xilinx DLL driving multiple off chip clocks
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Wed, 13 Aug 2003 18:22:23 GMT
Links: << >>  << T >>  << A >>
This may not address your problem, but...

Just a thought, I like using the DDR mechanism to get clocks out of the
FPGA.  I've done source-synchonous outputs on V2 up to 200MHz with great
success.  Besides, it's free, since the IOB flip-flop's involved would not
otherwise be used.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



"Ken Morrow" <junk@not_morro.co.uk> wrote in message
news:Hod_a.2853$z7.464671@wards.force9.net...
> I have the standard sort of circuit from the Xilinx App note driving an
off
> chip clock:-
>
> Main clock comes onto chip through an IBUFG to CLKIN of the DLL
>
> CLK0 from the DLL is fed off the chip through an OBUFT.
>
> The output of the OBUFT, which is on a global clock pin, is fed back in
via
> an IBUFG to form CLKFB of the DLL.
>
> This seems to work fine.
>
> Main clock to output clock delay is constrained to <5 ns and this
constraint
> is achieved.
>
>
>
> Next I wanted to have 4 off chip clock outputs, timed as close as possible
> to the first one..
>
> I buffered the CLK0 from the DLL with a BUFG before the OBUFT to try to
> ensure that there was low skew between the 4 off  chip clock outputs.
>
> The main clock to external clock delay increased to 10nS and failed the
> constraint.
> It seemed that the router had used a mixture of global and other routing
to
> get the CLK0 to the various OBUFT,
> and that the other routing was slow.
>
> I removed the BUFG and the delay then passed my <5ns constraint without
> probs, despite using non-global routing.
>
> I am puzzled? Am I overlooking something?
>
> (Target device is a Virtex II 6000)
>
> Many Thanks,
>
> Ken.
>
>
>
>
>



Article: 59272
Subject: Re: Xilinx DLL driving multiple off chip clocks
From: mrand@my-deja.com (Marc Randolph)
Date: 13 Aug 2003 11:26:35 -0700
Links: << >>  << T >>  << A >>
"Ken Morrow" <junk@not_morro.co.uk> wrote in message news:<dHo_a.2998$z7.487794@wards.force9.net>...
> "Ken Morrow" <junk@not_morro.co.uk> wrote in message
> news:Hod_a.2853$z7.464671@wards.force9.net...
> > I have the standard sort of circuit from the Xilinx App note driving an
>  off
> > chip clock:-
> >
> > Main clock comes onto chip through an IBUFG to CLKIN of the DLL
> >
> > CLK0 from the DLL is fed off the chip through an OBUFT.
> >
> > The output of the OBUFT, which is on a global clock pin, is fed back in
>  via
> > an IBUFG to form CLKFB of the DLL.
> >
> > This seems to work fine.
> >
> > Main clock to output clock delay is constrained to <5 ns and this
>  constraint
> > is achieved.
> >
> >
> >
> > Next I wanted to have 4 off chip clock outputs, timed as close as possible
> > to the first one..
> >
> > I buffered the CLK0 from the DLL with a BUFG before the OBUFT to try to
> > ensure that there was low skew between the 4 off  chip clock outputs.
> >
> > The main clock to external clock delay increased to 10nS and failed the
> > constraint.
> > It seemed that the router had used a mixture of global and other routing
>  to
> > get the CLK0 to the various OBUFT,
> > and that the other routing was slow.
> >
> > I removed the BUFG and the delay then passed my <5ns constraint without
> > probs, despite using non-global routing.
> >
> > I am puzzled? Am I overlooking something?
> >
> > (Target device is a Virtex II 6000)
> >
> > Many Thanks,
> >
> > Ken.
> >
> Thinking about it further, even if the delay was 10ns, the DLL should have
> removed it.
> I would have expected very little delay from the main clock to the output of
> the OBUFTs,
> wether or not I have the BUFG in the way.
> Seems OK without the BUFG, but not with.

Howdy Ken,

I recall discovering the same thing on a design 18 months or so ago,
although I don't remember the difference being 5 ns (between BUFG and
not)!  I believe the problem is that even though you are driving the
net with a BUFG, it gets off the global clock net immedately and uses
normal routing to get to non-CLK IO's.

This is the reason you'll hear people talking about using a DDR scheme
to generate a clock at the IOB.  Anything less than that, and you are
subject to an inexact amount of routing delay and skew.  The next best
thing to using DDR is using MAXDELAY and MAXSKEW constraints.

See http://direct.xilinx.com/xcell/xl32/xl32_53.pdf and the other app
notes that this one points to.

Good luck,

   Marc

Article: 59273
Subject: Re: Datasheet for National PAL20L10
From: "Valeria Dal Monte" <aaa@bbb.it>
Date: Wed, 13 Aug 2003 19:33:17 GMT
Links: << >>  << T >>  << A >>

"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> ha scritto nel
messaggio news:bhdge8$meu$1@news.tu-darmstadt.de...
> Valeria Dal Monte <aaa@bbb.it> wrote:
> : At www.freetradezone.com there is the AMD PAL20L10 data sheet
> : for free. The National version is available for the subscribers only.
>
> Are you sure? I would guess that National has the datasheet for free...

National is out of PLD business since many years and don't give
any assistance or documentation for their old devices. You can
find old data sheets only in indipendent archive services as
Freetradezone with subscription.




Article: 59274
Subject: FPGA/DSP Expert - business partner for innovative FFT
From: kim.seung@sbcglobal.net (Seung)
Date: 13 Aug 2003 12:36:45 -0700
Links: << >>  << T >>  << A >>
Hello

I have a patent and recently added one more on innovative FFT
algorithm and architecture.
If you're a business minded expert on FPGA with interests in DSP, this
is a great opportunity. Our FFT is 'the' optimal HW solution as
follows:

1. Minimum HW complexity: 100% HW utilization
2. Suitable for super fast pipelined FFT: only local data flow - not
based on butterfly algorithm
3. Minimum clock cycles: baseline architecture needs N clock for
N-point FFT
4. Scalable to arbitrary large FFT size
5. Multi-dimension extension: world's first 'intrinsic'
multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs)
: great for 2-D/3-D real-time medical imaging, SAR, etc.

If you're interested in building a business together based on this
innovation,
please contact me with your resume. It'll be ideal if you have
contacts for potential customers.

Any help on this matter from FPGA/DSP group members will be
appreciated.


Thanks.

Seung P. Kim, Ph.D
Silicon Computing, Inc.
Mountain View, CA



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