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Messages from 59450

Article: 59450
Subject: Legacy 4005 series and current Xilinx ISE offerings?
From: "JoeG" <JoeG@nowhere.net>
Date: Tue, 19 Aug 2003 19:03:50 GMT
Links: << >>  << T >>  << A >>
I've asked Xilinx the question about legacy support for years. We have
hundreds of XC4000 series parts fielded on MILITARY
applications.  Specifically, we literally have hundreds of these
XC4000(militarized parts) devices fielded on DDG-51 Class Destroyers - the
hub of the US Navy. We need to maintain and support these ships for another
20 yrs. However Xilinx newer tool suites ISE(neither did the Alliance) DO
NOT support these legacy devices. Only the legacy XACT series s/w supported
these parts



Xilinx and distributors have always touted the fact that their SRAM  FPGAs
extend the tail end design of the product lifecycle by  allowing upgrades to
the FIELDED products. However, we CAN'T do this  unless the current tool
offered by Xilinx supports the  older legacy devices such as the XC4000.



This is NOT acceptable, as the old tools  are not supported by Xilinx,
maintaining the old tools, old platforms(SunWorkstations) and older
operating systems may NOT be possible or feasible.



So we are STUCK with maintaining an OLD machine with OLD Xilinx XACT
software.

JoeG



Article: 59451
Subject: Re: 22V10, ABEL & Current Design Tools?
From: mikeandmax@aol.com (Mikeandmax)
Date: 19 Aug 2003 19:43:02 GMT
Links: << >>  << T >>  << A >>
Joe G from nowhere asked -


>
>Who has current design tools that will maintain legacy 22V10 design using
>ABEL? We used to use DataIO's ABEL package and Minc Synario's ABEL(before
>Xilinx swallowed them).
>
Well, apparently Xilinx allowed Lattice to that buffet - since we(Lattice) also
own the source from synario/minc........
ispLEVER3 is a free downloadable tool which includes ABEL/Schematic as well as
Synplicity and Exemplar Leonardo Spectrum, and does support 22V10 - after all,
we make them.
Visit the lattice website, 
www.latticesemi.com 
and look for downloadable s/w



Michael Thomas
LSC SFAE
New York/New Jersey
631-874-4968 fax 631-874-4977
michael.thomas@latticesemi.com
for the latest info on Lattice products - http://www.latticesemi.com
LATTICE - BRINGING THE BEST TOGETHER


Article: 59452
Subject: Re: DDFS question
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 19 Aug 2003 12:51:29 -0700
Links: << >>  << T >>  << A >>
My conclusion:
Using Virtex-II, –what else is there?  :-)  –  use a 13 MHz input clock
with arbitrary duty cycle. Quadruple the frequency in the DCM (using FS
mode) which gives neglibible jitter ( 100 ps?) and divide by 1625 to get
the 32-MHz clock that toggles a flip-flop to generate 16 kHz with about
100 ps jitter ( plus any inherent jitter coming from the rising edges of
the 13 MHz input.)
I think there is no way to do it any better or cheaper. One DCM plus 11 flip-flops.

Frugally yours
Peter Alfke
=============
Peter A

John_H wrote:
> 
> My apologies if my own continuing discussion of jitter was annoying.
> I tried to underscore that at 16kHz, the jitter from the dual modulus
> divider is pretty insignificant.
> But, to be complete....
> 
> While DDS does a good job of giving us our outputs from the MSbit, remember
> that dividers give us edges, not square waves.  The DCM approach is great -
> quadruple the frequency to 52 MHz and divide by 1625 to get the toggle
> control for an output flop.  No real jitter.  50% duty cycle.  Great.
> 
> Taking a 13 MHz clock and doubling it by using the edges will produce rising
> edges with 26 MHz timing.  Dividing by 1625 gives an event every 16 kHz.
> Now, doesn't this event want to be a clock?  If only a clock-enable is
> needed, it works great.  If jitter on the falling edge doesn't matter, but
> 50% duty cycle does, having a clock high for 812 cycles and low for 813
> works great.  If falling edge jitter and duty cycle don't matter, using the
> MSbit of the divider gives a nice 37% duty cycle square wave with no jitter
> on the rising edge.
> 
> With all the qualifications, the 13 MHz doubler isn't a slam-dunk but is a
> great solution for most requirements.
> 
> I still think the jitter is insignificant at 0.0012 unit intervals,
> peak-to-peak.
> 
> Masochistically yours,
> - John_H
> 
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3F425BDF.D28FF25E@xilinx.com...
> > I do not understand the continuing discussion about 30 or more ns of
> jitter.
> > I gave you a circuit that gets the worst-case jitter down to <10 ns, and
> > if you use the DCM frequency doubler, the jitter will be measured in
> picoseconds.
> > So what's the 30-ns masochism about?
> >
> > Peter Alfke
> > =======================
> > Peter Alfke wrote:
> > >
> > > If you really care about nanosecond jitter, here is the best solution:
> > > Double your 13 MHz input frequency and then divide the result by 1625.
> > > If you use "my" frequency doubler (TechXclusives, 6 easy pieces), you
> > > end up with the perfect frequency and a jitter equal to the duty-cycle
> > > error of the 13 MHz, probably less than 10 ns.  The whole circuit costs
> > > you a dozen flip-flops.
> > > Peter Alfke, Xilinx Applications.
> > > ========================
> > > David Lamb wrote:
> > > >
> > > > Hi everyone,
> > > > I need to generate a 16khz clock from a 13mhz input clock. I read a
> lot of
> > > > post on DDFS but I still don't understand how precise is the output
> clock.
> > > > Fout = Fclock * N / 2^k
> > > > If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
> > > > However, I read that there is jitter on the output clock up to the
> input
> > > > clock period. I thus wonder if this <complicated> clock divider would
> really
> > > > yield better result than generating a pulse at every 812/813
> (alternating)
> > > > input clock pulse. On average, this is a 16khz clock, and it jitters
> by one
> > > > input clock period. Am I missing something here?
> > > > Thanks
> > > > David

Article: 59453
Subject: Re: Parallel interface to an FPGA
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Tue, 19 Aug 2003 16:07:48 -0500
Links: << >>  << T >>  << A >>


Michael Chan wrote:

>Hi, I'm designing a board that contains a VirtexEM amongst other stuff, and
>I want to interface a PC parallel port to the FPGA so I can do some simple
>I/O from the pc to the board and vice versa (I want to use this link to
>debug hardware I program the fpga with).  I'm wondering if anyone has done
>something simmilar, and are there any issues I should be aware of?  Can the
>parallel port strobe signal strobe data into the FPGA?  Would a serial
>interface be easier for my purposes (given I would also have to implement a
>UART on the FPGA)?
>  
>
I've developed some products that use the parallel port to control them. 
 I used
the IEEE-1284 hardware handshaking protocol built into most PC's parallel
port chips.  Differing from the standard, these chips don't delay the strobe
signals from the data, so the external device has to provide delays before
clocking data.  Otherwise, the only quirky thing is that you have to reverse
the bus direction by changing a bit in  the control register, although 
it seems
that there is enough information in the I/O instructions that that could 
have
been automatic, too.  I have an address counter in the external device 
(FPGA)
so I can read or write a bunch of sequential registers at one 
instruction per
byte transferred.

Jon


Article: 59454
Subject: Re: 22V10, ABEL & Current Design Tools?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 20 Aug 2003 09:15:01 +1200
Links: << >>  << T >>  << A >>
Mikeandmax wrote:
> 
> Joe G from nowhere asked -
> 
> >
> >Who has current design tools that will maintain legacy 22V10 design using
> >ABEL? We used to use DataIO's ABEL package and Minc Synario's ABEL(before
> >Xilinx swallowed them).
> >
> Well, apparently Xilinx allowed Lattice to that buffet - since we(Lattice) also
> own the source from synario/minc........
> ispLEVER3 is a free downloadable tool which includes ABEL/Schematic as well as
> Synplicity and Exemplar Leonardo Spectrum, and does support 22V10 - after all,
> we make them.
> Visit the lattice website,
> www.latticesemi.com
> and look for downloadable s/w
> 
> Michael Thomas
> LSC SFAE

Michael,
 My understanding is the 'free' version is a 6 month demo, and  $$$ are 
needed for more than that ?
 Lattice also do not have a separate ABEL download, but instead have one
very large bundle.
 Seems there would be an opening for a smaller download, of ABEL only,
for SPLD and CPLDs (eg new 4000 family ) ?

-jg

Article: 59455
Subject: Re: Xilinx DLL driving multiple off chip clocks
From: kenm@morro.co.uk (Ken Morrow)
Date: 19 Aug 2003 14:41:35 -0700
Links: << >>  << T >>  << A >>
For anyone who might be interested the DDR method to get a clock off
chip
is shown in:-

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15194

(Might need to stitch this url back together if it has wrapped.)

Cheers,

Ken.


"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<zlv_a.903$Gb.724@newssvr25.news.prodigy.com>...
> This may not address your problem, but...
> 
> Just a thought, I like using the DDR mechanism to get clocks out of the
> FPGA.  I've done source-synchonous outputs on V2 up to 200MHz with great
> success.  Besides, it's free, since the IOB flip-flop's involved would not
> otherwise be used.
> 
> 
> -- 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
> 
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
> 
> 
> 
> "Ken Morrow" <junk@not_morro.co.uk> wrote in message
> news:Hod_a.2853$z7.464671@wards.force9.net...
> > I have the standard sort of circuit from the Xilinx App note driving an
>  off
> > chip clock:-
> >
> > Main clock comes onto chip through an IBUFG to CLKIN of the DLL
> >
> > CLK0 from the DLL is fed off the chip through an OBUFT.
> >
> > The output of the OBUFT, which is on a global clock pin, is fed back in
>  via
> > an IBUFG to form CLKFB of the DLL.
> >
> > This seems to work fine.
> >
> > Main clock to output clock delay is constrained to <5 ns and this
>  constraint
> > is achieved.
> >
> >
> >
> > Next I wanted to have 4 off chip clock outputs, timed as close as possible
> > to the first one..
> >
> > I buffered the CLK0 from the DLL with a BUFG before the OBUFT to try to
> > ensure that there was low skew between the 4 off  chip clock outputs.
> >
> > The main clock to external clock delay increased to 10nS and failed the
> > constraint.
> > It seemed that the router had used a mixture of global and other routing
>  to
> > get the CLK0 to the various OBUFT,
> > and that the other routing was slow.
> >
> > I removed the BUFG and the delay then passed my <5ns constraint without
> > probs, despite using non-global routing.
> >
> > I am puzzled? Am I overlooking something?
> >
> > (Target device is a Virtex II 6000)
> >
> > Many Thanks,
> >
> > Ken.
> >
> >
> >
> >
> >

Article: 59456
Subject: Re: Altera JTAG verification
From: gregs@altera.com (Greg Steinke)
Date: 19 Aug 2003 14:52:51 -0700
Links: << >>  << T >>  << A >>
Rajeev,

When configuring by JTAG, the devices are initialized into User mode
when they receive a special "Startup" instruction and are clocked on
TCK several times. The Jam file made by MAX+PLUS II or Quartus II for
a multiple-device JTAG chain sends the Startup instruction to all
devices in the chain at the same time (by shifting through all the
instruction registers). By doing so, all devices initialize at the
same time.

If you want to reconfigure only one device in the chain, you can do so
by using MAX+PLUS II/Quartus II to make a different Jam file that has
only one SOF file as its base. This will make a Jam file that puts the
rest of the devices into Bypass, so they will continue to operate. To
do this, you should wire the board so that each device has its own
Conf_Done pullup resistor as shown in the Configuration App Note.

On a slightly different note - 
Andrew Paule correctly points out to look for signal integrity issues
on the JTAG lines. The most important signal here is TCK. Even though
it's only a few MHz at most, it's still a clock signal and so ringing
will cause multiple clocking. SI could cause a problem on TDI or TMS,
but usually it's OK there - usually any ringing settles out by the
time TCK is issued. So take a look at the TCK as close to the FPGAs as
possible. If one of the devices is double-clocked while receiving the
configuration data, it will sense the error by the CRC circuit and
will not operate.

To the last point regarding MySupport: I have notified the appropriate
group of the issue, and they are looking into what happened there to
rectify the situation.

Sincerely, 
Greg Steinke
Altera
gregs@altera.com


rrr@ieee.org (Rajeev) wrote in message news:<c0f37b00.0308190441.702fc6d1@posting.google.com>...
> Greg,
> 
> Thank you for your thoughtful and knowledgeable reply.
> 
> Does the device enter user mode immediately after it is configured,
> or only after the entire chain is configured ?
> 
> FYI, I did post a service request at Altera's mySupport website, the
> request number is 10334600 (more general questions than a specific
> instance).  The reason I'm here is that I was not able to get my 
> questions answered, and the service request was unceremoniously 
> closed on Aug 7.
> 
> Thanks!
> -rajeev-

Article: 59457
Subject: Re: Parallel interface to an FPGA
From: Jeff Sampson <jsampson@pobox.com>
Date: Tue, 19 Aug 2003 17:08:16 -0500
Links: << >>  << T >>  << A >>
Andras Tantos wrote:
>>>Hi, I'm designing a board that contains a VirtexEM amongst other stuff,
>>
> and
> 
>>>I want to interface a PC parallel port to the FPGA so I can do some
>>
> simple
> 
>>>I/O from the pc to the board and vice versa (I want to use this link to
>>>debug hardware I program the fpga with).  I'm wondering if anyone has
>>
> done
> 
>>>something simmilar, and are there any issues I should be aware of?  Can
>>
> the
> 
>>>parallel port strobe signal strobe data into the FPGA?  Would a serial
>>>interface be easier for my purposes (given I would also have to
>>
> implement a
> 
>>>UART on the FPGA)?
>>
>>Parallel Port (ie PC Printer port) seems "easy" but to get it correct
>>is actually not so simple. and cable is heavy :)
>>
>>use FT245 ! www.ftdichip.com looks like serial port from usb side
>>ad like strobed parallel from the other side. cheaper than implementing
>>correct LPT support at the end.
>>
>>of course you can do uart in FPGA and only add level converters
>>
> 
> 
> This device looks really promising. One question though: where can I buy it
> (in low quantities) in the US? Or in Europe?
> 
> Thanks,
> Andras Tantos

This place sells them in small quantities:

http://www.saelig.com/ftdi.htm

-- 
Jeff Sampson
http://tcrobots.org/members/jsamp.htm


Article: 59458
Subject: Re: Which software from Xilinx
From: leotran@att.net (Loi Tran)
Date: Tue, 19 Aug 2003 23:00:06 GMT
Links: << >>  << T >>  << A >>
In article <3F413D76.4FD29586@xilinx.com>, Eric Crabill <eric.crabill@xilinx.com> wrote:
>
>Hi,
>
>Based on my experience teaching a Xilinx lab
>course at SJSU, I suggest you do not try to
>mix and match versions...
>
>I tell my students to go out and buy the XSE
>4.2i product, which is available from Prentice
>Hall.  This way, you can use the same thing at
>home as you are using in the lab.
>
>Eric
>

All of your students must be quite wealthy.  I can't remember a time as a 
student that I was ever able to put down ~$600 for software.  Actually, I 
don't even put down $600 now unless the software is absolutely top quality and 
necessary.  Foundation is hardly top-quality.  I've worked with it for the 
last 2 years.  I know.  It does have its moments, but they're rare.  I don't 
even want to get started on Webpack ISE.  Xilinx should stay out of the 
software business.  They design wonderful hardware.  In software, they're 
worst than u-soft.

LT

Article: 59459
Subject: Synchronous FSM
From: tatto0_2000@yahoo.com (Wong)
Date: 19 Aug 2003 16:28:57 -0700
Links: << >>  << T >>  << A >>
Hi,
  I have a FSM to incorporate with some input signals. Unfortunately,
one of input signal might toggle and back to its original state within
ONE fpga clock interval. As a consequence, FSM failed to read the
signal changes.
  So anyone of you know how to do this in synchronous state machine
rather than increase the fpga clock frequency? Thanks !!

Article: 59460
Subject: Re: Which software from Xilinx
From: user@domain.invalid
Date: Tue, 19 Aug 2003 17:41:36 -0600
Links: << >>  << T >>  << A >>
LT,

I believe Eric was referring to this:
http://vig.prenhall.com/catalog/academic/product/0,4096,0130097292,00.html
which costs  $56.70 USD through Prentice Hall.

Ryan Laity
Xilinx Applications


Loi Tran wrote:
> In article <3F413D76.4FD29586@xilinx.com>, Eric Crabill <eric.crabill@xilinx.com> wrote:
> 
>>Hi,
>>
>>Based on my experience teaching a Xilinx lab
>>course at SJSU, I suggest you do not try to
>>mix and match versions...
>>
>>I tell my students to go out and buy the XSE
>>4.2i product, which is available from Prentice
>>Hall.  This way, you can use the same thing at
>>home as you are using in the lab.
>>
>>Eric
>>
> 
> 
> All of your students must be quite wealthy.  I can't remember a time as a 
> student that I was ever able to put down ~$600 for software.  Actually, I 
> don't even put down $600 now unless the software is absolutely top quality and 
> necessary.  Foundation is hardly top-quality.  I've worked with it for the 
> last 2 years.  I know.  It does have its moments, but they're rare.  I don't 
> even want to get started on Webpack ISE.  Xilinx should stay out of the 
> software business.  They design wonderful hardware.  In software, they're 
> worst than u-soft.
> 
> LT


Article: 59461
Subject: Re: Which software from Xilinx
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Tue, 19 Aug 2003 16:45:54 -0700
Links: << >>  << T >>  << A >>

Hi,

The XSE 4.2i product is available for about $100.
You can find it at Amazon and many university
bookstores.  That's quite reasonable, considering
you even get a textbook on digital design from a
respectable author bundled with it.  I paid more
than that for a thermodynamics textbook (ugh...)
back in 1993 when I was a student at SJSU.

I'm sorry that you have not enjoyed your time with
the Xilinx tools as much as I have.

Eric

Loi Tran wrote:
> 
> All of your students must be quite wealthy.  I can't
> remember a time as a student that I was ever able to
> put down ~$600 for software.  Actually, I don't even
> put down $600 now unless the software is absolutely
> top quality and necessary.  Foundation is hardly
> top-quality.  I've worked with it for the last 2
> years.  I know.  It does have its moments, but
> they're rare.  I don't even want to get started
> on Webpack ISE.  Xilinx should stay out of the
> software business.  They design wonderful hardware.
> In software, they're worst than u-soft.
> 
> LT

Article: 59462
Subject: Re: DDFS question
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Wed, 20 Aug 2003 10:18:34 +1000
Links: << >>  << T >>  << A >>
John_H wrote:
> "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
> message news:3f416e93@dnews.tpgi.com.au...
> <snip>
> 
>>The jitter generated by this particular divider is actually 38ns, which
>>is *half* of one period of the input clock.  77ns (one period) is the
>>upper limit for an arbitrary frequency division, but often the jitter is
>>much less.
> 
> </snip>
> 
> The periods are 62.462 us and 62.538 us which, when you account for
> rounding, is a 77 ns difference.
> 
> The values I'm used to are either "peak-to-peak" jitter which would
> encompass the entire 77 ns value and "rms jitter" which is a good value for
> judging random jitter when the observation times for jitter peak-to-peak
> values are too long.
> 
> Did I miss something?

Yes.

The N/N+1 prescaler divides by 812 and 813, so the periods are 62.462 us 
and 62.538 us, as you said, but the jitter (using the usual definition) 
isn't the difference in the periods.

Jitter is a measure of the displacement (of edges) from their ideal 
points in time, and (this will be evident if you simulate it) the 
difference in this case is 38ns p-p.

E.g.
Edge	Ideal	Actual	Difference
0	0	0	0
1	62.5us	62.46us	-38.5ns
2	125us	125us	0
3	187.5us	187.46	-38.5ns
5	250us	250us	0
...

You seem to be thinking of "cycle to cycle jitter," which is indeed 77ns 
p-p in this case.

Regards,
Allan.


Article: 59463
Subject: Re: DDFS question
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Wed, 20 Aug 2003 10:38:06 +1000
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> I do not understand the continuing discussion about 30 or more ns of jitter.
> I gave you a circuit that gets the worst-case jitter down to <10 ns, and
> if you use the DCM frequency doubler, the jitter will be measured in picoseconds.
> So what's the 30-ns masochism about?

Often it's important to not create additional clock domains in a design. 
  I'm sure you're aware that single clock domain designs are much easier 
to develop.

Or perhaps the 16kHz signal is getting sampled by the 13MHz clock 
anyway, which means that 38ns of jitter is unavoidable regardless of 
whether a DCM was used, in which case it's cheaper (less FPGA area, less 
power, etc.) just to generate the signal digitally.

Whether any of these things matter depends on the OP's application, 
about which (as usual) we know nothing.

Regards,
Allan.

> Peter Alfke
> =======================
> Peter Alfke wrote:
> 
>>If you really care about nanosecond jitter, here is the best solution:
>>Double your 13 MHz input frequency and then divide the result by 1625.
>>If you use "my" frequency doubler (TechXclusives, 6 easy pieces), you
>>end up with the perfect frequency and a jitter equal to the duty-cycle
>>error of the 13 MHz, probably less than 10 ns.  The whole circuit costs
>>you a dozen flip-flops.
>>Peter Alfke, Xilinx Applications.
>>========================
>>David Lamb wrote:
>>
>>>Hi everyone,
>>>I need to generate a 16khz clock from a 13mhz input clock. I read a lot of
>>>post on DDFS but I still don't understand how precise is the output clock.
>>>Fout = Fclock * N / 2^k
>>>If I use k= 21 bits and N=2581, I would obtain a 15.9993 khz clock.
>>>However, I read that there is jitter on the output clock up to the input
>>>clock period. I thus wonder if this <complicated> clock divider would really
>>>yield better result than generating a pulse at every 812/813 (alternating)
>>>input clock pulse. On average, this is a 16khz clock, and it jitters by one
>>>input clock period. Am I missing something here?
>>>Thanks
>>>David


Article: 59464
Subject: Xilinx FPGA pin locking/assignment
From: Jeff Sampson <jsampson@pobox.com>
Date: Tue, 19 Aug 2003 20:32:27 -0500
Links: << >>  << T >>  << A >>
I remember back when I used Xilinx XC95xx CPLDs that Xilinx was bragging about 
the pin locking capabilities of the 9500 series. And the few designs that I did 
always routed to the assignment that I gave the pins.

Do the FPGAs have that kind of success? Or do people end up have to redesign 
boards when they change the logic? (I can't imagine that.)

I have given up on the Spartan II chips for my prototyping system. I decided the 
3.3V I/O was going to be too much screwing around to interface with my other 5V 
parts. The reason is that I want to randomly assign any pin as input or output 
and have it be 5V in or out respectively. So I'll put my Spartan II chips on the 
shelf for stage 2 develepment. (ie. first PCB prototype where I can group 
outputs into 8 or 16 bit chunks and use level translator chips.)

So I'm back to either XC31xxA or XC52xx parts. I can easily get these parts and 
my software supports them. (I could probably get Spartan 1 parts if I really 
tried hard. But the ones I have found are pretty pricey.)

I want to make a board similar to my CPLD board:

http://www.infinetivity.com/~jsampson/qprot/qprot.htm

I just don't want to go to the trouble of making the board with a bunch of 
connectors and find out the PAR won't assign the bits on my connectors. My 
designs will probably be lean on logic usage so I assume that greatly improves 
my chances of successful routing.

On the CPLD I tried to group the 8-bits of the connector to the same function 
block. Is that necessary on the FPGAs? The XC3000 data sheet doesn't even seem 
to group them. They are just labled "I/O" on the pin listing.

-- 
Jeff Sampson
http://tcrobots.org/members/jsamp.htm


Article: 59465
Subject: random address
From: jaideep@sasken.com (jaideep)
Date: 19 Aug 2003 21:08:17 -0700
Links: << >>  << T >>  << A >>
Hi All,

I have a very elementary question? How do we generate a random
address( in VHDL) using a integer variable say, i from 0 to 4095(say)?
Can we read/write from/to a random address of a memory?

TIA

Jaideep

Article: 59466
Subject: Re: Which software from Xilinx
From: francoischoquette@hotmail.com (Francois Choquette)
Date: 19 Aug 2003 21:25:01 -0700
Links: << >>  << T >>  << A >>
leotran@att.net (Loi Tran) wrote in message news:<WZx0b.106221$0v4.7467848@bgtnsc04-news.ops.worldnet.att.net>...
> In article <3F413D76.4FD29586@xilinx.com>, Eric Crabill <eric.crabill@xilinx.com> wrote:
> >
> >Hi,
> >
> >Based on my experience teaching a Xilinx lab
> >course at SJSU, I suggest you do not try to
> >mix and match versions...
> >
> >I tell my students to go out and buy the XSE
> >4.2i product, which is available from Prentice
> >Hall.  This way, you can use the same thing at
> >home as you are using in the lab.
> >
> >Eric
> >
> 
> All of your students must be quite wealthy.  I can't remember a time as a 
> student that I was ever able to put down ~$600 for software.  Actually, I 
> don't even put down $600 now unless the software is absolutely top quality and 
> necessary.  Foundation is hardly top-quality.  I've worked with it for the 
> last 2 years.  I know.  It does have its moments, but they're rare.  I don't 
> even want to get started on Webpack ISE.  Xilinx should stay out of the 
> software business.  They design wonderful hardware.  In software, they're 
> worst than u-soft.
> 
> LT

Prentice-Hall sells at least two books containing a student edition of
Xilinx 4.2 software.  They're about 100 USD.  As a teaching assistant
at the university, I use "Digital Design: Principles and Practices"
from John F. Wakerly.


Francois Choquette

Article: 59467
Subject: Re: Skew on a clock tree on a virtex II : what is the good figure ?
From: "louis lin" <n2684172@ms17.hinet.net>
Date: Wed, 20 Aug 2003 13:16:56 +0800
Links: << >>  << T >>  << A >>

Thank you very much for your suggestion.
The protection and redundancy requirements of our system
exhausted all global clocks.
Is the manual routing the only solution?
Or I can add some constraint to the P&R tool?
Besides, the "timing report" means P&R report or Timing Analyzer report?


----- Original Message -----
From: "Austin Lesea" <Austin.Lesea@xilinx.com>
Newsgroups: comp.arch.fpga
Sent: Monday, August 18, 2003 10:41 PM
Subject: Re: Skew on a clock tree on a virtex II : what is the good figure ?


: Louis,
:
: You will get timing voilations in your timing report.
:
: As well, you may have to additionally manually route the clock lines to registers so that
the
: clock always gets to the ff's before the data (no warnings for this).  That is what you
lose
: when you run out of global clocks.
:
: I suggest that you re-design your circuitry to use fewer global clocks, and more clock
enables
: (which one can always do).
:
: Austin
:
: louis lin wrote:
:
: > Sometimes I can't help using non-clock net for low fan-out clock
: > because all clock nets were consumed.
: > Will the P&R tools report any warning or error
: > when it can't overcome the skew?
: > How can I realize if the skew cause any timing violation?
: >




Article: 59468
Subject: Re: Xilinx FPGA pin locking/assignment
From: antti@case2000.com (Antti Lukats)
Date: 19 Aug 2003 22:39:20 -0700
Links: << >>  << T >>  << A >>
Jeff Sampson <jsampson@pobox.com> wrote in message news:<3F42CFAB.3030501@pobox.com>...
> I remember back when I used Xilinx XC95xx CPLDs that Xilinx was bragging 
> about the pin locking capabilities of the 9500 series. And the few designs 
> Do the FPGAs have that kind of success? Or do people end up have to redesign 

forget pinlocking as a special feature. its just there, for all devices.
there are some restrictions, like global clk inputs, and for LVDS the
neg-pos pins ar paired etc etc but generically you can assign pins at
your will.

and advice for you - whatever you design today, dont look back!
so use Spartan II they are 5V tolerant as you need.

antti

Article: 59469
Subject: Re: 22V10, ABEL & Current Design Tools?
From: Andrew Paule <lsboogy@qwest.net>
Date: Wed, 20 Aug 2003 00:42:55 -0500
Links: << >>  << T >>  << A >>
Just convert your abel code to verilog - it's easy, and then you don't 
have to worry about it for a few more years.  You can do the conversion 
for a PAL (16xx,20xx, 22xx) in an hour or so. 

Andrew

JoeG wrote:

>Who has current design tools that will maintain legacy 22V10 design using
>ABEL? We used to use DataIO's ABEL package and Minc Synario's ABEL(before
>Xilinx swallowed them).
>
>Thanks in advance
>
>JoeG
>
>
>  
>


Article: 59470
Subject: IO tco timing differs between Altera Quartus II versions
From: wolfram.stumpf@diehl-avionik.de (Wolfram Stumpf)
Date: 19 Aug 2003 23:09:30 -0700
Links: << >>  << T >>  << A >>
I'm synthesising a design targeting the Altera Apex20KE
(EP20K400EFI672-2X). The design uses 2.5V IOs. While moving from
Quartus version 2.1sp1 to 2.2sp1, I realised the the tco-value for my
2.5V IOs changed.

How can this be? I'm in the loop with the Altera support for a while.
At first they denied changing anything in their library. Now they are
trying to find out which library is correct. Probably this is a secret
fix and they don't want tell the public. I really need to now, if my
design fullfils my constraining or not. If someone had the same
problem and already an answer from Altera, please share your wisdom
:-)

The example below shows the different timing for the output of the IO
register through the pad:

--------------------------------------
2.1sp1
--------------------------------------
Info: tco from clock CLK to destination pin BLM_SYNC through register
I_2642_ff_out~REGOUT is 5.449 ns
  Info: + Longest clock path from clock CLK to source register is
3.202 ns
    Info: 1: + IC(0.000 ns) + CELL(1.799 ns) = 1.799 ns; Loc. =
Pin_R6; CLK Node = 'CLK'
    Info: 2: + IC(0.775 ns) + CELL(0.628 ns) = 3.202 ns; Loc. =
IOC_L20; REG Node = 'I_2642_ff_out~REGOUT'
    Info: Total cell delay = 2.427 ns
    Info: Total interconnect delay = 0.775 ns
  Info: + Micro clock to output delay of source is 0.342 ns
  Info: + Longest register to pin delay is 1.905 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. =
IOC_L20; REG Node = 'I_2642_ff_out~REGOUT'
    Info: 2: + IC(0.000 ns) + CELL(1.905 ns) = 1.905 ns; Loc. =
Pin_L20; PIN Node = 'BLM_SYNC'
    Info: Total cell delay = 1.905 ns

--------------------------------------
2.2sp1
--------------------------------------
Info: tco from clock CLK to destination pin BLM_SYNC through register
I_2642_ff_out~REGOUT is 7.610 ns
  Info: + Longest clock path from clock CLK to source register is
3.202 ns
    Info: 1: + IC(0.000 ns) + CELL(1.799 ns) = 1.799 ns; Loc. =
Pin_R6; CLK Node = 'CLK'
    Info: 2: + IC(0.775 ns) + CELL(0.628 ns) = 3.202 ns; Loc. =
IOC_L20; REG Node = 'I_2642_ff_out~REGOUT'
    Info: Total cell delay = 2.427 ns
    Info: Total interconnect delay = 0.775 ns
  Info: + Micro clock to output delay of source is 0.342 ns
  Info: + Longest register to pin delay is 4.066 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. =
IOC_L20; REG Node = 'I_2642_ff_out~REGOUT'
    Info: 2: + IC(0.000 ns) + CELL(4.066 ns) = 4.066 ns; Loc. =
Pin_L20; PIN Node = 'BLM_SYNC'
    Info: Total cell delay = 4.066 ns


Regards

          Wolfram Stumpf

Article: 59471
Subject: Re: random address
From: Christian Schneider <cgs-news@cgschneider.com>
Date: Wed, 20 Aug 2003 08:50:39 +0200
Links: << >>  << T >>  << A >>
You can use a pseudo random generator. It does not create purely random 
data, but it generates reproduceable, random looking, data.

Pseudo random generators are built of "linear feedback shift registers" 
LFSR. This means that you build a shift register use "some" register 
outputs and xor them to create the feedback signal. Depandant on the 
number of bits you need different register outputs for the generation of 
the feedback signal.

This xilinx app note is a good explanation, and has a table, how to 
calcualate the feedback for the most common sizes:

http://www.xilinx.com/xapp/xapp052.pdf

Chris

jaideep wrote:
> Hi All,
> 
> I have a very elementary question? How do we generate a random
> address( in VHDL) using a integer variable say, i from 0 to 4095(say)?
> Can we read/write from/to a random address of a memory?
> 
> TIA
> 
> Jaideep


Article: 59472
Subject: Re: Synchronous FSM
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Wed, 20 Aug 2003 07:22:21 GMT
Links: << >>  << T >>  << A >>
Use the signal to clock a FF with D set to 1.  Use the output of this FF
with some additional logic to both re-register the pulse to your clock
domain and stretch the pulse (reset the first FF).  Now you have a wide
pulse aligned to your FSM clock.  Go from there.

The real (I mean REAL) ugly alternative is to use a bunch of
routing/combinatorial delay to stretch the pulse.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



"Wong" <tatto0_2000@yahoo.com> wrote in message
news:509bfe22.0308191528.374d2add@posting.google.com...
> Hi,
>   I have a FSM to incorporate with some input signals. Unfortunately,
> one of input signal might toggle and back to its original state within
> ONE fpga clock interval. As a consequence, FSM failed to read the
> signal changes.
>   So anyone of you know how to do this in synchronous state machine
> rather than increase the fpga clock frequency? Thanks !!



Article: 59473
Subject: Re: serial communication between pc and altera fpga
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Wed, 20 Aug 2003 09:08:50 +0100
Links: << >>  << T >>  << A >>
"Symon" <symon_brewer@hotmail.com> wrote in message
news:a28bc07f.0308190944.9b2bd98@posting.google.com...
> Hi Jonathan,
>       I thought about doing this in perl a while back but didn't get
> round to it. Sounds like Tcl could be promising, I like 'easy'!

So do I.  Just for grins, here's a tiny Tcl script that sets up the
serial port and sends a string to it.  No more than that.  But it
gives you an idea of how simple it is...

set myPort [open "com1:" w]
fconfigure $myPort -mode 19200,n,8,1
fconfigure $myPort -handshake none
puts -nonewline $myPort "Any old string"
flush $myPort
close $myPort

AND it would work correctly on both Windows and Unix,
without any change whatsoever (except for the name of the
serial port, /dev/tty or somesuch thing).

Receiving input is just a tad harder, as always, because you
never know exactly what you're going to get and when you are
going to get it.  To do a good job you need to do it
asynchronously using an event loop and "fileevent readable".
This is all standard Tcl stuff.

> Do you
> have any recommendations of where a hardware engineer could start to
> learn about Tcl? Any books you like?

Start at www.tcl.tk and download Tcl/Tk 8.4.4.  It comes with
various demos and comprehensive help.  There's also a bunch of
other links on that site, including some tutorial material.

I have a very soft spot for the splendid Tcl-for-hardware-people
course that we offer at http://www.doulos.com/frtcl.html :-)
Seriously, it's very unusual to find a course targeted at
hardware people and EDA applications...

But the book to buy is definitely Brent Welch's superb "Practical
Programming in Tcl/Tk".  Be ready to compensate the postman for
back injury - it's about 1100 pages...

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 59474
Subject: Re: Parallel interface to an FPGA
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 20 Aug 2003 09:14:26 +0100
Links: << >>  << T >>  << A >>
"Andras Tantos" <andras_tantos@tantos.yahoo.com> writes:

<about the FTDI245>

> This device looks really promising. One question though: where can I buy it
> (in low quantities) in the US? Or in Europe?

We bought ours from Alphamicro.  Very straightforward things they are
too!

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt



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