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Messages from 59375

Article: 59375
Subject: Re: serial communication between pc and altera fpga
From: "cfk" <cfk_alter_ego@pacbell.net>
Date: Sun, 17 Aug 2003 21:29:29 GMT
Links: << >>  << T >>  << A >>
Dear Sarah:
    Well, let me take a stab and see where it goes.

    If I had that problem, I would search in two directions. For the FPGA, I
would try to understand how a UART works. That would involve searches for
things like '8250', '16550' or even the venerable '1683'. I would imagine
that Verilog or VHDL, not C or C++ would be appropriate for the FPGA UART
end. I suspect that the Xilinx web site has some examples of UART code in
either hardware definition language.

    The reason you need Verilog or VHDL for the FPGA end is you are creating
flip-flops and logic that all works in parallel and the notion of C just
doesnt quite get there for hardware definition.

    On the PC end, there are a number of open-source C and C++ files
available for terminal emulators that deal with a serial port. In Linux, all
source code is available. In windows, I suspect you will find that MFC has a
terminal emulator widget that you can instantiate and go. For additional
information, I would go back and study some of Petzold's Richter's or Oney's
books if I couldnt get a grok with MFC.

   Hope this begins your quest and is what you might be looking for to
start.

Charles

p.s. Back to slugging it out with synopsys DesignWare PCI interface
documentation.
p.p.s. All capitalization or lack therof is intentional and a sign of
respect (or lack thereof)

"sarah" <sarahshen2003@yahoo.ca> wrote in message
news:d51c0c2.0308171312.59523daa@posting.google.com...
> hI,
>
> I have a project. I need to realise the serial communication between
> PC
> and Altera APEX20KE FPGA in c or c++. The function of UART in FPGA is
> working well. It can send data through uart to PC. For PC, The task is
> to receive the data from FPGA UART and give the control signal to FPGA
> through the serial port in pc. My operating system is win2000.
>
> Does anybody know how to realise it in c or c++?
>
> Thanks.
>
> Sarah



Article: 59376
Subject: Re: Skew on a clock tree on a virtex II : what is the good figure ?
From: "louis lin" <n2684172@ms17.hinet.net>
Date: Mon, 18 Aug 2003 09:24:34 +0800
Links: << >>  << T >>  << A >>


Sometimes I can't help using non-clock net for low fan-out clock
because all clock nets were consumed.
Will the P&R tools report any warning or error
when it can't overcome the skew?
How can I realize if the skew cause any timing violation?


"Austin Lesea" <Austin.Lesea@xilinx.com>  news:3F3BBF4C.F2A0F39F@xilinx.com...
: I am reminded by one of my good friends here in ICDES,
:
: That the skew (delay) of the logic signals is by design larger than the clock network, so
the software
: doesn't even have to think about skew (much).
:
: In other words, the FPGA interconnect is "correct by design."
:
: That is why it is not a good idea to use local interconnect for clocks and data.
:
: Austin
:
: Austin Lesea wrote:
:
: > JF,
: >
: > Skew can always be a problem, if you do not take it into account.  Since the software
does take
: > internal skew into account automatically, with the timing constraints properly set,
internal paths
: > of the design should have no problems with setup, or hold timing.
: >
: > External wide IO busses need to be thought out, as the software doesn't understand
constraining a
: > wide IO buss to less than X skew (nice feature, though).
: >
: > As the die gets larger, there isn't much you can do, as the speed of light in silicon
(propagation
: > of signals in the wires), combined with the RC delays, combine to make the longest lines
have the
: > delays mentioned.
: >
: > The speed of the chip has almost nothing to do with this (ie the fastest clock rate the
global
: > clock tree will toggle at).  But it is true that the faster the speed grade, the smaller
the skew
: > will be.  But the skew is dominated more by the silicon light speed (speed of the signal
in
: > silicon) and by the metal line RC, which is a small component of the speed grade.
: >
: > Austin
: >
: > jean-francois hasson wrote:
: >
: > > Hi,
: > >
: > > Considering your answer does it imply that the chip (xc2v6000-5) is
: > > not fast enough for a 450 ps skew on the clock to be a problem ?
: > >
: > > J.F. Hasson
: > >
: > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message
news:<3F3AAE78.AF5F5717@xilinx.com>...
: > > > J.F.,
: > > >
: > > > The report by the tools is correct.
: > > >
: > > > Different sized parts will have different skews (delays) in the their clock
: > > > trees due to size.
: > > >
: > > > Additionally, skew is a function of position on the tree, so from the top left
: > > > corner down to the middle of a part all the way to the bottom left corner, the
: > > > skew will be less than 130 ps for a 2V6000, wheras from the top left corner over
: > > > towards the top middle over to the right corner, it will be about 450 ps for a
: > > > 2V6000.
: > > >
: > > > Top to bottom: 130 ps.  Right to left: 450 ps.  Smallest in the middles, largest
: > > > at the corners.
: > > >
: > > > For a 2V1000, these are all less than 100 ps.
: > > >
: > > > Thus if you wanted to make the highest speed wide parallel interface, I would
: > > > use the left or right sides (least skew), rather than the top or bottom edges
: > > > (for least skew between bits).
: > > >
: > > > If I had to use the top or bottom edges, I would try to group the IOs near the
: > > > center, or near the left and right extremes.
: > > >
: > > > Again the timing reports and FPGA_Editor report the right (worst case) numbers.
: > > >
: > > > Hope this helps,
: > > >
: > > > Austin
: > > >
: > > > jean-francois hasson wrote:
: > > >
: > > > > Hi,
: > > > >
: > > > > I am working on a design involving a virtex II -5. I read in a previous post
: > > > > that the skew one could expect from a clock tree is less than 100 ps.
: > > > > However when, on the design I am developping, I run the timing analyzer I
: > > > > get a skew for some clock on a clock tree of about 450 ps or 500 ps (using
: > > > > the 5.1i F23). How should I interpret this difference ? Any clue ? Which
: > > > > figure is the right one ?
: > > > >
: > > > > J.F. Hasson
:



Article: 59377
Subject: Re: custom memory array implementaion
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Mon, 18 Aug 2003 03:23:46 GMT
Links: << >>  << T >>  << A >>
How fast is the clock?
What chip are you using?

It seems to me that you approach might be overly complex.  With a bit of
control logic you could easily enable/disable shifting in what is a 256bit x
128 stage shift register.  Depending on how you intend to read from this
(not entirely clear from your post) you might be able to use 8 SRL's x 256
to construct the array.  You can even have a 256 bit input register that
would feed (or not) the SRL array based on your control scheme.

Depending on your clock frequency you could consider using block RAM with
intelligent control.  Just as an example, if your clock (how often a 256 bit
word is available) is 1MHz, you could run the FPGA at 256MHz and use two
18Kbit SelecRAM blocks to hold the data.  You'd then have a dual port random
access solution for your problem.  For higher data rates you could configure
the DP RAM with a wider port, say 32 bits.

I think that, in general, it is more efficient to run FPGA's as fast as
they'll go and serialize a solution as opposed to creating huge wide
parallel paths that eat-up a lot of logic while running well below the
attainable clock rates on some of these devices.

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"




"Choudhary" <kiran_krishna_choudhary@yahoo.com> wrote in message
news:470b6539.0308170952.1f728ed7@posting.google.com...
> Hi Group,
>
>  This is a question related to custom memory array implementaion.
>
>  I need to implement two memory array which alternate for read and
> write according to the following:
>
>
> Writing input into Array:
> Every clock cycle a module produces a 256 bit wide data. At the end of
>  128 clock cycles, this data fills the memory array and no read takes
> places till that point. R127 has to hold the value in first clock
> cycle, Rn has to hold the value in 128-n clock cycle,R0 has to hold
> the value in 128 th clock cycle.I can use a 1 to 128 (256 bit wide)
> DeMux which select address decreases from 127 to 0.
>
> Reading: Basically two arrays alternate for read and write.
> A 128 to 1 (256 bit wide) MUX reads one of the data items in the array
> (which was written  128 clock cycles earlier) based on MUX select
> signal which is produced some where else. Reading is not in any
> particular order.
>
>
> Input           ---------------
> --/--  |DeMux| |      R0       |
>  256            --------------- 
>                 ---------------
>                |      R1       |
>                 --------------- 
>                       :
>                       :
>                 ---------------
>                |      R127     |
>                 ---------------   ---|MUX| --/--
>                                             256
>
> Now my question is :
>
> I can steer the input into array using a 128 to 1 demux (256 bit
> wide). However since I know the order in which the data goes, I don't
> necessairly need to use a demux. Every clock cycle I write into R0
> only.I will have shift bit associated with each data location except
> at R127 called 's' in the below figure. 's' in R0 is always set to 1,
> enabling that R0 can be shifted down in the next clock cycle. 's' in
> the remaining locations will be set sequentailly and will be reset at
> the end of 128 clock cycles to prevent unnecessary shifts.
>
> (In the each  clock cycle following, a new value will be written into
> R0 and the old value in R0 will be shifted to R1; and at the same time
> 's' in R0 will be shifted down from 's' in R1 so that R1 can be shited
> in the next clock cycle. Like wise in third clock cycle 's' in R2 is
> automatically set from the 's' in R1.)
>
>
> Input           ---------------
> --/------------|      R0       |[s]
>  256            ---------------
>                       |
>                 --------------- 
>                |      R1       |[s]
>                 --------------- 
>                       :
>                       :         [s]
>                       |
>                 ---------------
>                |      R127     |
>                 ---------------   ---|MUX| --/--
>                                             200
>
> The switching switching activity is now 127*(127+1)/2 [=n*(n+1)/2]=
> 127*64 ==>
> 64 times higher than the usual switching activity in the array.
>
> So is this worth  for saving some wires (127*256) and few gates in the
> form of 1 to 128 (256 bit wide)Demux ?
>
>
> Thanks for your time.
>
> Regards,
> Choudhary



Article: 59378
Subject: Re: custom memory array implementaion
From: jimwu88NOOOSPAM@yahoo.com (Jim Wu)
Date: 17 Aug 2003 21:50:22 -0700
Links: << >>  << T >>  << A >>
Why not use dual port RAMs?

Jim Wu
jimwu88NOOOSPAM@yahoo.com

kiran_krishna_choudhary@yahoo.com (Choudhary) wrote in message news:<470b6539.0308170952.1f728ed7@posting.google.com>...
> Hi Group,
> 
>  This is a question related to custom memory array implementaion.
>  
>  I need to implement two memory array which alternate for read and
> write according to the following:
>

Article: 59379
Subject: Re: Problem with Modelsim Lisence server...
From: deb_astro@yahoo.co.in (Debashish)
Date: 17 Aug 2003 23:49:28 -0700
Links: << >>  << T >>  << A >>
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3F3D0668.3080103@flukenetworks.com>...
> Debashish wrote:
> 
> > Here i have a problem with my Modelsim lisence server.I have 2
> > lisences for modelsim in my office. But many a times if someone dont
> > close the modelsim properly or dont release the lisence (by command
> > quit -sim), lisence stays active even if he is not working.So most of
> > the time i am not able to use 2 linces. So being a Windows 2000 server
> > we had to restart it again and agian atleast once everyday, two kill
> > those process and regain the 2 lisences.
> 
> 1. Learn the lmstat command to find out who is holding licenses,
>     and train them to close the gui.
> 
> 2. Learn to use command line execution: vcom -c and vsim -c.
>     vcom (command line) does not require a license. Bringing up
>     the gui with vsim.exe holds a licenses for the whole
>     session, even if you are just editing and compiling.
> 
>     Running a text testbench with vsim -c only holds the license
>     during a sim and then relinquishes it.
> 
> 
>       -- Mike Treseler


Thank you Mike i have downloaded the FLEXLM enduser guide.This solved
all my problems.I am using lmstat -a and lmremove

Article: 59380
Subject: Re: Data Structure Viewer
From: arvindk@xebeo.com (Arvind Kumar)
Date: 18 Aug 2003 02:51:31 -0700
Links: << >>  << T >>  << A >>
Good One.!! I liked it!!!

Cheers,
Arvind Kumar


"Jim Wu" <jimwu88NOOOOSPAM@yahoo.com> wrote in message news:<BnZZa.239$jw4.1@nwrdny03.gnilink.net>...
> Data Structure Viewer is a GUI based tool written in Perl and Perl-Tk. It
> allows you to convert between a data structure (e.g. IPv4 header) and
> individual fields in the data structure by simple mouse clicks. It can be
> configured to support almost any data structure definition. Please check it
> out at http://www.geocities.com/jimwu88/chips/
> 
> Please let me know about any questions or suggestions.
> Thanks,
> 
> Jim Wu
> jimwu88NOOOSPAM@yahoo.com  (remove NOOOSPAM)

Article: 59381
Subject: Re: xilinx PAR removing Logic
From: "Peter Mash" <pwtm2@cam.ac.uk>
Date: Mon, 18 Aug 2003 10:53:49 +0100
Links: << >>  << T >>  << A >>
Alison

I might be shot by some people for saying this, but I would recommend
StateCAD, free with the Xilinx WebPack (which is freely downloadable). You
can instatiate counters very easily, assign signals and other random logic,
and its visual design can be quite useful for checking over the
state-machine.  It produces Verilog and/or VHDL code optimised for your
requirements, and not just for Xilinx XST, but for Synopsis etc as well.

It has a few shortfalls, but I have just completed a major design on it, and
it is now implemented well.

Regards to all

PETE

"alison" <verilogquestion@yahoo.com> wrote in message
news:4fe9efd7.0308161449.231d65d9@posting.google.com...
> jimwu88NOOOSPAM@yahoo.com (Jim Wu) wrote in message
news:<70223a9.0308160833.140fa73d@posting.google.com>...
> > As rickman pointed out, assignments in the default state of a decoder
> > do not apply to all the states.
> >
> > Looks like you're using Verilog, so I'd suggest the following style
> > for the default assignments:
> >
> >     dataout = your_default_value;
> >
> >     case (state)
> >         STATE1:
> >         STATE2:
> >         STATE3:
> >         STATE4:
> >         STATE5: dataout = value_in_state_5;
> >         STATE6: dataout = value_in_state_6;
> >         STATE7: dataout = value_in_state_7;
> >         default: dataout = your_default_value;
> >     endcase
> >
> > This should take care of the latch inference problem.
> >
> > Jim Wu
> > jimwu88NOOOSPAM@yahoo.com
> >
> > verilogquestion@yahoo.com (alison) wrote in message
news:<4fe9efd7.0308151808.5dd21f51@posting.google.com>...
> > > Hello everyone,
> > >
> > > I have a design which has a FSM acting as a controller for an
> > > algorithm.
> > > It has 25 states but three of them are used for:
> > >
> > > state 5 --Reading data from the block ram by setting the en, rw,
> > > address signals
> > > and using a variable name data which is declared as 'reg' in the state
> > > machine
> > > to latch data out of the ram.
> > >
> > > state 6-- add a constant value to 'reg data' and set set the dataout
> > > equall to that  eg  dataout = data +5;
> > > then set en, rw and address variables so that this value gets written
> > > in ram.
> > >
> > > state7- wait a clk cycle.
> > >
> > > The variable are defined in the statemachine module as
> > >
> > > reg [15,0] data;      // its further defined as input
> > > reg [15,0] address;   // its further defined as output
> > > reg [15,0] dataout;   // its further defined as output
> > >
> > >
> > > and so on
> > >
> > > these variables are also assigned a value of zero in default state to
> > > avoid latches
> > >
> > > But only three states use them and rest do not.
> > >
> > >
> > > PROBLEM  functional simmulation is fine
> > >
> > > Place and route tool is removing the ram saying that all the above
> > > signals are sourceless. Although i can see them connected correctly
> > > after synthesis.
> > >
> > >
> > > Question; Why is data and rest of the signals becomming a latch since
> > > i have it assigned a value both in
> > > reset and default state and its being utilized in state 5 ,6 ,7.
> > >
> > >
> > >
> > >
> > >
> > > Thanks for the help
>
>
> Thanks alot guys i will give it a try.
> alison



Article: 59382
Subject: Re: Xilinx Webpack ISE and Verilog-2001?
From: "Peter Mash" <pwtm2@cam.ac.uk>
Date: Mon, 18 Aug 2003 10:56:28 +0100
Links: << >>  << T >>  << A >>
Yes, it does, and I've tried it (and it works on implementation), but other
Xilinx tools like ECS (the schematic entry) don't though - they just give
you an empty box!

Regards

PETE

"dont_reply" <anon@anon.com> wrote in message
news:%5ZYa.91$sa6.9636923@newssvr21.news.prodigy.com...
> Does Xilinx Webpack ISE support RTL-synthesis of Verilog-2001?  If so,
what
> was the first version to support it?  I'm mainly looking at support for
> 'signed' number support.
> (Signed regs, wires, inputs/outputs, and '>>>')
>
>



Article: 59383
Subject: Parallel interface to an FPGA
From: "Michael Chan" <s354025@student.uq.edu.au>
Date: Mon, 18 Aug 2003 21:05:27 +1000
Links: << >>  << T >>  << A >>
Hi, I'm designing a board that contains a VirtexEM amongst other stuff, and
I want to interface a PC parallel port to the FPGA so I can do some simple
I/O from the pc to the board and vice versa (I want to use this link to
debug hardware I program the fpga with).  I'm wondering if anyone has done
something simmilar, and are there any issues I should be aware of?  Can the
parallel port strobe signal strobe data into the FPGA?  Would a serial
interface be easier for my purposes (given I would also have to implement a
UART on the FPGA)?

Thanks.

Michael.




Article: 59384
Subject: Re: Never used FPGA board for sale
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Mon, 18 Aug 2003 11:34:00 GMT
Links: << >>  << T >>  << A >>
> Anyone wants to buy this board? (never used)
> It's a Cesys Spartan with 300,000 gates (Xilinx).
> It has a PCI bus with own PCI controller.
>
> http://www.zenhacker.com/Blog.htm
>
> frank@zenhacker.com
>
>
Is there a 'market place' to sell FPGA boards and chips. I have something
laying around on my desktop collectiong only dust :)

Martin



Article: 59385
Subject: Re: VHDL for FPGA VME Slave
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Mon, 18 Aug 2003 14:12:35 +0100
Links: << >>  << T >>  << A >>
"Colin Jackson" <jacksoncolin@fake_yahoo.com> wrote in
message news:PN6dnT-jrv5926CiU-KYgw@comcast.com...
> I'm working on a FPGA that is to have a few R/W registers on a VME bus.
>
> Anybody have some VHDL code they would like to share?
>
> If I use your ideas then your name will forever be in lights!

Be very, very afraid.

VME was defined as an *asynchronous* protocol to keep it
independent of any CPU's clock.  Consequently, any VME
interface needs to be sensitive to EDGES on several different
strobe signals (*DS0, *DS1, *AS and several others).  I think
you can do a reasonable job if you are prepared to oversample
all the strobes with a clock of about 80MHz or faster, but
a direct (asynch) implementation in FPGA would be horrible.

Once you've coped with that asynch-strobes nonsense, the main
remaining problem is performance.  Given that you're only
accessing a few registers, speed may not be a major problem.
If this is so, the rest of the task is comparatively easy -
just a matter of reading the fine print carefully, so that
you don't get confused about address modifiers, word
widths and burst transfers.

Finally, be careful about electrical specs.  VME was defined
around a particular set of LSTTL devices (74LS641-1 bidi
buffers, and a few others).  Output drivers need to be able
to sink 64mA, and be 5V-tolerant, to meet the specs.  74F543
bidi latch/buffer chips are your friends here, if you can
still get 'em.

Enjoy!
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 59386
Subject: Quartus and dcfifo
From: "Chris Saturn" <chris_saturnNOSPAM@hotmail.com>
Date: Mon, 18 Aug 2003 16:07:06 +0200
Links: << >>  << T >>  << A >>
Hi to all,



I am really new to FPGA's so I am a little confused over a lot of stuff yet.



In Quartus II, when you use the dcfifo from the Megawizard the ram can be
only internal or could be an external module?

For example if i want to use an external SRAM module to read and write data
with a Stratix?

Will the complete design be in Quartus or just the inputs and the outputs
going to the SRAM?



If not, how can I simulate if they are working together?



Thanks a lot for your time..



Chris





Article: 59387
Subject: Altera JTAG verification
From: rrr@ieee.org (Rajeev)
Date: 18 Aug 2003 07:07:39 -0700
Links: << >>  << T >>  << A >>
We have a board with approx 30 ACEX devices.  For pin count
reasons, the devices are configured via the JTAG port.  
I have built a small dumb PC peripheral that allows us to
do bit-banging of the JTAG lines with some efficiency.  At
the PC end we have ported Altera's JAM player, we build and
use text JAM files rev 2.0, we call the JAM player with the
-ACONFIGURE option.

The system works.

The problem we have is that we will sometimes get a successful
load of all devices, but one or the other device does not
function correctly.  I am speculating that perhaps a device
is correctly configured, but gets corrupted later during the
configuration cycle.  What I would like to do is use JTAG to
verify all devices, _after_ all the devices are configured.

Unfortunately, the JAM file build option in MaxPlus2 shows a 
verification option but it is grayed out.

What I'm hoping someone will be able to help me with is:

1. How hard is this ?  Are there some options somewhere that would
allow me to use existing tools to readback and verify all the 
config bits post-facto ?  Or is more engineering called for ?

2. If it's hard, where can I go to get help, paid or otherwise ?

Thanks !
-rajeev-

Article: 59388
Subject: Re: serial communication between pc and altera fpga
From: Mario Trams <Mario.Trams@informatik.tu-chemnitz.de>
Date: Mon, 18 Aug 2003 16:18:55 +0200
Links: << >>  << T >>  << A >>
sarah wrote:

> hI,
>  
> I have a project. I need to realise the serial communication between
> PC
> and Altera APEX20KE FPGA in c or c++. The function of UART in FPGA is
> working well. It can send data through uart to PC. For PC, The task is
> to receive the data from FPGA UART and give the control signal to FPGA
> through the serial port in pc. My operating system is win2000.
> 
> Does anybody know how to realise it in c or c++?

Assuming that the hardware-part is working well (what makes your
question a little bit out-of-topic), you should check some Windows
documentation how to access the serial port. 
Under Unix/Linux, for instance, you would open a so-called 
device-file that is associated with the serial port and you
would simply use read() and write() OS functions.

But for Windows I don't know how to access the serial port.
Did you try to search in Google?

Regards,
Mario  

Article: 59389
Subject: Re: serial communication between pc and altera fpga
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Mon, 18 Aug 2003 15:35:53 +0100
Links: << >>  << T >>  << A >>

"Mario Trams" <Mario.Trams@informatik.tu-chemnitz.de> wrote in message
news:bhqme4$hhm$1@anderson.hrz.tu-chemnitz.de...
> sarah wrote:
>
> > hI,
> >
> > I have a project. I need to realise the serial communication between
> > PC
> > and Altera APEX20KE FPGA in c or c++. The function of UART in FPGA is
> > working well. It can send data through uart to PC. For PC, The task is
> > to receive the data from FPGA UART and give the control signal to FPGA
> > through the serial port in pc. My operating system is win2000.
> >
> > Does anybody know how to realise it in c or c++?
>
> Assuming that the hardware-part is working well (what makes your
> question a little bit out-of-topic), you should check some Windows
> documentation how to access the serial port.
> Under Unix/Linux, for instance, you would open a so-called
> device-file that is associated with the serial port and you
> would simply use read() and write() OS functions.
>
> But for Windows I don't know how to access the serial port.

Consider using Tcl instead.  Driving Windows serial ports from
C/C++ is extremely tiresome, but Tcl makes it easy.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 59390
Subject: Re: Virtex II Output Impedance
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Mon, 18 Aug 2003 07:36:57 -0700
Links: << >>  << T >>  << A >>
Because,

We use a resistor network to provide the proper 100 ohm output impedance.

Austin

Andrew Paule wrote:

> Most On Semi, Arizona, cypress etc. ECL components use about 7 Ohms
> output impedance.  You will find that the majority of us old ECL
> designers just plop a 43 Ohm on a 50 Ohm line.  Why is it that your ECL
> outs (PECL is just a rail definition) are under this?
>
> Andrew
>
> Austin Lesea wrote:
>
> >5.6 ohms....
> >
> >Again from the terminator wizard.  Where did you get 7 ohms?  From the midpoint of
> >the IV curve (which is pretty close to the estimate from hyperlynx which looks at
> >the transistion region and averages the R).
> >
> >Austin
> >
> >Andrew Paule wrote:
> >
> >
> >
> >>Is the PECL 7 Ohms?
> >>
> >>Andrew
> >>
> >>Austin Lesea wrote:
> >>
> >>
> >>
> >>>22.6 ohms, typical corners of PVT
> >>>
> >>>This can be found by using the "terminator Wizard" in Hyperlynx, or by taking
> >>>the V/I in the IV tables directly from the ASCII IBIS model.
> >>>
> >>>Austin
> >>>
> >>>
> >>>
> >>>Jeremy Whatley wrote:
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>>Can anyone tell me what kind of output impedance I should expect to see from
> >>>>a Xilinx Virtex II XC2V1000-FF896 FPGA?  The Digitally Controlled Impedance
> >>>>feature was not used for this design.  The signals in question are LVTTL
> >>>>12mA fast slew rate (I think that's default).
> >>>>
> >>>>Thanks!
> >>>>
> >>>>Jeremy Whatley
> >>>>jeremyw@erlangtech.com
> >>>>
> >>>>
> >>>>
> >>>>
> >>>
> >>>
> >>>
> >
> >
> >


Article: 59391
Subject: Re: Skew on a clock tree on a virtex II : what is the good figure ?
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Mon, 18 Aug 2003 07:41:54 -0700
Links: << >>  << T >>  << A >>
Louis,

You will get timing voilations in your timing report.

As well, you may have to additionally manually route the clock lines to registers so that the
clock always gets to the ff's before the data (no warnings for this).  That is what you lose
when you run out of global clocks.

I suggest that you re-design your circuitry to use fewer global clocks, and more clock enables
(which one can always do).

Austin

louis lin wrote:

> Sometimes I can't help using non-clock net for low fan-out clock
> because all clock nets were consumed.
> Will the P&R tools report any warning or error
> when it can't overcome the skew?
> How can I realize if the skew cause any timing violation?
>
> "Austin Lesea" <Austin.Lesea@xilinx.com>  news:3F3BBF4C.F2A0F39F@xilinx.com...
> : I am reminded by one of my good friends here in ICDES,
> :
> : That the skew (delay) of the logic signals is by design larger than the clock network, so
> the software
> : doesn't even have to think about skew (much).
> :
> : In other words, the FPGA interconnect is "correct by design."
> :
> : That is why it is not a good idea to use local interconnect for clocks and data.
> :
> : Austin
> :
> : Austin Lesea wrote:
> :
> : > JF,
> : >
> : > Skew can always be a problem, if you do not take it into account.  Since the software
> does take
> : > internal skew into account automatically, with the timing constraints properly set,
> internal paths
> : > of the design should have no problems with setup, or hold timing.
> : >
> : > External wide IO busses need to be thought out, as the software doesn't understand
> constraining a
> : > wide IO buss to less than X skew (nice feature, though).
> : >
> : > As the die gets larger, there isn't much you can do, as the speed of light in silicon
> (propagation
> : > of signals in the wires), combined with the RC delays, combine to make the longest lines
> have the
> : > delays mentioned.
> : >
> : > The speed of the chip has almost nothing to do with this (ie the fastest clock rate the
> global
> : > clock tree will toggle at).  But it is true that the faster the speed grade, the smaller
> the skew
> : > will be.  But the skew is dominated more by the silicon light speed (speed of the signal
> in
> : > silicon) and by the metal line RC, which is a small component of the speed grade.
> : >
> : > Austin
> : >
> : > jean-francois hasson wrote:
> : >
> : > > Hi,
> : > >
> : > > Considering your answer does it imply that the chip (xc2v6000-5) is
> : > > not fast enough for a 450 ps skew on the clock to be a problem ?
> : > >
> : > > J.F. Hasson
> : > >
> : > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message
> news:<3F3AAE78.AF5F5717@xilinx.com>...
> : > > > J.F.,
> : > > >
> : > > > The report by the tools is correct.
> : > > >
> : > > > Different sized parts will have different skews (delays) in the their clock
> : > > > trees due to size.
> : > > >
> : > > > Additionally, skew is a function of position on the tree, so from the top left
> : > > > corner down to the middle of a part all the way to the bottom left corner, the
> : > > > skew will be less than 130 ps for a 2V6000, wheras from the top left corner over
> : > > > towards the top middle over to the right corner, it will be about 450 ps for a
> : > > > 2V6000.
> : > > >
> : > > > Top to bottom: 130 ps.  Right to left: 450 ps.  Smallest in the middles, largest
> : > > > at the corners.
> : > > >
> : > > > For a 2V1000, these are all less than 100 ps.
> : > > >
> : > > > Thus if you wanted to make the highest speed wide parallel interface, I would
> : > > > use the left or right sides (least skew), rather than the top or bottom edges
> : > > > (for least skew between bits).
> : > > >
> : > > > If I had to use the top or bottom edges, I would try to group the IOs near the
> : > > > center, or near the left and right extremes.
> : > > >
> : > > > Again the timing reports and FPGA_Editor report the right (worst case) numbers.
> : > > >
> : > > > Hope this helps,
> : > > >
> : > > > Austin
> : > > >
> : > > > jean-francois hasson wrote:
> : > > >
> : > > > > Hi,
> : > > > >
> : > > > > I am working on a design involving a virtex II -5. I read in a previous post
> : > > > > that the skew one could expect from a clock tree is less than 100 ps.
> : > > > > However when, on the design I am developping, I run the timing analyzer I
> : > > > > get a skew for some clock on a clock tree of about 450 ps or 500 ps (using
> : > > > > the 5.1i F23). How should I interpret this difference ? Any clue ? Which
> : > > > > figure is the right one ?
> : > > > >
> : > > > > J.F. Hasson
> :


Article: 59392
Subject: Re: serial communication between pc and altera fpga
From: sarahshen2003@yahoo.ca (sarah)
Date: 18 Aug 2003 07:46:48 -0700
Links: << >>  << T >>  << A >>
thanks.

For fpga, the uart is working.

For pc part, what is the meaning MFC? IS it microsoft? Can you tell me
the name of Petzold's Richter's or Oney's books ?

Thank you.

Sarah

"cfk" <cfk_alter_ego@pacbell.net> wrote in message news:<ZsS%a.2148$Nq2.134769898@newssvr13.news.prodigy.com>...
> Dear Sarah:
>     Well, let me take a stab and see where it goes.
> 
>     If I had that problem, I would search in two directions. For the FPGA, I
> would try to understand how a UART works. That would involve searches for
> things like '8250', '16550' or even the venerable '1683'. I would imagine
> that Verilog or VHDL, not C or C++ would be appropriate for the FPGA UART
> end. I suspect that the Xilinx web site has some examples of UART code in
> either hardware definition language.
> 
>     The reason you need Verilog or VHDL for the FPGA end is you are creating
> flip-flops and logic that all works in parallel and the notion of C just
> doesnt quite get there for hardware definition.
> 
>     On the PC end, there are a number of open-source C and C++ files
> available for terminal emulators that deal with a serial port. In Linux, all
> source code is available. In windows, I suspect you will find that MFC has a
> terminal emulator widget that you can instantiate and go. For additional
> information, I would go back and study some of Petzold's Richter's or Oney's
> books if I couldnt get a grok with MFC.
> 
>    Hope this begins your quest and is what you might be looking for to
> start.
> 
> Charles
> 
> p.s. Back to slugging it out with synopsys DesignWare PCI interface
> documentation.
> p.p.s. All capitalization or lack therof is intentional and a sign of
> respect (or lack thereof)
> 
> "sarah" <sarahshen2003@yahoo.ca> wrote in message
> news:d51c0c2.0308171312.59523daa@posting.google.com...
> > hI,
> >
> > I have a project. I need to realise the serial communication between
> > PC
> > and Altera APEX20KE FPGA in c or c++. The function of UART in FPGA is
> > working well. It can send data through uart to PC. For PC, The task is
> > to receive the data from FPGA UART and give the control signal to FPGA
> > through the serial port in pc. My operating system is win2000.
> >
> > Does anybody know how to realise it in c or c++?
> >
> > Thanks.
> >
> > Sarah

Article: 59393
Subject: Re: Never used FPGA board for sale
From: "Frank Andreas de Groot" <nospam@nospam.org>
Date: Mon, 18 Aug 2003 16:54:51 +0200
Links: << >>  << T >>  << A >>
Try here or eBay..

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:IQ20b.107844$kc5.1096824@news.chello.at...
> >
> Is there a 'market place' to sell FPGA boards and chips. I have something
> laying around on my desktop collectiong only dust :)



Article: 59394
Subject: Xilinx's library associations
From: smukthav@yahoo.com (Sandeep)
Date: 18 Aug 2003 08:29:14 -0700
Links: << >>  << T >>  << A >>
Does anyone know if there is a way to tell the Xilinx tools to
maintain library associations for symbols that are not unique. For
example is it possible to have an unsigned adder associated with
unsigned library and a signed adder associated with signed library be
represented with same entity names but with different library
associations at the top-level instantiation ? Assume that the adders
are black boxes.

Sandeep

Article: 59395
Subject: Re: Translate: Map
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 18 Aug 2003 16:06:35 GMT
Links: << >>  << T >>  << A >>
I think this is an issue of your display preferences within ISE.

The main project navigator's Edit menu item, Preferences..., Processes tab,
Property Display level, select "Advanced" from the drop-down list.

You're there!
The "Disable Register Ordering" check box is now accessible.

- John_H


"Peter Mash" <pwtm2@cam.ac.uk> wrote in message
news:bhonuf$p80$1@pegasus.csx.cam.ac.uk...
> Dear People,
>
> I have found that by adding the option "-r" to the command line of the
> Xilinx mapping tools, I can route larger designs than previously possible.
>
> Although, this is only through the command-line. Does anybody know a way
of
> doing this through the Xilinx ISE? (It is not available in the options
menu
> under map - I've already checked?)
>
>
> Regards
>
> PETE MASH
>
>



Article: 59396
Subject: Re: Never used FPGA board for sale
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Mon, 18 Aug 2003 16:27:30 GMT
Links: << >>  << T >>  << A >>
OK, I'll try it here: For sale:

    6 pcs Altera EP1K50TC144-3
    7 pcs Altera MAX7032AETC44-10
    ca. 130 pcs async RAM 128kBx8
    ca. 15 boards with ACEX 1K50 + 128 kB RAM + 512 kB Flash + MAX for
config from Flash

Martin
----- Original Message -----
From: "Frank Andreas de Groot" <nospam@nospam.org>
Newsgroups: comp.arch.fpga
Sent: Monday, August 18, 2003 4:54 PM
Subject: Re: Never used FPGA board for sale


> Try here or eBay..
>
> "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:IQ20b.107844$kc5.1096824@news.chello.at...
> > >
> > Is there a 'market place' to sell FPGA boards and chips. I have
something
> > laying around on my desktop collectiong only dust :)
>
>



Article: 59397
Subject: Re: Old Xilinx FPGAs
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 18 Aug 2003 09:34:09 -0700
Links: << >>  << T >>  << A >>
We use the English language carefully:
TOLERANT means that the pin tolerates to be driven with a specified
standard voltage, perhaps a series-resistor is needed. (Heck, with the
right resistor, we are 1000-V tolerant!)
COMPATIBLE means that we can receive and drive the proper level
directly. 

Peter Alfke, Xilinx
===============================
Jeff Sampson wrote:
> 
> E
> The inputs are 5V tolerant. But the outputs can only be driven with 3.3V (at the
> VCCO pin). Or am I wrong? If I can drive the outputs with 5V that would save
> lots of screwing around. I don't remember right of hand where I saw that. But
> I'll go back and track it down.
> 
> I did end up buying Spartan II parts.
> 
> --
> Jeff Sampson
> http://tcrobots.org/members/jsamp.htm

Article: 59398
Subject: Re: Quartus and dcfifo
From: sdatta@altera.com (Subroto Datta)
Date: 18 Aug 2003 11:25:32 -0700
Links: << >>  << T >>  << A >>
"Chris Saturn" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bhqmi9$r8k$1@sunnews.cern.ch>...
> Hi to all,
> 
> 
> 
> I am really new to FPGA's so I am a little confused over a lot of stuff yet.
> 
> 
> 
> In Quartus II, when you use the dcfifo from the Megawizard the ram can be
> only internal or could be an external module?
> 
> For example if i want to use an external SRAM module to read and write data
> with a Stratix?
> 
> Will the complete design be in Quartus or just the inputs and the outputs
> going to the SRAM?
> 
> 
> 
> If not, how can I simulate if they are working together?
> 
> 
> 
> Thanks a lot for your time..
> 
> 
> 
> Chris

Hi Chris,

  If you use the DCFIFO or for that matter any of the megawizards, the
logic will be implemented inside the FPGA. There is a single VHDL
output file (vho) or Verilog output file (vo), written out by Quartus
that you can simulate, using a VHDL/Verilog simulator like Modelsim.
If you do not want to use a VHDL/Verilog simulator you may also use
the simulator built into Quartus.

If you want to simulate an external memory, you will need to bring out
the interface pins to the external memory, as primary inputs/outputs
of the FPGA model. You will then need another simulation model for the
memory, from the memory vendor, which should be hooked up to the FPGA
model. This composite model (FPGA+external memory) can then be
simulated using a VHDL/Verilog simulator.

- Subroto Datta
Altera Corp.

Article: 59399
Subject: Re: Altera JTAG verification
From: Andrew Paule <lsboogy@qwest.net>
Date: Mon, 18 Aug 2003 13:40:14 -0500
Links: << >>  << T >>  << A >>
You should be able to read back the data and compare it one the host 
machine - I don't know if the verify has too small a buffer for this 
(was developed long ago and far away - used Max Plus in the 95 time frame).

Andrew

Rajeev wrote:

>We have a board with approx 30 ACEX devices.  For pin count
>reasons, the devices are configured via the JTAG port.  
>I have built a small dumb PC peripheral that allows us to
>do bit-banging of the JTAG lines with some efficiency.  At
>the PC end we have ported Altera's JAM player, we build and
>use text JAM files rev 2.0, we call the JAM player with the
>-ACONFIGURE option.
>
>The system works.
>
>The problem we have is that we will sometimes get a successful
>load of all devices, but one or the other device does not
>function correctly.  I am speculating that perhaps a device
>is correctly configured, but gets corrupted later during the
>configuration cycle.  What I would like to do is use JTAG to
>verify all devices, _after_ all the devices are configured.
>
>Unfortunately, the JAM file build option in MaxPlus2 shows a 
>verification option but it is grayed out.
>
>What I'm hoping someone will be able to help me with is:
>
>1. How hard is this ?  Are there some options somewhere that would
>allow me to use existing tools to readback and verify all the 
>config bits post-facto ?  Or is more engineering called for ?
>
>2. If it's hard, where can I go to get help, paid or otherwise ?
>
>Thanks !
>-rajeev-
>  
>




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