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Messages from 24900

Article: 24900
Subject: Re: Looks like Xilinx is at it again!
From: Ray Andraka <ray@andraka.com>
Date: Mon, 21 Aug 2000 21:15:02 GMT
Links: << >>  << T >>  << A >>

Ray Andraka wrote:
> 
> Ditto, except in my case the log in button always brings me back to the
> registration page. **Sigh**

(that is the log in button sends me to:
https://xapps2.xilinx.com/cgi-bin/Registration/Protected/registration.pl?ctrl_register=websupport&ctrl_user=randraka
)

I now have two different passwords too!

> 
> Greg Neff wrote:
> >
> > In article <39A15F1A.5321452@andraka.com>,
> >   Ray Andraka <ray@andraka.com> wrote:
> > > Hey folks, has anyone tried to get support from xilinx lately for
> > 3.1?  They've
> > > now got a web page you have to log into to get support.  All well and
> > good if it
> > > worked I suppose.  Thing is I've registered several times now.  For
> > registering
> > > you get an autogenerated note back saying it will take a day to grant
> > access to
> > > websupport.  THing is even after two weeks it still gives you the new
> > > registration page when you log in (frustrating part is it fills in
> > all the
> > > blanks except the registration code, so I'm already there in the data
> > base).
> > (snip)
> >
> > Well, it works for me.  I go to this page:
> >
> > http://www.xilinx.com/support/clearexpress/websupport.htm
> >
> > And hit the big 'LOG IN' button.  This does not bring me back to the
> > registration page, as you described.
> >
> > My experience has been that responses to web support questions have
> > been prompt (less than 1 business day).  I find this easier than trying
> > to work via telephone, because of our 3 hour time difference.
> >
> > --
> > Greg Neff
> > VP Engineering
> > *Microsym* Computers Inc.
> > greg@guesswhichwordgoeshere.com
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 24901
Subject: xdl documentation
From: William Chow <choww@eecg.utoronto.ca>
Date: Mon, 21 Aug 2000 21:19:14 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm looking for documentation on the Xilinx xdl file format. I've tried
looking for it off Xilinx's support page. Can't get to it. Can someone
help me out?

Thanks.

William

/* -------- William Chow : "WHO SAYS YOU CAN'T DO IT?!" -------- */ 
Email = choww@eecg.utoronto.ca   || choww@ugsparc0.eecg.utoronto.ca

Article: 24902
Subject: Re: Looks like Xilinx is at it again!
From: Anna Acevedo <acevedo@xilinx.com>
Date: Mon, 21 Aug 2000 15:16:54 -0700
Links: << >>  << T >>  << A >>

--------------08D4985EBC4D0FE29F31189C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

 Xilinx has made some changes (enhancements) to the web site as well as changing service provider.  This may have caused
some problem with the scripts that run the on line forms.
Best way to resolve this is to contact webmaster@xilinx.com



Ray Andraka wrote:

> Ray Andraka wrote:
> >
> > Ditto, except in my case the log in button always brings me back to the
> > registration page. **Sigh**
>
> (that is the log in button sends me to:
> https://xapps2.xilinx.com/cgi-bin/Registration/Protected/registration.pl?ctrl_register=websupport&ctrl_user=randraka
> )
>
> I now have two different passwords too!
>
> >
> > Greg Neff wrote:
> > >
> > > In article <39A15F1A.5321452@andraka.com>,
> > >   Ray Andraka <ray@andraka.com> wrote:
> > > > Hey folks, has anyone tried to get support from xilinx lately for
> > > 3.1?  They've
> > > > now got a web page you have to log into to get support.  All well and
> > > good if it
> > > > worked I suppose.  Thing is I've registered several times now.  For
> > > registering
> > > > you get an autogenerated note back saying it will take a day to grant
> > > access to
> > > > websupport.  THing is even after two weeks it still gives you the new
> > > > registration page when you log in (frustrating part is it fills in
> > > all the
> > > > blanks except the registration code, so I'm already there in the data
> > > base).
> > > (snip)
> > >
> > > Well, it works for me.  I go to this page:
> > >
> > > http://www.xilinx.com/support/clearexpress/websupport.htm
> > >
> > > And hit the big 'LOG IN' button.  This does not bring me back to the
> > > registration page, as you described.
> > >
> > > My experience has been that responses to web support questions have
> > > been prompt (less than 1 business day).  I find this easier than trying
> > > to work via telephone, because of our 3 hour time difference.
> > >
> > > --
> > > Greg Neff
> > > VP Engineering
> > > *Microsym* Computers Inc.
> > > greg@guesswhichwordgoeshere.com
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

--
*****************************
Anna M. Acevedo
Xilinx University Program
2100 Logic Drive
San Jose, CA 95124
PH: (408) 879-5338
FAX: (408) 879-4780

Email: anna.acevedo@xilinx.com
http://www.xilinx.com/programs/univ.htm
*****************************


--------------08D4985EBC4D0FE29F31189C
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;Xilinx has made some changes (enhancements) to the web site as well
as changing service provider.&nbsp; This may have caused some problem with
the scripts that run the on line forms.
<br>Best way to resolve this is to contact webmaster@xilinx.com
<br>&nbsp;
<br>&nbsp;
<p>Ray Andraka wrote:
<blockquote TYPE=CITE>Ray Andraka wrote:
<br>>
<br>> Ditto, except in my case the log in button always brings me back
to the
<br>> registration page. **Sigh**
<p>(that is the log in button sends me to:
<br><a href="https://xapps2.xilinx.com/cgi-bin/Registration/Protected/registration.pl?ctrl_register=websupport&ctrl_user=randraka">https://xapps2.xilinx.com/cgi-bin/Registration/Protected/registration.pl?ctrl_register=websupport&amp;ctrl_user=randraka</a>
<br>)
<p>I now have two different passwords too!
<p>>
<br>> Greg Neff wrote:
<br>> >
<br>> > In article &lt;39A15F1A.5321452@andraka.com>,
<br>> >&nbsp;&nbsp; Ray Andraka &lt;ray@andraka.com> wrote:
<br>> > > Hey folks, has anyone tried to get support from xilinx lately
for
<br>> > 3.1?&nbsp; They've
<br>> > > now got a web page you have to log into to get support.&nbsp;
All well and
<br>> > good if it
<br>> > > worked I suppose.&nbsp; Thing is I've registered several times
now.&nbsp; For
<br>> > registering
<br>> > > you get an autogenerated note back saying it will take a day
to grant
<br>> > access to
<br>> > > websupport.&nbsp; THing is even after two weeks it still gives
you the new
<br>> > > registration page when you log in (frustrating part is it fills
in
<br>> > all the
<br>> > > blanks except the registration code, so I'm already there in
the data
<br>> > base).
<br>> > (snip)
<br>> >
<br>> > Well, it works for me.&nbsp; I go to this page:
<br>> >
<br>> > <a href="http://www.xilinx.com/support/clearexpress/websupport.htm">http://www.xilinx.com/support/clearexpress/websupport.htm</a>
<br>> >
<br>> > And hit the big 'LOG IN' button.&nbsp; This does not bring me back
to the
<br>> > registration page, as you described.
<br>> >
<br>> > My experience has been that responses to web support questions
have
<br>> > been prompt (less than 1 business day).&nbsp; I find this easier
than trying
<br>> > to work via telephone, because of our 3 hour time difference.
<br>> >
<br>> > --
<br>> > Greg Neff
<br>> > VP Engineering
<br>> > *Microsym* Computers Inc.
<br>> > greg@guesswhichwordgoeshere.com
<br>> >
<br>> > Sent via Deja.com <a href="http://www.deja.com/">http://www.deja.com/</a>
<br>> > Before you buy.
<br>>
<br>> --
<br>> -Ray Andraka, P.E.
<br>> President, the Andraka Consulting Group, Inc.
<br>> 401/884-7930&nbsp;&nbsp;&nbsp;&nbsp; Fax 401/884-7950
<br>> email ray@andraka.com
<br>> <a href="http://www.andraka.com">http://www.andraka.com</a>&nbsp;
or <a href="http://www.fpga-guru.com">http://www.fpga-guru.com</a>
<p>--
<br>-Ray Andraka, P.E.
<br>President, the Andraka Consulting Group, Inc.
<br>401/884-7930&nbsp;&nbsp;&nbsp;&nbsp; Fax 401/884-7950
<br>email ray@andraka.com
<br><a href="http://www.andraka.com">http://www.andraka.com</a>&nbsp; or
<a href="http://www.fpga-guru.com">http://www.fpga-guru.com</a></blockquote>

<p>--
<br>*****************************
<br>Anna M. Acevedo
<br>Xilinx University Program
<br>2100 Logic Drive
<br>San Jose, CA 95124
<br>PH: (408) 879-5338
<br>FAX: (408) 879-4780
<p>Email: anna.acevedo@xilinx.com
<br><A HREF="http://www.xilinx.com/programs/univ.htm">http://www.xilinx.com/programs/univ.htm</A>
<br>*****************************
<br>&nbsp;</html>

--------------08D4985EBC4D0FE29F31189C--

Article: 24903
Subject: Re: Non-disclosures in job interviews, Round One
From: Darin Johnson <darin@usa.net>
Date: Mon, 21 Aug 2000 22:16:58 GMT
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes:

> I had my interview with company A this morning. It started out a little
> uneven. I entered and was presented with the application, NDA and some
> other paperwork to fill out. I was also asked to sign into the visitors
> log. However the visitor's log was like none I had ever seen before.
> Each visitor had an entire page with a three paragraph agreement to
> sign. One of the paragraphs was a brief, but broadly worded NDA. Words
> to the effect that I would not divulge any information that I obtained
> while at this facility.
> 
> I did not sign.

Of course, the issue may boil down to:  would one want to work at a
place that requires such things.  If it's a major burden just to
get in and out of an interview, would day-to-day work also involve
bureaucratic nonsense?  A lot of companies looking for good talent
don't realize that first impressions work both ways.

The person hiring should make it clear that any bureaucratic nonsense
is not reflective of the actual job itself (in a mass interview
situation though...), and try to hide a lot of it.  Get the prospects
hooked during the first interview, instead of making them nervous...

I had one interview where I actually had to sign a form, before going
in, saying I would waive my rights under a California labor law
(something about ability to sue when terminated).  Being desparate, I
did it anyway.  But I don't know if it was a sign of how the company
was going to operate in the future, or if it was a normal company that
happened to have an over-zealous lawyer.
Article: 24904
Subject: Re: Verilog multiplier in Xilinx...
From: "Austin Franklin" <austin@darkroom65.com>
Date: 21 Aug 2000 22:26:15 GMT
Links: << >>  << T >>  << A >>
Thanks for the tip, I'll check it out for the one multiplier they have.  It
claims it can do a 16x16 multiply at 59MHz...in a Virtex -6.  We'll see. 
For the 4k/Spartan, there are two additional multipliers, one optimized for
area, and one optimized for speed.

I don't do simulations with delay information, it's unnecessary.  I do
thought need an exact Verilog output model for this so I can do simulation
in VCS.

Mike Peattie <mpeattie@xilinx.com> wrote in article
<398EFD5C.C845D6FA@xilinx.com>...
> Austin,
> 
>     You can run ngdbuild on your design, which will merge all your
netlists
> together (including the coregen multiplier), then run ngd2ver to get a
verilog
> simulation file.  This simulation will not have routing delays- it's
purely
> functional.
> 
> Mike
> 
> Austin Franklin wrote:
> 
> > Torbjörn Stabo <etxstbo@kk.ericsson.se> wrote in article
> > <398A8153.6E265E32@kk.ericsson.se>...
> > > > Anyone have any Verilog code they'd be willing to share for a
'decent'
> > > > multiplier?  I am looking for something that can do a 24 x 24
> > multiply...it
> > > > can take quite a few cycles, and it's for a Virtex architecture.
> > >
> > > Have you tried Coregen? No source, but it sounds like it's the result
> > that matters to you..
> > >
> >
> > Thanks for the suggestion, I did look at it, but it doesn't appear to
have
> > a Verilog output mode.
> > If I don't get the Verilog source (or a protected model) then how do I
unit
> > delay simulate it?
> 
> 
Article: 24905
Subject: Re: Looks like Xilinx is at it again!
From: Ray Andraka <ray@andraka.com>
Date: Mon, 21 Aug 2000 23:37:08 GMT
Links: << >>  << T >>  << A >>


Anna Acevedo wrote:
> 
>  Xilinx has made some changes (enhancements) to the web site as well as
> changing service provider.  This may have caused some problem with the scripts
> that run the on line forms.

I love when they "fix" the stuff that wasn't broken.  So explain to me again why
you need password protected access to submit a technical support case?  Seems to
me if they already ask for all your info it would be relatively easy to cross
check that against a database to see that you are under maintenance if they
really felt that to be necessary.  Certainly it shouldn't become a major PITA
for the users who are in some cases already spending an inordinate amount of
time working around tools problems.


> Best way to resolve this is to contact webmaster@xilinx.com

Yep, that gets an automated response too :-)


 
> 
> Ray Andraka wrote:
> 
> > Ray Andraka wrote:
> > >
> > > Ditto, except in my case the log in button always brings me back to the
> > > registration page. **Sigh**
> >
> > (that is the log in button sends me to:
> > https://xapps2.xilinx.com/cgi-bin/Regis
> > ration/Protected/registration.pl?ctrl_register=websupport&ctrl_user=randraka
> >
> > )
> >
> > I now have two different passwords too!
> >
> > >
> > > Greg Neff wrote:
> > > >
> > > > In article <39A15F1A.5321452@andraka.com>,
> > > >   Ray Andraka <ray@andraka.com> wrote:
> > > > > Hey folks, has anyone tried to get support from xilinx lately for
> > > > 3.1?  They've
> > > > > now got a web page you have to log into to get support.  All well and
> > > > good if it
> > > > > worked I suppose.  Thing is I've registered several times now.  For
> > > > registering
> > > > > you get an autogenerated note back saying it will take a day to grant
> > > > access to
> > > > > websupport.  THing is even after two weeks it still gives you the new
> > > > > registration page when you log in (frustrating part is it fills in
> > > > all the
> > > > > blanks except the registration code, so I'm already there in the data
> > > > base).
> > > > (snip)
> > > >
> > > > Well, it works for me.  I go to this page:
> > > >
> > > > http://www.xilinx.com/support/clearexpress/websupport.htm
> > > >
> > > > And hit the big 'LOG IN' button.  This does not bring me back to the
> > > > registration page, as you described.
> > > >
> > > > My experience has been that responses to web support questions have
> > > > been prompt (less than 1 business day).  I find this easier than trying
> > > > to work via telephone, because of our 3 hour time difference.
> > > >
> > > > --
> > > > Greg Neff
> > > > VP Engineering
> > > > *Microsym* Computers Inc.
> > > > greg@guesswhichwordgoeshere.com
> > > >
> > > > Sent via Deja.com http://www.deja.com/
> > > > Before you buy.
> > >
> > > --
> > > -Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930     Fax 401/884-7950
> > > email ray@andraka.com
> > > http://www.andraka.com  or http://www.fpga-guru.com
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
> 
> --
> *****************************
> Anna M. Acevedo
> Xilinx University Program
> 2100 Logic Drive
> San Jose, CA 95124
> PH: (408) 879-5338
> FAX: (408) 879-4780
> 
> Email: anna.acevedo@xilinx.com
> http://www.xilinx.com/programs/univ.htm
> *****************************
> 

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 24906
Subject: Re: Verilog multiplier in Xilinx...
From: Ray Andraka <ray@andraka.com>
Date: Tue, 22 Aug 2000 00:05:25 GMT
Links: << >>  << T >>  << A >>
DO you need a single cycle multiply, or is pipelined OK.  If pipelined is OK, a
16x 16 properly designed will clock at about 150 MHz in a VIrtex -4 and about
195 MHz in a -6.  24 bits is good to somwhere around 134 MHz (I've done it at
134) in the -4 parts.  The design is not hard.  The COREGEN multiplier will get
close, but can be improved upon at the cost of some area if the speeds don't
meet your needs.


Austin Franklin wrote:
> 
> Thanks for the tip, I'll check it out for the one multiplier they have.  It
> claims it can do a 16x16 multiply at 59MHz...in a Virtex -6.  We'll see.
> For the 4k/Spartan, there are two additional multipliers, one optimized for
> area, and one optimized for speed.
> 
> I don't do simulations with delay information, it's unnecessary.  I do
> thought need an exact Verilog output model for this so I can do simulation
> in VCS.
> 
> Mike Peattie <mpeattie@xilinx.com> wrote in article
> <398EFD5C.C845D6FA@xilinx.com>...
> > Austin,
> >
> >     You can run ngdbuild on your design, which will merge all your
> netlists
> > together (including the coregen multiplier), then run ngd2ver to get a
> verilog
> > simulation file.  This simulation will not have routing delays- it's
> purely
> > functional.
> >
> > Mike
> >
> > Austin Franklin wrote:
> >
> > > Torbjörn Stabo <etxstbo@kk.ericsson.se> wrote in article
> > > <398A8153.6E265E32@kk.ericsson.se>...
> > > > > Anyone have any Verilog code they'd be willing to share for a
> 'decent'
> > > > > multiplier?  I am looking for something that can do a 24 x 24
> > > multiply...it
> > > > > can take quite a few cycles, and it's for a Virtex architecture.
> > > >
> > > > Have you tried Coregen? No source, but it sounds like it's the result
> > > that matters to you..
> > > >
> > >
> > > Thanks for the suggestion, I did look at it, but it doesn't appear to
> have
> > > a Verilog output mode.
> > > If I don't get the Verilog source (or a protected model) then how do I
> unit
> > > delay simulate it?
> >
> >

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 24907
Subject: Re: xdl documentation
From: Philip Freidin <philip@fliptronics.com>
Date: Mon, 21 Aug 2000 17:09:14 -0700
Links: << >>  << T >>  << A >>

Send a request to
    xdl_support@xilinx.com

On Mon, 21 Aug 2000 21:19:14 GMT, William Chow <choww@eecg.utoronto.ca> wrote:
>I'm looking for documentation on the Xilinx xdl file format. I've tried
>looking for it off Xilinx's support page. Can't get to it. Can someone
>help me out?
>William

Philip Freidin

Mindspring that acquired Earthlink that acquired Netcom has
decided to kill off all Shell accounts, including mine.

My new primary email address is    philip@fliptronics.com

I'm sure the inconvenience to you will be less than it is for me.
Article: 24908
Subject: Re: Verilog multiplier in Xilinx...
From: "Austin Franklin" <austin@darkroom65.com>
Date: 22 Aug 2000 00:30:33 GMT
Links: << >>  << T >>  << A >>
Hi Ray,

The problem with the CoreGen is I can't control what it generates...so I
can't control the speed or the area (for the Virtex, that is...at least
with 2.1i).  For the 24 bit multiplier, I just made a
shift/accumulate...and it is very very small, and takes 24 cycles (which I
have 72, so it's not a problem), and can handle the 50MHz clock no problem.

I did run the CoreGen for the 16x16 (it did a horrible job on the
24x24...), and it did a very nice job.  I got a single cycle signed 17x16
multiplier that'll run at > 50MHz in a -5!

My two requirements were so opposite...luckily!  The 24 bit multiplier
could be very slow, and as such, I could make it very small...which is
good, because the 16 bit multiplier I needed two of, and it kind of needed
to be single cycle, which usually dictates large.  I could have done it
pipelined if I wanted to change the depth of a FIFO downstream from 16 to
32...means re-doing all the gray coded counters and gray coded compare
logic.  Now I just have to simulate the 16 bit multiplier in VCS and make
sure it works ;-)

Thanks,

Austin


Ray Andraka <ray@andraka.com> wrote in article
<39A1C325.A1F05DAA@andraka.com>...
> DO you need a single cycle multiply, or is pipelined OK.  If pipelined is
OK, a
> 16x 16 properly designed will clock at about 150 MHz in a VIrtex -4 and
about
> 195 MHz in a -6.  24 bits is good to somwhere around 134 MHz (I've done
it at
> 134) in the -4 parts.  The design is not hard.  The COREGEN multiplier
will get
> close, but can be improved upon at the cost of some area if the speeds
don't
> meet your needs.
> 
> 
> Austin Franklin wrote:
> > 
> > Thanks for the tip, I'll check it out for the one multiplier they have.
 It
> > claims it can do a 16x16 multiply at 59MHz...in a Virtex -6.  We'll
see.
> > For the 4k/Spartan, there are two additional multipliers, one optimized
for
> > area, and one optimized for speed.
> > 
> > I don't do simulations with delay information, it's unnecessary.  I do
> > thought need an exact Verilog output model for this so I can do
simulation
> > in VCS.
> > 
> > Mike Peattie <mpeattie@xilinx.com> wrote in article
> > <398EFD5C.C845D6FA@xilinx.com>...
> > > Austin,
> > >
> > >     You can run ngdbuild on your design, which will merge all your
> > netlists
> > > together (including the coregen multiplier), then run ngd2ver to get
a
> > verilog
> > > simulation file.  This simulation will not have routing delays- it's
> > purely
> > > functional.
> > >
> > > Mike
> > >
> > > Austin Franklin wrote:
> > >
> > > > Torbjörn Stabo <etxstbo@kk.ericsson.se> wrote in article
> > > > <398A8153.6E265E32@kk.ericsson.se>...
> > > > > > Anyone have any Verilog code they'd be willing to share for a
> > 'decent'
> > > > > > multiplier?  I am looking for something that can do a 24 x 24
> > > > multiply...it
> > > > > > can take quite a few cycles, and it's for a Virtex
architecture.
> > > > >
> > > > > Have you tried Coregen? No source, but it sounds like it's the
result
> > > > that matters to you..
> > > > >
> > > >
> > > > Thanks for the suggestion, I did look at it, but it doesn't appear
to
> > have
> > > > a Verilog output mode.
> > > > If I don't get the Verilog source (or a protected model) then how
do I
> > unit
> > > > delay simulate it?
> > >
> > >
> 
> -- 
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com  
> http://www.andraka.com  or http://www.fpga-guru.com
> 
Article: 24909
Subject: Re: Looks like Xilinx is at it again!
From: "S. Ramirez" <sramirez@cfl.rr.com>
Date: Tue, 22 Aug 2000 00:40:43 GMT
Links: << >>  << T >>  << A >>
Rick,
     I agree with you here that they shouldn't make it a major PITA to file
technical support cases OR set up the tools.  I have a Customer ID number --
that should be sufficient.  In fact, when one calls the technical support
line, they ask you for it.
     When calling in, I have never been asked about whether I am under
maintenance or not.  I just simply furnish them my Customer ID number.  Who
cares if one is under maintenance or not?  If one is designing in their
product, that should be sufficient.  It will only result in silicon sales,
right?
     Every once in a while, Marketing or Sales does something that is
totally contrary to the design process.  The last thing we need in FPGA/ASIC
design is roadblocks!
     I hope Peter Alfke is lurking somewhere and reading all this stuff!  Of
course, he's engineering!
-Simon Ramirez, Consultant
-Synchronous Design, Inc.


> Anna Acevedo wrote:
> >
> >  Xilinx has made some changes (enhancements) to the web site as well as
> > changing service provider.  This may have caused some problem with the
scripts
> > that run the on line forms.
>
> I love when they "fix" the stuff that wasn't broken.  So explain to me
again why
> you need password protected access to submit a technical support case?
Seems to
> me if they already ask for all your info it would be relatively easy to
cross
> check that against a database to see that you are under maintenance if
they
> really felt that to be necessary.  Certainly it shouldn't become a major
PITA
> for the users who are in some cases already spending an inordinate amount
of
> time working around tools problems.



Article: 24910
Subject: urgent help fr a beginer
From: "ravikumar" <svkrishn@md3.vsnl.net.in>
Date: Mon, 21 Aug 2000 18:58:00 -0700
Links: << >>  << T >>  << A >>
dear friends
am goin fr interview
cananyone of u tell me a site so that i can learn quicker
pls also send a cc at ravikumar_ece@usa.net

ravi


Article: 24911
Subject: Re: Looks like Xilinx is at it again!
From: Greg Neff <gregneff@my-deja.com>
Date: Tue, 22 Aug 2000 02:10:44 GMT
Links: << >>  << T >>  << A >>
In article <39A1BC84.8FA7DA5D@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
(snip)
> I love when they "fix" the stuff that wasn't broken.  So explain to me
again why
> you need password protected access to submit a technical support case?
 Seems to
> me if they already ask for all your info it would be relatively easy
to cross
> check that against a database to see that you are under maintenance if
they
> really felt that to be necessary.
(snip)

It's not a question of maintenance qualification.  They want the
registration and password for security reasons.  Web support exchanges
are done on secure web pages.  The web support service maintains a
history of all support calls and responses, which you can access at any
time.  They don't want unauthorized people poking around and picking up
information exchanged between a customer and Xilinx support.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 24912
Subject: Re: Further FPGA metastability questions
From: murray@pa.dec.com (Hal Murray)
Date: 22 Aug 2000 02:27:43 GMT
Links: << >>  << T >>  << A >>

In article <V9yjiSA75Wo5EwcM@4Links.co.uk>,
 Paul Walker <paul@4Links.co.uk> writes:

> To excite the dither, would it be possible to use a pair of clocks
> running at almost the same frequency, but separated by a few ppm.
> 
> Suppose they are both nominally 100MHz, or 10ns period, and the
> difference between the frequencies is 10ppm, then the phase difference
> between them should change by about 0.1ps on each clock cycle. 

I don't think that helps.  Yes, it will have a good chance of
provoking a few metastable events each time the clocks drift
past eachother, but it will spend a long time cycling around to
try again so on the average it doesn't matter.


If the clocks are too close, I'd expect noise coupling through
the power supply or such might bring them into frequency lock.

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 24913
Subject: Re: Metastability and antifuze
From: murray@pa.dec.com (Hal Murray)
Date: 22 Aug 2000 02:47:24 GMT
Links: << >>  << T >>  << A >>

In article <QZTn5.8$ui4.20637@news.pacbell.net>,
 "Elftmann" <elftmann@pacbell.net> writes:

> Actel set out on the same mission to characterize metastability
> characteristics in our newer devices, but ran into the same problem as the
> Xilinx team did.  I'll check back with Product Engineers next week and see
> where it sits on the priority list these days.  As a result of past
> discussions in this group I continue to push on Product Engineering to make
> metastability characterization standard operating procedure.

Thanks.

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 24914
Subject: Re: Some notes on metastability
From: murray@pa.dec.com (Hal Murray)
Date: 22 Aug 2000 02:59:17 GMT
Links: << >>  << T >>  << A >>

> The topic of designing circuits for dealing with metastability is a very 
> well researched area. The now widely held belief is that it is impossible 
> to design such a circuit. Indeed, ALL claimed metastable free circuits 
> have been proven not to be. Usually the only thing achieved by complex 
> circuits that try and deal with all sorts of special cases, is that they 
> obscure the metastable mode during analysis. The best way to deal with 
> the metastable problem (the synchronization of an asynchronous signal 
> feeding into and affecting a synchronous system) is to synchronize the 
> signal with a multi stage synchronizer, comprizing of no more than 2 or 
> more flipflops, connected as a shift register, and clocked by the clock 
> of the destination domain.

I lump fix-it type circutis with snake oil and perpetual motion machines.
There is one good use for them.  They give you an instant calibration on
the author.

I'm not sure ALL of them have been proved not to work - idiots have
invented too many of them.  I can find the flaw in most of them.  A
runt reset pulse is common.  But it gets boring after a while.  It's
probably more productive to encourage vendors to provide data. 1/2 :)


Aside from complicating the analysis and wasting resources, I think
some of them are actually harmful.  If they add a gate delay in the
wrong place or increase the loading on a critical signal, then they are
reducing the gain-bandwidth product which increases the settling time.

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 24915
Subject: Re: Looks like Xilinx is at it again!
From: Peter Alfke <palfke@earthlink.net>
Date: Tue, 22 Aug 2000 03:23:39 GMT
Links: << >>  << T >>  << A >>


"S. Ramirez" wrote:

>
>      I hope Peter Alfke is lurking somewhere and reading all this stuff!  Of
> course, he's engineering!

He is always lurking. :-)
I have also forwarded the first comments in this thread to the VP in charge of
customer support. (Just a few hours ago. Let's see)
Some of this may be due to arcane change in procedure. I cannot imagine that
"we" are that dumb. And we definitely want to be helpful. That's our policy,
not just mine.

Peter Alfke

Article: 24916
Subject: Re: Mealy vs Moore FSM model
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 22 Aug 2000 00:10:03 -0400
Links: << >>  << T >>  << A >>
Jimmy Roberts wrote:
> 
> Hi Folks,
> 
> What are the advantages and disadvantages of using Mealy model of FSMs vs
> Moore model, on FPGA.
> In Mealy model, the outputs depends on the states only, whereas in Moore
> model, the outputs depend on the states and the actual inputs. I presume
> Mealy model is better (less combinatorial logic). Do you agree? Any other
> thoughts.

I use a modified Mealy model (or modfied Moore depending on how you look
at it) where the outputs are specified as only a function of the current
state, but are a implemented as a function of the previous state and the
previous inputs. What this means in hardware is that the outputs are
registered without delays by duplicating the next state functions along
with the output functions to feed the output registers. At the same time
you clock in the next state, you are clocking in the next output. No
output decoding glitches and no output delays. 

           _____________________________
          |     _______       _______   |
          |    |       |     |       |  |
          ---->|       |     |       |  |
input          | Next  |     | State |--+---> State
--------+----->| State |---->|       |  |
        |      |       |     |       |  | 
        |      |  f () |     |>      |  | 
        |      |_______|     |_______|  |
        |                               |
        |   ____________________________|
        |  |
        |  |    ________      ________      ________
        |  |   |        |    |        |    |        |   
        |  --->|        |    |        |    |        |   
        |      |  Next  |    |  Next  |    |        |   
        |      |  State |--->| Output |--->| Output |------> Output
        ------>|        |    |        |    |        |   
               |  f ()  |    |  g ()  |    |>       |   
               |________|    |________|    |________|

Next State = f (Input, Present State)
Ouput  = g ( f (Input, Present State))


In VHDL this allows me to specify both the NextState and the NextOutput
in the same case statement in the same process, very clean and easy to
maintain.

I don't normally worry about the quantity of combinatoral logic
generated by a particular machine type. I find that this is best
optimized by selecting the best encoding method for the machine size and
flow. In LUT based logic, the machine selection often does not have an
impact on the number of logic levels in the design. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 24917
Subject: Re: Some notes on metastability
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Mon, 21 Aug 2000 21:24:16 -0700
Links: << >>  << T >>  << A >>
Philip,

although devices may go metastable in the various ways you list, they
don't necessarily have to show all these behaviors. The symmetry of
the classic TTL cross-coupled flipflop was nasty because the compound
delays allowed a tail-chasing (oscillatory) mode, and the saturation
inherent in this mode reduced loop gain, prolonging the agony. A
positive feedback loop with one dominant (more like some CMOS flipflop
structures) pole can hang at the 'null' point, but is much less prone
to oscillate. The LS74 was awful; in one system we worked on, each
metastability event could be heard on a nearby FM radio.

The sometimes-seen analogy of a bowling ball perched on a knife edge
is misleading, because it will eventually fall off, but won't rock
back and forth first! A bowling ball has one dominant pole!

John

Article: 24918
Subject: Re: Mealy vs Moore FSM model
From: Lars Rzymianowicz <larsrzy@ti.uni-mannheim.de>
Date: Tue, 22 Aug 2000 09:34:36 +0200
Links: << >>  << T >>  << A >>
Jimmy Roberts wrote:
> What are the advantages and disadvantages of using Mealy model of FSMs vs
> Moore model, on FPGA.
> In Mealy model, the outputs depends on the states only, whereas in Moore
> model, the outputs depend on the states and the actual inputs. I presume
> Mealy model is better (less combinatorial logic). Do you agree? Any other
> thoughts.

It's the other way 'round. Outputs in Moore are dependent on the state,
in Mealy on the state and inputs.
So with Mealy, you can get glitches, etc., if your inputs arrive at
different times (or stabilize very late). And you have more logic. But
you can react within the present clk cycle.
With Moore, you avoid glitches, but still have an output delay due to
the output logic.
One step further is, what we call Simple-Moore. Use a user-defined state
encoding and include the outputs in the state vector. Then you have a Moore
machine with only clk-to-output delay, the fastest version you can get.

Lars
-- 
Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713
email:    larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/

Article: 24919
Subject: Re: Mealy vs Moore FSM model
From: murray@pa.dec.com (Hal Murray)
Date: 22 Aug 2000 07:35:45 GMT
Links: << >>  << T >>  << A >>

I'm missing the big picture.  Why do I care which type of FSM I use?

I normally lump the state and output bits together.  If an output
signal happens to be useful as a state bit, then I use it.  This
is fairly common in one-hot state machines.

Is there something wrong with doing that?

I'm usually working with small state machines.  Does that matter?


-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 24920
Subject: Re: Leonardo Spectrum with Altera - am I being stupid???
From: "Ernst Zwingenberger" <ernst.zwingenberger@elca.de>
Date: Tue, 22 Aug 2000 10:29:24 +0100
Links: << >>  << T >>  << A >>
Hi steve,

you may receive this error if you have not chosen Exemplar as the
third-party vendor in the MAX+PLUS II software or if your Library
Mapping File (.lmf) is set incorrectly in the MAX+PLUS II Compiler.
To verify these settings, perform the following steps in the Compiler:

   1. Choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select Exemplar from the Vendor drop-down list box (EDIF Netlist
      Reader Settings dialog box).

   3. Choose Customize to expand the EDIF Netlist Reader Settings dialog
box.

   4. Under Library Mapping Files, ensure that the LMF #1 option is turned
      on and that the exemplar.lmf file appears in the LMF #1 box.

search "Can't find design file DFF" at
http://www.altera.com/html/atlas/searchatlas.html for more details

Ernst Zwingenberger
El Camino GmbH
http://www.elca.de

<steve (Steve Rencontre)> schrieb in im Newsbeitrag:
<memo.20000821184516.1344W@steve.rsn-tech.co.uk>...
> I've been trying to get the free version of Leonardo Spectrum from
> Altera's web site to work. It seems fine up to place-and-route, when the
> MaxPlus2 compiler starts complaining it "Can't find design file DFF".
> Since that's an Altera primitive, it's not surprising it isn't in a design
> file! A bit of experimenting suggests it can't find /any/ of the
> primitives.
>
> I've tried it with an absolutely minimal design (see below) and it's just
> not having any of it. My installation of MaxPlus2 seems fine and I can
> compile non-Leonardo projects with no difficulty. I'm using Windows 2000,
> but the same thing happens with NT4.
>
> Anyone know the big secret?
>
> =======================================
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity test is
> port
>   (
>    CLK : in std_logic;
>  D : in std_logic;
>  NOT_D : out std_logic
>   );
> end test;
>
> architecture a of test is
> begin
>
>  process (CLK)
>  begin
>   if CLK'event and CLK = '1' then
>    NOT_D <= not D;
>   end if;
>
>  end process;
>
> end a;
>
>
>
> --
> Steve Rencontre  http://www.rsn-tech.co.uk
> file://#include <disclaimer.h>


Article: 24921
Subject: Re: Fully constrained designs...
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Tue, 22 Aug 2000 09:43:45 +0000
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> 
> How does the router know a register isn't changing every clock cycle?
> 
> This isn't difficult, it just takes time, as do most 'engineered' things,
> in order to do them right.  You just have to clearly, and accurately,
> timespec your design...the only one who knows how your design is supposed
> to work is you, the tools can't (for the most part) guess at what paths are
> multi-cycle...
> 
> It does take time up front to do this, but trust me, it saves you a LOT of
> time in the long run.  Also, taking the time to engineer an optimal pinout
> up front saves a LOT of time in the long run too...

Mind you you have to watch for circular problems.
If you are trying to evaluate several designs for gross timing,
how do know the optimal layout to get the timing right
to time the layouts?

Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Octal Computers:Where a step backward is two steps forward!"
 http://www.jetnet.ab.ca/users/bfranchuk/index.html
Article: 24922
Subject: Re: Mealy vs Moore FSM model
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 22 Aug 2000 08:49:17 -0400
Links: << >>  << T >>  << A >>
The difference between the Mealy and Moore machines is not the output
decoding. The difference is that the Mealy machine outputs only depend
on the state. The Moore machine outputs depend on how you got to that
state. So you need extra FFs to store the outputs. When you say you use
a state variable as an output, this is just referring to the state
assignment, not the machine type. 

If you are doing schematic design or instantiated HDL you can do any
machine design equally easily. For synthesized HDL, you want a machine
that will give you the type of outputs you need and minimize the
complexity of the code. I found the modified Mealy machine to be the
most straight forward to design with. 

The difference between the modified type and non-modified is also based
on the type of output you need. If you need an output that is glitch
free, then both the Mealy and the Moore machines may be a problem unless
you use a "glitch free" state assignment. The modified machines register
the outputs so that they are glitch free. This also gives you the
maximum setup time in the logic that uses your outputs. 



Hal Murray wrote:
> 
> I'm missing the big picture.  Why do I care which type of FSM I use?
> 
> I normally lump the state and output bits together.  If an output
> signal happens to be useful as a state bit, then I use it.  This
> is fairly common in one-hot state machines.
> 
> Is there something wrong with doing that?
> 
> I'm usually working with small state machines.  Does that matter?
> 
> --
> These are my opinions, not necessarily my employers.  I hate spam.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24923
Subject: Re: Mealy vs Moore FSM model
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 22 Aug 2000 08:57:09 -0400
Links: << >>  << T >>  << A >>
Lars Rzymianowicz wrote:
> 
> Jimmy Roberts wrote:
> > What are the advantages and disadvantages of using Mealy model of FSMs vs
> > Moore model, on FPGA.
> > In Mealy model, the outputs depends on the states only, whereas in Moore
> > model, the outputs depend on the states and the actual inputs. I presume
> > Mealy model is better (less combinatorial logic). Do you agree? Any other
> > thoughts.
> 
> It's the other way 'round. Outputs in Moore are dependent on the state,
> in Mealy on the state and inputs.
> So with Mealy, you can get glitches, etc., if your inputs arrive at
> different times (or stabilize very late). And you have more logic. But
> you can react within the present clk cycle.
> With Moore, you avoid glitches, but still have an output delay due to
> the output logic.
> One step further is, what we call Simple-Moore. Use a user-defined state
> encoding and include the outputs in the state vector. Then you have a Moore
> machine with only clk-to-output delay, the fastest version you can get.

Thanks, I never remember which name is which. But I would dispute your
claim that the Moore (outputs depend on the state only) is
"glitch-free". The glitches in this machine come from the state
variables switching at the same time. So you not only get delay, you get
glitches. 

The Mealy machine (outputs depend on inputs and state) can be made to be
glitch free. This depends on how you interpret the machine. I don't
think many people really need a machine whose output changes
asynchronously with the input, but really want a clock synchronized
output. In this case the Mealy machine uses FFs to store the outputs
that correspond to the state transitions. These outputs are remembered
until the next clock. This will be a truly "glitch-free" output. 

The way I learned it is that the Moore machine outputs depend on the
states, the Mealy machine outputs depend on the transitions. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24924
Subject: Re: Mealy vs Moore FSM model
From: "Jimmy Roberts" <j_robby@hotmail.com>
Date: Tue, 22 Aug 2000 15:12:16 +0100
Links: << >>  << T >>  << A >>
> It's the other way 'round. Outputs in Moore are dependent on the state,
> in Mealy on the state and inputs.

You are right, I always call it the other way round.

> One step further is, what we call Simple-Moore. Use a user-defined state
> encoding and include the outputs in the state vector. Then you have a
Moore
> machine with only clk-to-output delay, the fastest version you can get.

Is it always possible to encode the states so that the outputs are in the
state vector?
I do not think so...




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