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Messages from 62450

Article: 62450
Subject: Re: How to protect fpga based design against cloning?
From: "kryten_droid" <kryten_droid@ntlworld.com>
Date: Thu, 30 Oct 2003 02:31:37 -0000
Links: << >>  << T >>  << A >>
"Hal Murray" <hmurray@suespammers.org> wrote in message
news:vq0q8120q03379@corp.supernews.com...
> >That idea of shipping the SIM separately to the
> >end-users, so that the (contract) manufacturer cannot sell units on
> >the side, also has merit.
>
> How much of a problem is that?
>
> I'd think that major US based contract manufacturer would be
> very careful.  It would be a serious damage to their reputation
> if something like that happened and word about it got out.

True.

I suspect most people only behave fairly because of the risks and costs of
getting caught are high.

In poorer parts of the world (where much manufacturing is done) they have
much to gain from 'cheating' and know the difficulty of flying lawyers there
to do expensive international legal actions.

Often they don't give a mouse-sized shit -
their attitude is "what are you going to do about it?"

Some people don't have a reputation to worry about.




Article: 62451
Subject: Questions that question????
From: ramntn@yahoo.com (ram)
Date: 29 Oct 2003 19:35:26 -0800
Links: << >>  << T >>  << A >>
Hi everybody,
  I am thinking abt how much information can be provided to a quetion
posted related to design with emerging hitech FPGA's.I started using
this usenet just a few weeks ago,and I find it very interesting to
notice people with great experience working in industries or with FPGA
manufacuturers replying to the best they could.So I started thinking,
how much of an information related to the desing should be given for a
question.
The less information i give, i likely to get no repliess, and the more
i give , i might loose my valuable design , what would be a tradeoff
here?
So, how do people in industry find a solution to their desing at the
very shortest time and make sure the product hits the market, before
their competitors make it.
regards
RaM

Article: 62452
Subject: Re: Questions that question????
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 30 Oct 2003 04:06:34 GMT
Links: << >>  << T >>  << A >>
"ram" wrote:

> The less information i give, i likely to get no repliess, and the more
> i give , i might loose my valuable design , what would be a tradeoff
> here?

Well, you have to be intelligent about how you conduct yourself.  It's one
thing to talk about and ask about how to design a UART module, for example,
and quite another to discuss complete designs, including proprietary
information.  You have to assume that your competitors are also on the list.
It would be silly not to.

Any non-trivial design is going to be quite complex, with hundreds, if not
thousands of lines of code.  The context of most USENET questions is the
realm of a few lines of code or issues dealing with architechture,
approaches to take and some basic digital signal processing theory.  Clearly
you will not post whole designs here.  And, clearly you should not post code
fragments that might reveal something that you may not want to have your
competitors see.

A common technique is to write a new little chunck of code that shows the
problem without the context of the rest of your design being present.  For
example, you can talk about how to efficiently count 1's in a data stream
without telling the world that you are working on data compression.

This is something that we all have to deal with in one way or another.  In
general, the benefits outweigh the risk, by far.  Just be smart.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 62453
Subject: DDFS technique problem in generating a few clocks
From: atif@kics.edu.pk (Atif)
Date: 29 Oct 2003 20:13:16 -0800
Links: << >>  << T >>  << A >>
Hello all,
I am generating the clock of frequency 548KHz from an input clock of
73.728MHz. I am using the Direct digital frequency synthesis DDFS
technique from 
www.xilinx.com/xcell/xl31/xl31_32.pdf
But I am getting the wrong output as;
*************************************************
Running...
                 929 929.134	 t=0.000000 
929.134period=929.134000 
929.134t=929.134000 
freq=1076271.022264 HZ
                2747 2746.71	 t=929.134000 
2746.71period=1817.576000 
2746.71t=2746.710000 
freq=550183.321083 HZ
                4578 4577.85	 t=2746.710000 
4577.85period=1831.140000 
4577.85t=4577.850000 
freq=546107.889075 HZ
Exiting VeriLogger Pro at simulation time 10000000
0 Errors, 0 Warnings
Compile time = 0.00000, Load time = 0.04700, Execution time = 0.04700

Normal exit
***********************************************************************
Here is the code of my program:
***********************************************************************
// Thanks to Jonathan Bromley for his valuable suggestions for the
code.
`timescale 1ns/1ps
module fulladd28(out,clock,reset);
   parameter a=28'd1995207;
   parameter w = 28; // bit width of phase accumulator
   output out;
   input clock, reset;
   reg [w-1:0] sum;
   always @(posedge clock or posedge reset)     
         if(reset)
               sum <= 0;
           else
              sum <= sum+a;
   assign out = sum[w-1];
endmodule	//end of module fulladd28
module stimulus;
   wire OUT;
   reg CLOCK, RESET;
   fulladd28 myfulladd28(OUT, CLOCK, RESET);
   always@(posedge OUT)
      begin
         :freqmeter
         real t, period;
         period=$realtime - t;
         $display($time, " ", $realtime, "\t t=%f ",t);
         $display($realtime, "period=%f ",period);
         t=$realtime;
         $display($realtime, "t=%f ",t);
         $display("freq=%f HZ", 1000000000/period);
      end
   initial
      begin
         RESET=1'b1;
         #10 RESET=1'b0;
      end
   initial
      begin
         CLOCK=1'b0;
         forever #6.782 CLOCK=~CLOCK;
      end
   initial
      begin
         #10000 $finish;
      end
endmodule //end of module stimulus
***********************************************************************

Can anyone please guide me why is this deviation from the desired
frequency and how to remove this? Is there any other accurate method
of generating the desired frequency from the input one?
I want the accuracy of 20ppm. The device to be used is
Xc2s50-5PQ208-I.

Thanks and Regards
Atif Nadeem
Research Associate

Article: 62454
Subject: Re: How to protect fpga based design against cloning?
From: jakespambox@yahoo.com (Jake Janovetz)
Date: 29 Oct 2003 21:06:16 -0800
Links: << >>  << T >>  << A >>
Several years ago in an interview with a large company, a friend of
mine asked how they ended up reverse engineering a product from
another large company.  The guy smirked and said: "We removed the top
and took lots of pictures."  They were working on a full-custom ASIC.

First entry on Google: http://www.bltinc.com

   Jake


khimbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote in message news:<3fa04f49.34454006@news.compuserve.com>...
> On Wed, 29 Oct 2003 13:30:09 +0100, Markus Zingg <m.zingg@nct.ch>
> wrote:
> 
> >Hi all
> >
> >I don't know too much about fpga's yet so bear with me if this sounds
> >too silly. I'm quite interested from what I heard so far and intend to
> >dig deeper into the topic.
> >
> >While reading diverse articles about fpga's I got the impression that
> >they have to be programmed out of a prom or through a microprocessor
> >etc. However, this means that it would be very easy to "catch" this
> >code in a finished design and abuse it to clone/copy such a design.
> >
> >So, my question is, is my impression right, and if so what common
> >protection mechanisms are available? Or are there fpga's available
> >that contain flash memory for the purpose of progrmming them on chip
> >or such? Some scheme similar to what's available with most
> >microcontrollers that contain on chip flash?
> >
> >TIA
> >
> >Markus
> 
> This is an interesting subject.  I guess there are two concerns:
> 
> 1)  Theft of the configuration bitstream so that you could clone and
> produce identical products.  Obviously the circuitry connected to the
> FPGA would have to be a copy and probably not to hard to go after the
> bad guys in the courts with copywrite laws etc.  I am more concerned
> about #2.
> 
> 2)  IP Theft.  The question here is ( in the Altera/Xilinx context )
> if you record the configuration bitstream what can you do with it as
> far as reverse engineering ?  Can anyone reasonably , meaning with
> existing tools or software or ... how?,   take this bitstream and
> figure out your HDL  ?  I wouldn't know where to start but perhaps
> there are some factory or other smart folks here who have a better
> insight into this ??  
> 
> Khim Bittle

Article: 62455
Subject: Some FPGA questions
From: snarflemike@yahoo.com (Mike Silva)
Date: 29 Oct 2003 22:17:12 -0800
Links: << >>  << T >>  << A >>
I'm an embedded software type who has suddenly gotten a strong urge to
learn about FPGAs and VHDL.  I've done a fair amount of hardware
design in the past, but only using standard micros, peripherals, 74xx
stuff, etc.  I've looked at some beginner threads, but I have some
questions that I did not see answers to.  I know these are vague
questions, but they're the best I can come up with for now:

1) I know I want to learn VHDL.  I know this (or at least, I think I
know this) because I've used C a whole lot, and Ada a little, and I
vastly prefer Ada.  I read a comment here that while Verilog may be
used more in the US for ASICs, VHDL is used more for FPGAs.  If true,
why is this?

2) Where do I get a free VHDL compiler?  Does it come with the free
tools from Xilinx and/or Altera?  Or do those free tools simply work
with other vendors' compilers?  The whole tool situation is completely
confusing to me.

3) For my situation, where ease of learning and a cheap but capable
evaluation board are the important considerations, which company's
free tools and which evaluation board should I get?

4) I'd also like to find what I guess I'd call prototyping boards,
with my meaning of the difference being that an evaluation board would
have enough hardware to make for a reasonable development environment,
while a prototyping board would be a cheaper and smaller board using
the same FPGA for one-off or very low volume projects.

5) Is it a fairly simple process to download VHDL modules floating
about on the web and incorporate them?  I am particularly fascinated
by the notion of downloading a CPU core and building some goodies
around it.

6) Eventually I'd like to learn enough to be able to design a simple
CPU core.  Is this a reasonable goal for an after-work "hobby"?  How
big are e.g. 8-bit CPUs like the 6811, Z80, AVR, etc, in lines of
code, and FPGA real estate? (measured in gates?  is that the standard
unit of chip real estate?)

Thanks for any answers or suggestions!

Mike

Article: 62456
Subject: Re: Xilinx Spartan3: Price
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 30 Oct 2003 06:32:51 GMT
Links: << >>  << T >>  << A >>
"Austin Lesea" wrote:

> A real customer doesn't care what it costs right now, because 'right now'
is
> not when they are going to sell anything.  They want to know what it will
cost
> when they go into production (along with all of their competitors).

Nitpicking, but, companies like mine are "real customers" yet we only need a
few hundred or thousand devices for production ... not hundreds of
thousands.

I've always thought that semiconductor pricing was unfairly skewed to favor
the big guys.  I understand discount structures, etc., but there's a huge
difference between $200 and $12.  And, it's weird, 'cause you'd think that
you'd sell a ton more chips if the little guys could buy them at a more
affordable price point.

I've been dealing with a semiconductor manufacturer that's been downright
rude about discounts because they were the only game in town.  Now, with
Virtex 2 Pro's high speed serial I/O capabilities I have a chance to drop
them like a hot potato in my next design.  The likelyhood of that happening
is extremely high at this point.  I'm sure they bend over backwards for
those who move more chips, but, what they don't realize (even though I've
explained it), is that I'm ramping up.  They are literally handing Xilinx
business to the tune of thousands of V2P's per year.  Very unwise.

So, the high cost of chips for the sub 1K/year crowd might very well make
them look elsewhere and, as you can imagine, once you adopt and get
comfortable with another vendor the chances of getting a different chip onto
that a board are pretty low.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 62457
Subject: Re: Some FPGA questions
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Thu, 30 Oct 2003 06:54:17 GMT
Links: << >>  << T >>  << A >>
"Mike Silva" wrote:

> I'm an embedded software type who has suddenly gotten a strong urge to
> learn about FPGAs and VHDL.  I've done a fair amount of hardware

A few links that might be of interest to you (this is Xilinx/VirtexII
slanted):

Read this first:
 http://www.xilinx.com/univ/beginnersbookjune2003ver2.pdf

You need to read through the VirtexII data sheet:
 http://direct.xilinx.com/bvdocs/publications/ds031.pdf

and user guide:
 http://direct.xilinx.com/bvdocs/userguides/ug002.pdf

Then move on to the development system manuals:
 http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.pdf

probably get started with this one:
 http://toolbox.xilinx.com/docsan/xilinx6/books/docs/dev/dev.pdf



> 1) I know I want to learn VHDL.  I know this (or at least, I think I
> know this) because I've used C a whole lot, and Ada a little, and I
> vastly prefer Ada.  I read a comment here that while Verilog may be
> used more in the US for ASICs, VHDL is used more for FPGAs.  If true,
> why is this?

In the begining it probably doesn't make any difference which language you
go with.  In fact, Verilog might be faster and quicker to learn, since you
know C.  You'll slip right into it.
However, if you want to go beyond canned push-button designs in FPGA's I
think it's fair to say that nothing beats the capabilities afforded by VHDL.
This is almost the sort of thing that has to burn you for you to "see the
light" and understand why on tool can be (and is) better than the other.

For the record. I use Verilog.

For the record #2.  I know that I'll have to migrate to VHDL because Verilog
has already gotten in the way of optimizing my designs.

> 2) Where do I get a free VHDL compiler?

Download Xilinx Webpack

> 3) For my situation, where ease of learning and a cheap but capable
> evaluation board are the important considerations, which company's
> free tools and which evaluation board should I get?

Avnet and Insight/Memec have nice boards.  The range is from about US$200 to
over US$700.  The Microblaze board (expensive) might be what you are looking
for.

> 5) Is it a fairly simple process to download VHDL modules floating
> about on the web and incorporate them?  I am particularly fascinated
> by the notion of downloading a CPU core and building some goodies
> around it.

Once you understand the game, and if they are well written, yes.

The toughest thing to understand for a (let's generalize) software guy is
that, in the FPGA game, perfectly good code does not equate to a working
design.  You can have an HDL module that is a thing of beauty and does
exactly what it is supposed to do in a logical sense.  However, to make that
chunk-o-code work in a chip there are a number of other considerations that
come into play.  So, yet, generally speaking you might be able to use
downloaded code, but, in the context of a non-trivial design having good
code alone doesn't do the deed.


> 6) Eventually I'd like to learn enough to be able to design a simple
> CPU core.  Is this a reasonable goal for an after-work "hobby"?

I think so.  Hey, no delivery schedules!  That's paradise!


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 62458
Subject: Re: How to protect fpga based design against cloning?
From: "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Thu, 30 Oct 2003 07:21:32 GMT
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FA06256.3B3F612B@xilinx.com...

> Khim Bittle wrote:
(snip)
> > 2)  IP Theft.  The question here is ( in the Altera/Xilinx context )
> > if you record the configuration bitstream what can you do with it as
> > far as reverse engineering ?  Can anyone reasonably , meaning with
> > existing tools or software or ... how?,   take this bitstream and
> > figure out your HDL  ?  I wouldn't know where to start but perhaps
> > there are some factory or other smart folks here who have a better
> > insight into this ??
> >
> The simple answer is that it is impossible, since there is no
> documentation about the function of the individual config bits.
> The more sophisticated answer would be that is outrageously difficult
> and time consuming. After all the detective work figuring out what
> millions of individual bit are doing ( or not doing), you finally arrive
> at a big unstructured circuit mess.
> Good luck!
> I think it is easier to re-invent the functionality than to
> reverse-engineer it.

For large designs, I would have to agree.  People used to talk about
disassembling software and reverse engineering from that.   In the days when
software was 8K bytes or so, it might have been possible.   It is possible
to carry around 4000 lines of disassembled code, try to follow it and
comment it as one learns the functions.    Consider that some programs today
may be 80M, or maybe 20 million lines of disassembled code.   Well, maybe
some of it is tables and such.   It may have been written in a high-level
language, but you will get uncommented assembly code, with numeric addresses
instead of symbolic ones.

It might have been possible to disassemble the code for an XC4002 and figure
out the functions.   You might be able to carry around the netlist for it.
It will be a netlist, and likely not VHDL, or at least not readable VHDL.
For a device with millions, or hundreds of millions of equivalent gates,
well, you can figure out how big it might be to print.

It would probably be possible if your budget is in the tens of millions of
dollars or so.  Just a guess.

-- glen



Article: 62459
Subject: Re: Some FPGA questions
From: "Matt North" <m.r.w.north@NO_SPAMrl.ac.uk>
Date: Thu, 30 Oct 2003 08:32:05 -0000
Links: << >>  << T >>  << A >>
Mike,

Another link which might give you a good starting point for writing CPU
cores in Verilog/VHDL

www.opencores.org

I also agree that the xilinx web pack is a good place to start, you get
Modelsim and other goodies.

>>in the FPGA game, perfectly good code does not equate to a working
> >design.

This is because languages like VHDL are HARDWARE description languages, you
code should be
written is such a way that a synthesis tool can recognise it as a counter,
memory, mux etc.
The tool will then have a better chance at optimise your design.

A bit of hardware design experience doesn't go amiss either, it is sometimes
a good idea to think about
how the problem could be tackled using descrete logic blocks and then
convert them into components.

Matt


"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message
news:tA2ob.3157$qU1.32380119@newssvr21.news.prodigy.com...
> "Mike Silva" wrote:
>
> > I'm an embedded software type who has suddenly gotten a strong urge to
> > learn about FPGAs and VHDL.  I've done a fair amount of hardware
>
> A few links that might be of interest to you (this is Xilinx/VirtexII
> slanted):
>
> Read this first:
>  http://www.xilinx.com/univ/beginnersbookjune2003ver2.pdf
>
> You need to read through the VirtexII data sheet:
>  http://direct.xilinx.com/bvdocs/publications/ds031.pdf
>
> and user guide:
>  http://direct.xilinx.com/bvdocs/userguides/ug002.pdf
>
> Then move on to the development system manuals:
>  http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.pdf
>
> probably get started with this one:
>  http://toolbox.xilinx.com/docsan/xilinx6/books/docs/dev/dev.pdf
>
>
>
> > 1) I know I want to learn VHDL.  I know this (or at least, I think I
> > know this) because I've used C a whole lot, and Ada a little, and I
> > vastly prefer Ada.  I read a comment here that while Verilog may be
> > used more in the US for ASICs, VHDL is used more for FPGAs.  If true,
> > why is this?
>
> In the begining it probably doesn't make any difference which language you
> go with.  In fact, Verilog might be faster and quicker to learn, since you
> know C.  You'll slip right into it.
> However, if you want to go beyond canned push-button designs in FPGA's I
> think it's fair to say that nothing beats the capabilities afforded by
VHDL.
> This is almost the sort of thing that has to burn you for you to "see the
> light" and understand why on tool can be (and is) better than the other.
>
> For the record. I use Verilog.
>
> For the record #2.  I know that I'll have to migrate to VHDL because
Verilog
> has already gotten in the way of optimizing my designs.
>
> > 2) Where do I get a free VHDL compiler?
>
> Download Xilinx Webpack
>
> > 3) For my situation, where ease of learning and a cheap but capable
> > evaluation board are the important considerations, which company's
> > free tools and which evaluation board should I get?
>
> Avnet and Insight/Memec have nice boards.  The range is from about US$200
to
> over US$700.  The Microblaze board (expensive) might be what you are
looking
> for.
>
> > 5) Is it a fairly simple process to download VHDL modules floating
> > about on the web and incorporate them?  I am particularly fascinated
> > by the notion of downloading a CPU core and building some goodies
> > around it.
>
> Once you understand the game, and if they are well written, yes.
>
> The toughest thing to understand for a (let's generalize) software guy is
> that, in the FPGA game, perfectly good code does not equate to a working
> design.  You can have an HDL module that is a thing of beauty and does
> exactly what it is supposed to do in a logical sense.  However, to make
that
> chunk-o-code work in a chip there are a number of other considerations
that
> come into play.  So, yet, generally speaking you might be able to use
> downloaded code, but, in the context of a non-trivial design having good
> code alone doesn't do the deed.
>
>
> > 6) Eventually I'd like to learn enough to be able to design a simple
> > CPU core.  Is this a reasonable goal for an after-work "hobby"?
>
> I think so.  Hey, no delivery schedules!  That's paradise!
>
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin Euredjian
>
> To send private email:
> 0_0_0_0_@pacbell.net
> where
> "0_0_0_0_"  =  "martineu"
>
>



Article: 62460
Subject: Re: Some FPGA questions
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Thu, 30 Oct 2003 08:48:29 -0000
Links: << >>  << T >>  << A >>
Mike Silva <snarflemike@yahoo.com> wrote in message
news:20619edc.0310292217.1aecaef@posting.google.com...

> 5) Is it a fairly simple process to download VHDL modules floating
> about on the web and incorporate them?  I am particularly fascinated
> by the notion of downloading a CPU core and building some goodies
> around it.


A good start here would be to look at Xilinx's Picoblaze. It's a very
simple CPU core that's freely available.

If you look on the downloads page of my web site you'll find a tutorial
which walks you through building a design based on the Picoblaze with
Xilinx's free tools, Webpack.


Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk




Article: 62461
Subject: Re: Xilinx Spartan3: Price
From: news@sulimma.de (Kolja Sulimma)
Date: 30 Oct 2003 01:04:10 -0800
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote in message news:<3FA01AE9.BFCBD7A1@xilinx.com>...
> Uwe Bonnes wrote: 
> > If everyone of this team of 250 could contribute one day of lead time we
> > could also get  in a time frame where the parts are really available on the
> > market :-)
> > 
> One minute per team member would be sufficient.  :-)
> Peter Alfke

Which really is a contradiction to Austins post who essentially
explained the price difference with a 6 Month delay before purchase.

You are suggesting that in 250 Minutes the 250k price is going to drop
to 12$ but I doubt that the Avnet price is going to drop today.

So there would be a factor of 16 volume discount compared to a 1k
price.
I believe you agree that this is unusual?

Kolja Sulimma

Article: 62462
Subject: Re: How to protect fpga based design against cloning?
From: Markus Zingg <m.zingg@nct.ch>
Date: Thu, 30 Oct 2003 10:06:34 +0100
Links: << >>  << T >>  << A >>
>This discussion has not mentioned the best protection in any FPGA:
>All Xilinx Virtex-II devices have an on-chip decryptor that can decrypt
>a triple-DES encoded bitstream, using an on-chip stored 3x56-bit key.
>This key is kept alive with a small external battery. A small price to
>pay for the best security in a wide range of high-performance FPGAs...
>Peter Alfke, Xilinx Applications

Hi Peter

Thanks for your reply. This sounds like a good solution too. The
battery aproach is a bit two folded. On one hand it may adds security
in that if someone would tamper with the device and power would be
interupted the key is lost. On the other hand there are the added
costs of such a battery and also the not always so consistent
livespan. In other words the user would not even be able to replace
this battery or in other words, once the battery is low the product is
trash - right?

Markus

Article: 62463
Subject: Re: Xilinx Spartan3: Price
From: "Simon Peacock" <nowhere@to.be.found>
Date: Thu, 30 Oct 2003 22:18:41 +1300
Links: << >>  << T >>  << A >>
If I was buying 250k units.. I would be knocking on Peters door not
Avnet's.. when your interested in real volumes you don't have the cash to
waste on middle men.

Simon

"Kolja Sulimma" <news@sulimma.de> wrote in message
news:b890a7a.0310300104.2f095b62@posting.google.com...
> Peter Alfke <peter@xilinx.com> wrote in message
news:<3FA01AE9.BFCBD7A1@xilinx.com>...
> > Uwe Bonnes wrote:
> > > If everyone of this team of 250 could contribute one day of lead time
we
> > > could also get  in a time frame where the parts are really available
on the
> > > market :-)
> > >
> > One minute per team member would be sufficient.  :-)
> > Peter Alfke
>
> Which really is a contradiction to Austins post who essentially
> explained the price difference with a 6 Month delay before purchase.
>
> You are suggesting that in 250 Minutes the 250k price is going to drop
> to 12$ but I doubt that the Avnet price is going to drop today.
>
> So there would be a factor of 16 volume discount compared to a 1k
> price.
> I believe you agree that this is unusual?
>
> Kolja Sulimma



Article: 62464
(removed)


Article: 62465
Subject: PicoBlaze for Altera (ACEX1K)?
From: Pratip Mukherjee <pratipm@hotmail.com>
Date: Thu, 30 Oct 2003 11:27:59 GMT
Links: << >>  << T >>  << A >>
Hi,
I am looking for PicoBlaze (or similar) processor implementation for Altera 
ACEX1K FPGA.
Thanks in advance.

Pratip Mukherjee

Article: 62466
Subject: VirtexII-Pro: Full Readback via ICAP/SelectMAP
From: Sean Durkin <_23_@iis._42_.de>
Date: Thu, 30 Oct 2003 13:36:50 +0100
Links: << >>  << T >>  << A >>
Hi *,

I've been playing around with the internal SelectMAP-port (ICAP) of a 
2VP7 hooked up to the internal PPC (using info and code from xapp661). 
Reading and writing of registers (like ID code register and such) and 
single frames works fine, so the interface itself seems to be doing what 
it should.

I then tried to do a full readback (just the CLB data, no 
BlockRAM-contents and such), using the information from xapp138 and the
.rba-file, but readback stops somewhere in the middle, as I get no more 
data from the ICAP-interface.

Now, as I understand it, a 2VP7 has 1320 frames consisting of 424 Bytes 
each, so that should be 559680 Bytes for the configuration data alone 
plus the 4 padding bytes that proceed every frame, plus one padding 
frame at the beginning. That means a full readback should give me 565384 
Bytes of data, which then would have to be stripped of the padding data 
and masked with the .msk-file before being compared to the data in the 
.rbt-file for verification.

Yet after about 365000 Bytes or so I get no more data from the ICAP and 
the transfer stops, even though I issue a command to the ICAP to send me 
0x222fa 32bit-data words, exactly as it's done in the .rba-file.

I'm sure I'm missing something obvious here... has someone else done 
this, maybe via the external SelectMAP-port?

This is what I send to the ICAP to initiate the transfer:

/* This should initiate a full readback: */
static char cmd_fullReadback[44] = {
0xFF, 0xFF, 0xFF, 0xFF, /* Dummy Word */
0xAA, 0x99, 0x55, 0x66, /* Sync Word */
0x30, 0x01, 0xC0, 0x01, /* Write ID Code Register with next word */
0x01, 0x24, 0xA0, 0x93, /* XC2VP7 Product Code written to ID Register */
0x30, 0x00, 0x80, 0x01, /* Write to CMD Register */
0x00, 0x00, 0x00, 0x04, /* Command RCFG - Read Configuration Data */
0x30, 0x00, 0x20, 0x01, /* Write to Frame Address Register(FAR)*/
0x00, 0x00, 0x00, 0x00, /* Frame Address of Interest: 0x0 (beginning)*/
0x28, 0x00, 0x60, 0x00, /* Read from Frame Data Output Register(FDRO) */
0x48, 0x02, 0x22, 0xFA, /* Read 0x222fa 32bit-data words in 
command, as 				is done in .rba-file */
0x00, 0x00, 0x00, 0x00  /* Pad */
};

I then start reading single bytes and putting them into external RAM.

Any pointers as to what I'm missing would be greatly appreciated...

-- 
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany

mailto:23@iis.42.de
([23 , 42] <=> [durkinsn , fraunhofer])


Article: 62467
Subject: Accessing Ports of a "User to Interface Logic" on a Altera Nios
From: svpfit00@fht-esslingen.de (Sven)
Date: 30 Oct 2003 05:28:16 -0800
Links: << >>  << T >>  << A >>
I´m trying to access the Compact Flash Interface on the Altera Stratix
Board.
Searching Altera´s documentation did not bring any helping topics.
I found out that in the standard_32.sof the CF Adapter is connected to
the Nios Processor via a Avalon Bus Slave
using a "Interface to user logic". The "Interface to user logic" is
named "cf_ide_interface" and looks in SOPC
Builder like this .... 

"Port Name"   Width  Dicrection  Shared   Type
clk             1     input                clk
address         5     input                address
write_n         1     input                write_n
read_n          1     input                read_n
data            16    inout                data

in the generated "excalibur.h" the cf_ide_interface appears seamless
as a poiter to a memory address ...

#define na_cf_ide_interface          ((np_usersocket *) 0x00920a00) //
altera_avalon_user_defined_interface
#define na_cf_ide_interface_base                        0x00920a00

my generic problem is now howto access the different ports at this
memory address because i´m wondering
where does the data start or howto mask for e.g. the write_n bit ?

Can I assume that the ports are aligned in the same order at the
address like they appear in the list
above?

regards sven

Article: 62468
Subject: Hit Logic
From: andres.vazquez@gmx.de (Vazquez)
Date: 30 Oct 2003 05:36:13 -0800
Links: << >>  << T >>  << A >>
Hi,

I have a question concerning a possibility to find out whether
there is a hit or not (cache).

How can I check with few ressources need (Altera Cyclone device)
if there is one or more positions with '1'
within a 32bit-vector (in this case a signal hit='1'
should be the result)? 

Thank you very much for your help.


Kind regards
Andrés Vázquez
G&D System Development

Article: 62469
Subject: Re: Some FPGA questions
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Thu, 30 Oct 2003 14:00:00 +0000
Links: << >>  << T >>  << A >>
On Thu, 30 Oct 2003 06:54:17 GMT, "Martin Euredjian"
<0_0_0_0_@pacbell.net> wrote:

>"Mike Silva" wrote:
>
>> I'm an embedded software type who has suddenly gotten a strong urge to
>> learn about FPGAs and VHDL.  I've done a fair amount of hardware
>

>> 1) I know I want to learn VHDL.  I know this (or at least, I think I
>> know this) because I've used C a whole lot, and Ada a little, and I
>> vastly prefer Ada.  I read a comment here that while Verilog may be
>> used more in the US for ASICs, VHDL is used more for FPGAs.  If true,
>> why is this?
>
>In the begining it probably doesn't make any difference which language you
>go with.  In fact, Verilog might be faster and quicker to learn, since you
>know C.  You'll slip right into it.

If he knows and prefers ADA, (presumably for its unambiguity, clarity
and precision, compared to C) he will prefer VHDL, for precisely the
same reasons, to Verilog.

If you prefer Verilog, you probably prefer C to ADA. They are certainly
more concise. But that comes at a cost. (I don't mind a bit of extra
typing - in both senses - to save scratching my head)

>> 2) Where do I get a free VHDL compiler?
>
>Download Xilinx Webpack

>> 3) For my situation, where ease of learning and a cheap but capable
>> evaluation board are the important considerations, which company's
>> free tools and which evaluation board should I get?
>
>Avnet and Insight/Memec have nice boards.  The range is from about US$200 to
>over US$700.  The Microblaze board (expensive) might be what you are looking
>for.

Consider also www.xess.com

>> 5) Is it a fairly simple process to download VHDL modules floating
>> about on the web and incorporate them?  

>Once you understand the game, and if they are well written, yes.
>
>The toughest thing to understand for a (let's generalize) software guy is
>that, in the FPGA game, perfectly good code does not equate to a working
>design.  

If you have 74 series experience, you'll probably be fine. The
limitations are along the lines of keeping the design realisable in
hardware, such as avoiding code that would try to synthesise to a
flipflop with two clock signals, or compare a logic level against "Z"
(high-Z) instead of '0' or '1'.

Such non-realizable code is of course perfectly OK in a testbench, but
not in the design itself! Download and read a guide to VHDL coding for
synthesis - Xilinx have a good one - and it makes pretty good sense.

- Brian

Article: 62470
Subject: CLKFX problem with a Virtex II
From: jean-francois.hasson@fr.thalesgroup.com (jean-francois hasson)
Date: 30 Oct 2003 06:35:12 -0800
Links: << >>  << T >>  << A >>
Hi,

In the design I am working on there is (for the moment) a DCM
generating a CLK0, CLK2X and CLKFX outputs with CLKIN being 40 MHz and
no reset on the RST pin of the DCM (tied to VCC). All seems fine
during functionnal simulation but on the board the CLKFX does not
toggle (STATUS<2> of DCM is high but the LOCK is high too !?!). What
is confusing among other things is that a previous version of this
design was previously working fine on the board regarding this clock
at 160 MHz (clkfx). The difference between this failing version and
the previous one that I can think of is the fact that a fair amount of
logic has been added otherwise same board, same fpga, same clocking
scheme, ... If anyone can give me a piece of advice that would be of
great help. I will do further inverstigation in the mean time.

Thanks,

JF

Article: 62471
Subject: simulation stops preliminarily
From: "Valentin Tihomirov" <valentin@abelectron.com>
Date: Thu, 30 Oct 2003 16:48:49 +0200
Links: << >>  << T >>  << A >>
this code causes 100% simulation failure.

   Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value

   assert (Rx = '0')                    -- fail if bit = '1'
    report "Invalid data received1!"
    severity failure;

   assert (Rx = '1')                        -- fail if bit = '0'
    report "Invalid data received2!"
    severity failure;

   wait until AVAIL = '1';

   wait; -- will wait forever





I need to check a vaue after AVAIL rises to '1'. But the following test
shows that simulator ignores ASSERT clauses placed between WAIT forever
statement.

   Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value

   wait until AVAIL = '1';        -- wait for condition


-- these assertions are ignored by simulator!

   assert (Rx = '0')                    -- fail if bit = '1'
    report "Invalid data received1!"
    severity failure;

   assert (Rx = '1')                        -- fail if bit = '0'
    report "Invalid data received2!"
    severity failure;

   wait; -- will wait forever




Does ModelSim behaves properly?



Article: 62472
Subject: Re: PicoBlaze for Altera (ACEX1K)?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 30 Oct 2003 14:49:36 +0000
Links: << >>  << T >>  << A >>
Pratip Mukherjee <pratipm@hotmail.com> writes:

> Hi,
> I am looking for PicoBlaze (or similar) processor implementation for Altera 
> ACEX1K FPGA.

Erm, Picoblaze itself sounds unlikely - Picoblaze was very carefully
targetted to the Xilinx architecture.  I'm sure something similar
could be done for Altera, but I don't know of one - sorry.

Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 62473
Subject: TAP controller state vs PROG pin
From: RobertP <rpudlik@poczta.onet.pl>
Date: Thu, 30 Oct 2003 14:50:34 +0000
Links: << >>  << T >>  << A >>
I know that for Virtex, Virtex-E, and Spartan-II devices, TAP controller 
is held in reset state when PROG pin is low. This results that JTAG 
chain cannot be used then.
This was not the case for older devices (Spartan).
Anybody knows how what's the situation in newer devices (I'm 
particularly curious about Virtex II )?
Thanks.

--
Robert


Article: 62474
Subject: Re: Hit Logic
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Thu, 30 Oct 2003 15:21:15 -0000
Links: << >>  << T >>  << A >>
"Vazquez" <andres.vazquez@gmx.de> wrote in message
news:eee19a7a.0310300536.40db93bb@posting.google.com...

> How can I check with few ressources need (Altera Cyclone device)
> if there is one or more positions with '1'
> within a 32bit-vector (in this case a signal hit='1'
> should be the result)?

It should be OK simply to write the obvious VHDL or Verilog:

....

reg [31:0] hits;
wire hit;
assign hit = (hits != 0);

....

hit <= '1' when hits = (hits'range => '0') else '0';

....

Most synthesis tools will make a fair job of
constructing a nice tree of OR gates from this code,
or else use the carry-chain logic if that can be done.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.






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