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Here is a simple explanation: In any conventional flip-flop the asynchronous CLEAR input clears both the master and the slave directly and permanently as long as CLEAR is active. The synchronous RESET is just another (overriding ) input to the logic driving the D input. All behavior can be deduced from these simple facts Peter Alfke, Xilinx ApplicationsArticle: 79051
Marco wrote: > I should send text to a parallel printer. > > What is a centronics interface? > > See http://www.fapo.com/ieee1284.htm Best Regards, Roel > "Roel" <electronics_designer@hotmail.com> wrote in message > news:cuglno$51a$1@news2.zwoll1.ov.home.nl... > >>Marco wrote: >> >>>Is it possible? >>> >>> >> >>It's very simple in case of a printer having a centronics interface. >>Even graphics can be done easily after sending the right commands. >> >>In case of a USB printer you will need a USB host. Implementing that in >>an FPGA will be much more difficult, so buy an old fashion HP500 Deskjet >>from Ebay and use that one (: >> >>Best Regards, >>Roel >> >> > > >Article: 79052
Thanks folks. Hal, I understand at the purpose behind synchronizing the reset. I am curious to find out what goes on inside the flip-flop that does not cause it go metastable when the d input does not change but the reset changes. Thanks.Article: 79053
Phil, This would be a bug in XST. It would be helpful to submit it to them as such. Cheers, Jim > I'm trying to use the proposed IEEE.fixed_pkg (fixed-point math package) > available here: > > http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html > > The simulator doesn't complain (GHDL in this case), but ISE doesn't seem > to like the negative values in ranges, like: > > variable exp_value_fp : ufixed( 0 downto -17); > > I get this message: > > ERROR:Xst:1548 - c:/phil/vhdl/svm/../csvm.vhd line 60: Negative range in > type of signal <exp_value_fp> is not supported. > > 1) does fixed_pkg work with other synthesis tools? > 2) Suggestions for other alternatives to fixed_pkg that might work with > ISE? > > > Phil -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 79054
So let's take this slowly: You apply asynchronous reset, which forces both latches to 0. There is no metastability as long as CLEAR is active. Then you take away CLEAR asynchronously with repect to the clock. Let's assume the D input is a 1 (if it were a 0, we would not have this dicussion) Both latches are 0 while CLEAR is active,, but if CLEAR goes away right before the clock rising edge, the 1 on D might sneak in and set the master in a metastable way. After the rising clock edge, the master now drives the slave. That means you see a metastable (unbounded) 1 on the slave output Q. This happens only when the CLEAR goes inactive right before the rising clock edge, and only while D is 1. (I had this problem once in a FIFO synchronizer, and I solved it by using CLEAR to drive the D input in such a way that the Low on D appears before CLEAR goes Low= inactive. A simple inverter or buffer does the trick, depending on the chosen polarities.) Peter Alfke, Xilinx ApplicationsArticle: 79055
Other things to consider are configuration instances. I have tripped myself up this way when I didn't complete all my configuration definitions before trying the simulation.... But once I had them, I could use the same testbench for behavioral, post-synthesis, and post-place & route gate simulation. Jason "Thomas Stanka" <usenet_10@stanka-web.de> wrote in message news:372vg7F55n5k0U1@individual.net... > Hi, > > gavbiggs@yahoo.co.uk wrote: >> on to layout the design. Once the layout has been completed I can then >> use the 'Extract' button to create a *.sdf file from which a timing >> file is created. > > At this stage you could also extract a vhdl netlist from Designer. > When using Designer standalone it's the backanotate button pressed and in > the next dialog check the box "generate netlist". > >> The problem occurs when I apply back annotation and try to simulate the >> design with the *.sdf file. I apply the .sdf to QuickHDL by using the >> following in the command prompt: - >> qhsim <design> -sdf<delays> <SDF file> >> This will load up QuickHDL and then errors will occur, The errors are >> as shown below: >> >> ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'INBUF_7' >> ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'MX_3' >> ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'MX_3' >> ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'INBUF_1' >> ERROR: home/biggc/fat.sdf(14): failed to find instance /fat/'OUTBUF_10' >> WARNING: home/biggc/fat.sdf: this file is probably applied to thw wrong >> instance. >> Ignoring subsequent missing instances from this file. >> Failed to find any of the 8 instances from this file. >> The file is probably intended for a lower-level instance, not the >> top-level. > > I saw similar errors when the netlist created by designer and the sdf-file > used some different "encoding". > > Try search the netlist for something like inbuf[7] instead of inbuf_7. > > If I'm right yould configure that in some ways in the Designer software. > >> When the VHDL model has been applied to Actel Designer, the code is >> converted into a circuit, i.e. I/O pad buffers are created etc. this is >> what the errors seem to be referring to as I assume its trying to >> simulate the VHDL code which doesnt contain these instances. Do I need >> to simulate the .edn file (the netlist file) as well as the .sdf file? >> and if so how do I achieve this? > > I never tried Designer V8.x but I never saw Actel Designer inserting > io-buffer, this was done by a tool before (?Silicon Expert?) on edif > level. > > bye Thomas > > -- > Emailantworten bitte an thomas[at]obige_domain. > Usenet_10 ist für Viren und Spam reserviertArticle: 79056
Kedar P. Apte wrote: > Hello All > > I want to learn more about Bus Functional Models > > Please advice me about that. Like > > What a BFM contains...? > code for BFM written in which all languages ...? > Any documents or sites anyone can suggest to read about how to make a BFM > > Kedar A BFM models just the external timing of a device, but not its interal function. Typically a processor interfaces are modeled as BFS to save simulation time. This can be done in any language your simulator understands. Google knows of some documents ... Br, ChrisArticle: 79057
hello I want to map two microblaes into FPGA. Problem is that I do not aware that it is possible to use one LMB and one dual port BRAM for two microblazes so that two microblazes share memory address space. Does anyone have this experience ?Article: 79058
In article <110qsefisopekcf@corp.supernews.com>, Jim Lewis <Jim@SynthWorks.com> wrote: >Phil, >This would be a bug in XST. It would be helpful to >submit it to them as such. > >Cheers, >Jim > >> I'm trying to use the proposed IEEE.fixed_pkg (fixed-point math package) >> available here: >> >> http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html >> >> The simulator doesn't complain (GHDL in this case), but ISE doesn't seem >> to like the negative values in ranges, like: >> >> variable exp_value_fp : ufixed( 0 downto -17); >> >> I get this message: >> >> ERROR:Xst:1548 - c:/phil/vhdl/svm/../csvm.vhd line 60: Negative range in >> type of signal <exp_value_fp> is not supported. >> >> 1) does fixed_pkg work with other synthesis tools? >> 2) Suggestions for other alternatives to fixed_pkg that might work with >> ISE? >> >> I'm using ISE 6.2i, does anyone know if it works in 6.3*? PhilArticle: 79059
In article <420d0c7b$0$19426$8fcfb975@news.wanadoo.fr>,
KCL <kclo4_NO_SPAM_@free.fr> wrote:
>Why do you want to use negative indice?? it's the first time i saw such
>thing
>and so does it work if you use positive indice??
>
That's how the fixed point package (Fixed_pkg) works. It's a proposed
IEEE standard lib. (see:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html )
It's the way to denote that part of the vector is to
the right of the binary point and part is to the left.
so:
signal ufixed4_2 : ufixed(2 downto -1) := "1010";
would mean that ufixed4_2 is set to 2.5 (the binary point is at bit zero
and there are two bits to the right of the binary point and two bits to
the left).
Apparently many other synthesis tools (including Altera's) support this
and my simulator (GHDL in this case) supports it as well. It's been
suggested that ISE's not supporting negative indices is a bug; I tend to
agree that it is, and it's impeding my progress.
Any suggestions for working around this ISE bug?
Phil
>
>"Phil Tomson" <ptkwt@aracnet.com> a écrit dans le message de news:
>cui1g701ovi@enews2.newsguy.com...
>> In article <cufvla02a24@enews2.newsguy.com>,
>> Phil Tomson <ptkwt@aracnet.com> wrote:
>>>
>>>This page:
>>>http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0026_5.html#wp325264
>>>
>>>shows some templates for ROM inference in Spartan3 using Xilinx's ISE
>>>software.
>>>
>>>One of the templates is:
>>> library ieee;
>>> use ieee.std_logic_1164.all;
>>> use ieee.std_logic_unsigned.all;
>>> entity rominfr is
>>> port (
>>> clk : in std_logic;
>>> en : in std_logic;
>>> addr : in std_logic_vector(4 downto 0);
>>> data : out std_logic_vector(3 downto 0)
>>> );
>>> end rominfr;
>>> architecture syn of rominfr is
>>> type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
>>> constant ROM : rom_type :=
>>> ("0001","0010","0011","0100","0101","0110","0111","1000","1001","1010"
>>>,"1011","1100","1101","1110","1111","0001","0010","0011","0100","0101"
>>>,"0110","0111","1000","1001","1010","1011","1100","1101","1110","1111" );
>>> begin
>>> process (clk)
>>> begin
>>> if (clk'event and clk = '1') then
>>> if (en = '1') then
>>> data <= ROM(conv_integer(addr);
>>> end if;
>>> end if;
>>> end process;
>>> end syn;
>>>
>>>
>>>My question is: are they types of the inputs and outputs important for the
>>>software to infer the ROM? For example, could I have:
>>>
>>>
>>> entity rominfr is
>>> port (
>>> clk : in std_logic;
>>> en : in std_logic;
>>> addr : in std_logic_vector(9 downto 0);
>>> data : out ufixed(0 downto -17) -- ufixed is fixed point
>>> --type from:
>>> --http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html
>>> );
>>> end rominfr;
>>>
>>>Would the ROM still be inferred because I didn't use std_logic_vector on
>>>the data output? Just wondering how strict the template must be adhered
>>>to.
>>>
>>>
>>>There are conversion routines to go to/from std_logic_vector<=>ufixed,
>>>however I'd prefer to keep the output of the ROM in ufixed format if
>>>possible.
>>>
>>
>> FYI: the line:
>> data : out ufixed(0 downto -17)
>>
>> Causes the following error:
>> ERROR:Xst:1548 - c:/phil/vhdl/svm/../lookuptable.vhd line 13: Negative
>> range in type of signal <data> is not supported.
>>
>> So looks like you can't use a ufixed (with negative indices ) in a port
>> signal, anyway.
>>
>> Phil
>
>
Article: 79060I have read about Centronics ad its phase transition. I have read also EPP and ECP. I should implement a OPB Slave peripheral to print text. Could you tell me where I can find other information about Centronics, such as signal input and output? Many Thanks Marco "Roel" <electronics_designer@hotmail.com> wrote in message news:cujejn$hj1$1@news5.zwoll1.ov.home.nl... > Marco wrote: > > I should send text to a parallel printer. > > > > What is a centronics interface? > > > > > > See http://www.fapo.com/ieee1284.htm > > Best Regards, > Roel > > > > "Roel" <electronics_designer@hotmail.com> wrote in message > > news:cuglno$51a$1@news2.zwoll1.ov.home.nl... > > > >>Marco wrote: > >> > >>>Is it possible? > >>> > >>> > >> > >>It's very simple in case of a printer having a centronics interface. > >>Even graphics can be done easily after sending the right commands. > >> > >>In case of a USB printer you will need a USB host. Implementing that in > >>an FPGA will be much more difficult, so buy an old fashion HP500 Deskjet > >>from Ebay and use that one (: > >> > >>Best Regards, > >>Roel > >> > >> > > > > > >Article: 79061
Hi I am using Xilinx ISE6.0i to program the XPLA3 CPLD. Here is the UCF file statement I found in the web: NET "option<0>" LOC = "S:PIN5"; What is the exact meaning of it? Does it mean "Locking option<0> to PIN5 and Setting it to 1"? If option<0> is an output signal. what dose the "reset/set" resulting to? Thanks, -ZimmerArticle: 79062
If not, how to reset/set a pin at meantime lock it in a UCF statement? Thanks,Article: 79063
Tullio Grassi wrote: > Hi, > > can the MGT of Virtex-4FX talk to the > MGT of Virtex-2Pro (XC2VPX) ? > Any experience or problems ? Howdy Tullio, The FX parts with MGT's haven't even been released to engineering (or early) sample yet, so nobody is going to have experience with them yet except Xilinx. Regardless, there should be no problems getting the MGT's of the two parts (or most any other devices with a SERDES, including Altera's Stratix GX) talking to each other, provided you choose a bit rate that is supported by both devices. For example, make sure to have a -7 speed-grade V2Pro if you want to do 3.125 Gbps. Have fun, MarcArticle: 79064
Announcement ------------ Samplify Systems announces the availability of Samplify for Windows, a new PC compression application that demonstrates Samplify's unique lossless and lossy compression capabilities for sampled (numerical) data, such as samples from A/D (or for D/A) converters. Samplify for Windows compresses at 10+ Msamp/sec on a 2 GHz Pentium and achieves 2:1 compression on many bandlimited signals, regardless of center frequency. Samplify for Windows demonstrates the performance of Samplify's compression engine, which will be available in FPGAs and DSP chips in 2005. Samplify for Windows is available for free (full functionality during a 30-day evaluation) and as shareware ($49.95) from http://www.samplify.com/page8.html. Target applications include signal capture boards, signal generator cards, medical instruments, test and measurement equipment, wireless sensor networks, signal transfer and storage networks, and high-speed A/D and D/A converters. Try Samplify for Windows on your PC, to see how well your signals samplify (compress). If you like Samplify's compression results (at 10+ Msamp/sec on your PC), contact Samplify Systems to get identical results using your FPGA or DSP, at sampling rates up to 100 Msamp/sec. Wanted: signals to compress --------------------------- Samplify Systems is looking for signals to compress: sampled data from A/D (or for D/A) converters, streams of numbers, matrices, etc. that aren't currently being compressed, to determine how well Samplify compresses such signals. Samplify will compress "traditional" sampled data, such as speech (PCM, 8 ksamp/sec), audio (WAV, 48 ksamp/sec), and image (TIFF) files, but such signals already have effective compression solutions (ADPCM, MP3, WMA, JPEG, etc). Instead, Samplify is targeting high-speed sampled data signals that haven't been compressed (or compressible) before. Samplify compresses streams of numbers (integers) that represent real-world signals, signals for which no effective compression solutions have been available. If the following bullets describe your signals and/or systems, please try Samplify for Windows: =B7 You would save money by reducing signal storage or network traffic bottlenecks =B7 You've never tried to compress your signals before =B7 You work with bandlimited (oversampled) signals, where the sampling rate is at least two times higher than your signal bandwidth =B7 Your sampling rates are reasonably high (5+ Msamp/sec) =B7 You system already contains an FPGA (Xilinx, Altera) or DSP (TI, ADI, Freescale) in the signal processing path, or you are planning to use FPGAs or DSPs After trying Samplify for Windows, please send us an e-mail (info@samplify.com) describing your signals, and let us know what kind of compression ratio or rate-distortion curve you got using Samplify for Windows, and whether you plan to use lossless (SignalZIP) or lossy (Samplify, NoiseTrak) compression. More information ---------------- For more information about Samplify's new compression technologies, please visit: Home page: http://www.samplify.com Download Samplify for Windows: http://www.samplify.com/page8.html, or from http://www.hotdownloads.com/index.php3?job=3D3&id=3D71284 Electronic Design magazine article (20 Sep 2004 issue) about Samplify: http://www.elecdesign.com/Articles/Print.cfm?ArticleID=3D8691 Samplify FAQ (white paper): http://www.samplify.com/page6.html Samplify for Windows manual: http://www.samplify.com/page6.html FPGA products (Xilinx, Altera): http://www.samplify.com/page4.html DSP products (TI, ADI, Freescale): http://www.samplify.com/page5.htmlArticle: 79065
Hi, I need help for a Cypress programmable clock CY27EE16, maybe someone has already used this PLL here. This clock has a PLL, dividers, 6 outputs, 9 x 256 bytes of EEPROM, 256 bytes SRAM, and an I2C interface. There are 2 programmable I2C address, one for the 8 x 256 bytes EEPROM, and a 2nd for 256 bytes EEPROM/SRAM clock registers. The default I2C address are $40 to $47 for EEPROM and $68-$69 for the clock. My problem, after wrong I2C sequence, that now I can see I2C devices at $78-$7F and I can see the 16 first bytes of each 256 bytes to $FF. So I see only the EEPROM bytes and this bytes are software write protected by a clock register. Where is the clock registers ? Normally also at $7E-$7F, there are a conflict. I have tried to remove WP without succes, I'am not sure than I can write to the clock registers. Soneone has some experiance with I2C address conflict with this chip ? Thanks for your help... Regards, Didier. -- Didier MEQUIGNON Aniplayer download: http://aniplay.atari.org CT60 package download: http://ct60conf.atari.orgArticle: 79066
Hi everyone, I would like to count very fast (100MHz) using an 19-bit counter in spartan 3 - any ideas how to make such a fast counter! One idea is to use the Chinese Remainder Theorem to count, but that make's a "hit-rate" of only 60% or so, if the timing is restricted. The other Idea is to make a pipelined counter, but that make's the whole design a lot more complicated. Any other Ideas? I use the Spartan 3 digilent starter board! Thanks in advance! / PrebenArticle: 79067
Preben, have you done the timing analysis on a straightforward implementation? I have run longer counters at higher frequency in Spartan 3...There is a built-in carry structure! Is your counter loadable? if not, your counter might be implemented as a ripple ( or a partially-ripple) counter, then you can count several hundred MHz ( use the Q as clock source for the next slice, or next group of 4 flip-flops.) If you do this, you have to wait out the ripple delay before you use or decode the counter output. Thre are many ways to achieve 100 MHz, or 2x, or 4x that performance, it all depends on your real requirements. Peter Alfke, Xilinx Applications.Article: 79068
"Preben" <64bitNOspamNO@mailme.dk> wrote in message news:420fab6f$0$12714$edfadb0f@dread14.news.tele.dk... > Hi everyone, > > I would like to count very fast (100MHz) using an 19-bit counter in > spartan 3 - any ideas how to make such a fast counter! > One idea is to use the Chinese Remainder Theorem to count, but that make's > a "hit-rate" of only 60% or so, if the timing is restricted. > > The other Idea is to make a pipelined counter, but that make's the whole > design a lot more complicated. > !00 MHz does not sound that fast for a Spartan III. Did you try a HDL synthesys and P&R with time constraint? > Any other Ideas? Perhaps an 8 bit prescaler with a pipelined clock enable to an 11 bit counter. 20 bit counter using block RAM http://www.synplicity.com/literature/syndicated/pdf/spartan_3_v3_i3.pdf Have fun -Newman > > > I use the Spartan 3 digilent starter board! > > > Thanks in advance! > > / PrebenArticle: 79069
Hello, I'm trying since yesterday to interconnect the opencore mac to a microblaze design. After several problems solved, I'm stuck. The "Generate netlist now works fine" but When I try to "Generate bitstream", I have three errors from NgdBuild : ERROR:NgdBuild:604 - logical block 'wb2opb_0/wb2opb_0' with type 'wb2opb' could not be resolved. A Pin name mispelling can cause this, a missing edif or ngc file, or the mispelling of a type name. Symbol 'wb2opb' is not supported in target 'spartan 3'. ERROR:NgdBuild:604 - logical block 'opb2wb_0/opb2wb_0' with type 'opb2wb' could not be resolved. A Pin name mispelling can cause this, a missing edif or ngc file, or the mispelling of a type name. Symbol 'opb2wb' is not supported in target 'spartan 3'. ERROR:NgdBuild:604 - logical block 'wb_ethermac_0/wb_ethermac_0/maccore' with type 'eth_top' could not be resolved. A Pin name mispelling can cause this, a missing edif or ngc file, or the mispelling of a type name. Symbol 'eth_top' is not supported in target 'spartan 3'. For the wb_ethermac core, I've created a file that includes the eth_top of the ethernet mac core on opencore and present the interface to the outside world. I've done this as a ISE project then I synthetized it to have a .ngc file (because I have both VHDL & Verilog there) then I created an IP from this netfile and my vhdl top file. Any one has a clue on what to do ? Has anyone make this work ? (I'm using ISE/EDK 6.3) Thanks, SylvainArticle: 79070
"Preben" <64bitNOspamNO@mailme.dk> schrieb im Newsbeitrag news:420fab6f$0$12714$edfadb0f@dread14.news.tele.dk... > Hi everyone, > > I would like to count very fast (100MHz) using an 19-bit counter in > spartan 3 - any ideas how to make such a fast counter! Just a straight forward approach. Been there, done this recently. It was a 32 Bit counter, running at 130 MHz and still having some timing margin left. Regards FalkArticle: 79071
Peter, Hal and all. I was really interested in analysing this at the transistor level which I have now thanks to your inputs and other vlsi references that I looked up. Thanks. -sanjayArticle: 79072
Preben <64bitNOspamNO@mailme.dk> wrote: > Hi everyone, > I would like to count very fast (100MHz) using an 19-bit counter in > spartan 3 - any ideas how to make such a fast counter! > One idea is to use the Chinese Remainder Theorem to count, but that > make's a "hit-rate" of only 60% or so, if the timing is restricted. Spartan 3, 100MHz and ... fast? I think you are kidding. Did you try to implement the counter? I guess it will run much faster Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 79073
Hello All,
I have been simulating the FIFO code shown below with good success.
I have tested the behaviour under ModelSim waveform, where I send
three fifowren pulses, followed by three fiforden pulses, and a sequence
of numbers at the fifoin port, to determine if the right outputs pop off the
FIFO at the right time. I also test the FIFO in larger projects.
However. After generating Place and Route files, I ran the same
waveform testbed, same vectors, and got 0 outputs. No setup
warnings. What is wrong, or how do I find out what is wrong?
Thanks in Advance,
Brad Smallridge
b r a d @ a i v i s i o n . c o m
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity fifo36 is
port(
clk : in std_logic;
reset : in std_logic;
fifowren : in std_logic;
fiforden : in std_logic;
fifooe : in std_logic;
fifoin : in std_logic_vector(35 downto 0);
fifoout: out std_logic_vector(35 downto 0)
);
end fifo36;
architecture Behavioral of fifo36 is
component RAMB16_S36_S36
generic (
WRITE_MODE_A : string := "READ_FIRST";
WRITE_MODE_B : string := "READ_FIRST";
INIT_A : bit_vector := X"000000000";
SRVAL_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
INITP_00 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000"
);
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in STD_logic;
ENB : in STD_logic;
WEA : in STD_logic;
WEB : in STD_logic;
SSRA : in STD_logic;
SSRB : in STD_logic;
CLKA : in STD_logic;
CLKB : in STD_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal fifowraddr : std_logic_vector(8 downto 0);
signal fifordaddr : std_logic_vector(8 downto 0);
begin
bram00 : RAMB16_S36_S36
port map (
DIA => fifoin(31 downto 0),
DIB => (others=>'0'),
DIPA => fifoin(35 downto 32),
DIPB => (others=>'0'),
ENA => '1',
ENB => fifooe,
WEA => fifowren,
WEB => '0',
SSRA => '0',
SSRB => '0',
CLKA => clk,
CLKB => clk,
ADDRA => fifowraddr,
ADDRB => fifordaddr,
DOA => open,
DOB => fifoout(31 downto 0),
DOPA => open,
DOPB => fifoout(35 downto 32)
);
fifocnt: process(clk)
begin
if(clk'event and clk='1') then
if(reset='1') then
fifowraddr<=(others=>'0');
fifordaddr<=(others=>'0');
else
if(fifowren='1') then
fifowraddr<=fifowraddr+1;
end if;
if(fiforden='1') then
fifordaddr<=fifordaddr+1;
end if;
end if;
end if;
end process;
end Behavioral;
Article: 79074
Hello:
I am growing old trying to connect a simple peripheral to the user register
ipif. I first created the template using the create/import peripheral
wizard. If I try to implement any of my components in the user_logic.vhd
file, that were derived from vhdl functional models from schematics I get
errors like below. No matter how simple the schematic.
ERROR:NgdBuild:466 - output pad net 'scda<2>' has illegal connection.
Possible
pins causing this are:
pin I0 on block scda<2>_rt with type LUT1
Any help would be greatly appreciated.
Fayette
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