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Messages from 85575

Article: 85575
Subject: Re: computer upgrade time.
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Sat, 11 Jun 2005 03:43:20 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <pdqqe.615$FP2.225@lakeread03>,
Ray Andraka  <ray@andraka.com> wrote:
>Hmm, water cooling might let me put a radiator in another room. 

Actually, you can just have the radioator on the case.  Since the
radiator is significantly larger, you can use a much bigger, slower,
high volume but low speed fan which is generally quieter.

I forgot abotu water cooling in my earlier post.  Yeah, if you want
quiet and power, you're gonna have to water cool it and probably
either build it yourself or pay throguh the nose for a L337 WA73R
C00L3D N1NJA GAM1NG RIG.
-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu

Article: 85576
Subject: Selecting FPGA synthesis, place and route and simulation tools
From: rod.beresford@gmail.com
Date: 10 Jun 2005 22:01:48 -0700
Links: << >>  << T >>  << A >>
Hi,

We're considering using the Xilinx Spartan FPGA series. We plan to use
the free Web ISE tools for doing our verilog synthesis, place and route
and simulation. I have several questions about this. I'm  assuming that
synthesis and pnr are well taken care off by the Web ISE. However, I
noticed simulation might have to be done using ModelSim and rather than
being free it is provided only with time limited licensing. Are there
alternatives to ModelSim? We used to use Cadence's ncsim but we will
not have funding to use it anymore. We were using verilog and C
testbenches through PLI to get coverage in our simulations. I'd like to
hear about what other people and teams have experienced in this area.
This work is not-for-profit.

Thanks,
R. Beresford


Article: 85577
Subject: Re: computer upgrade time.
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sat, 11 Jun 2005 18:29:15 +1200
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> Time has come for a computer upgrade (I'm currently using a dual Athlon 
> 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, 
> matrox dual head video with a pair of 19" monitors), but I haven't kept 
> up at all with the computer market.  I'm wondering what people are using 
> these days for high end designs (for simulation and PAR especially).  
> I'd like something that doesn't sound like a vacuum cleaner and heat the 
> room like a space heater this time around too, perhaps I need to 
> consider liquid cooling?  ANy comments would be appreciated.  Yes, I 
> admit I am being lazy.

  Dual core chips are the latest 'hot thing', so you might want to track 
that, and decide if they are mature enough to move to, or wait a few 
months. ie right now, with both 64 bit and Dual core as recent crests, 
is not an ideal time to expect rock solid systems. If you do not HAVE to 
move asap, I'd wait a few months.
  AMD do claim to be on schedule for 65nm in 2006 :)
-jg



Article: 85578
Subject: FPGA or SSE2 ?
From: "John" <john@fpgasoc.org>
Date: 10 Jun 2005 23:35:05 -0700
Links: << >>  << T >>  << A >>
Hi,

I am trying to decide which of these two technologies to invest a good
amount of time into, and I have not found much of use on the net -
there are lots of figures, but comparing apples to oranges is not much
use :(

What I am looking to do is probably a typical use for SSE2, basically
image processing and compression (DCT, motion estimation, others). The
problem is trying to find comparisons between high-bandwidth (eg:
Hyper-transport or DDR DIMM interface) FPGA implementations of this
sort of operation, and SSE2.

If I have to put the FPGA onto a PCI bus, I very much doubt it could
possibly compete, but if it was possible to integrate into the
Northbridge, it may be a whole new ball game.

I've run the testbench for Intel's SSE libraries, and it seems to be
pretty stable at ~370 clocks/pixel when doing a 720x480 '422' baseline
JPEG at 75% quality. This gives 0.04 secs per image at 3.6GHz. What I'm
trying to figure out is (assuming I had the data bandwidth via a
low-latency connection) whether I'd be able to better that using an
FPGA. Any takers ?

I can find figures for parts of the JPEG algorithm (eg: Xilinx have an
8x8 DCT that will push 140 Mpixels/sec if pipelined), which is a large
part of the problem, but I'd like to see if the RLE/Huffmann encoding
took time as well (I'm aware it could/should be pipelined after the DCT
- something the P4 can't do - I'm just not sure how much extra overhead
it would be)

So, anyone got any figures for a best-case FPGA implementation ? They'd
be much appreciated :)

John


Article: 85579
Subject: Re: FPGA or SSE2 ?
From: Sylvain Munaut <com.246tNt@tnt>
Date: Sat, 11 Jun 2005 09:05:21 +0200
Links: << >>  << T >>  << A >>
Hi John

John wrote:
> I've run the testbench for Intel's SSE libraries, and it seems to be
> pretty stable at ~370 clocks/pixel when doing a 720x480 '422' baseline
> JPEG at 75% quality. This gives 0.04 secs per image at 3.6GHz. What I'm
> trying to figure out is (assuming I had the data bandwidth via a
> low-latency connection) whether I'd be able to better that using an
> FPGA. Any takers ?
> 
> I can find figures for parts of the JPEG algorithm (eg: Xilinx have an
> 8x8 DCT that will push 140 Mpixels/sec if pipelined), which is a large
> part of the problem, but I'd like to see if the RLE/Huffmann encoding
> took time as well (I'm aware it could/should be pipelined after the DCT
> - something the P4 can't do - I'm just not sure how much extra overhead
> it would be)
> 
> So, anyone got any figures for a best-case FPGA implementation ? They'd
> be much appreciated :)

I've done a simplified JPEG (same principle but more specialized)
encoder that only took b/w (but color is basically 3 times that + color
space conversion and different resolution and in a FPGA, you can just
duplicate the hw) and it took about 1500 LE in a basic Altera Cyclone
and it runned at about 100Mhz, needing 2 clock / pixels. I didn't try to
optimize it much since the first implementation met the constraint I
needed. So if you duplicate the hw for the other color component, the
figure would be 50Mpixels/s => 144 fps (0.007 sec par image).

So I'd say yes, you can easily beat the P4 for such a dedicated task.
The problem as you stated is to get the data in and out. 50Mpixels par
second at 24bits color is over the PCI peak rate (133Mbyte/s and it's
never reached).

RLE is basically a counter with a barrel shifter. Huffman, a simple
encoding/decoding table. Both can be done pretty efficiently.


	Sylvain

Article: 85580
Subject: Re: pcb layers on BGAs Spartan-3
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 11 Jun 2005 09:25:17 +0200
Links: << >>  << T >>  << A >>

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schrieb im
Newsbeitrag news:oibka1p30g1hs69add4jamu01mi9pc8de2@4ax.com...

> I blame Johnson for all this obsession with "return currents."

ROFL.
You got me!

Regards
Falk






Article: 85581
Subject: Re: pcb layers on BGAs Spartan-3
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 11 Jun 2005 09:29:28 +0200
Links: << >>  << T >>  << A >>

"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag
news:42a9fdac$0$346$ba620e4c@news.skynet.be...

>
> Take a look at
> http://www.xilinx.com/bvdocs/appnotes/xapp157.pdf
> For the FG256 they only show two signal layers.

OK, so this proves the old suggestion.
"Use your head before opening your mouth".
;-)

Regards
Falk





Article: 85582
Subject: Re: X-Fest devkit order leadtimes & software silliness....
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 11 Jun 2005 09:41:55 +0200
Links: << >>  << T >>  << A >>
"MK" <nospam.please@here.ever> schrieb im Newsbeitrag
news:d8ccr7$hg9$1$8300dec7@news.demon.co.uk...
>
> "Mike Harrison" <mike@whitewing.co.uk> wrote in message
> news:cenia1pc7q3ptsc4rrhts8phl8085g2smh@4ax.com...
> > Wondering if anyone else has experienced this....
> > After the recent X-Fest seminar in Cambridge UK, I ordered the Memex
FPGA
> Design Starter kit on the
> > x-fest special offer, as it was a cheap way to get the BaseX software.
> > I'm now told that the kit won't be shipped til mid-August. I have no
> problem with that as I don't
> > need the hardware immediately & already have the S3 starter kit..
> >
> > However when I contacted Memec to ask if they could ship the software
> immediately (which
> > Incidentally they charged my card for 2 weeks ago), they claimed that
this
> wasn't possible, and when
> > I pressed them they said they'd ask Xilinx but were fairly sure they
> wouldn't do it.
> >
> > I'm sure I'm not the only one who ordered this offer as it was a very
good
> deal compared to the
> > normal price - has anyone else had any joy getting the software out of
> them ahead of the hardware ?
> >
> > Seems like a pretty daft situation.....
>
>
> Hi Mike,
>
> I haven't ordered mine yet (still in shock at the 8-10 weeks delivery).
I'm
> fairly horrified that they charged your card before they had the stuff to
> send.
>
> I'm going to copy this to the Xilinx Apps manager and see what happens.
>
> On past experience (are you there Xilinx !!) it won't be much - I'm still
> waiting for price and delivery from Memec re S3E parts from an enquiry I
> made on 20th May.
>
> Michael Kellett
>

It was VERY surprising to see Memect to offer S3E kits, but all their
leaflets with pictures of the S3E kits where made with 'blurred' image of
the Xilinx S3E chips so it was quite clear the photos where FAKED, eg they
did use dummy packages for photo shooting. So for me it was also clear that
there is no hope to expect actual deliveries before late august/september.
business as usual (for Memec) announce, charge and let customer to wait for
6+ months.

If I would have any trust that Memec can deliver (orderdable products from
their web shop) I would have ordered the S3E kit rigth away, but knowing the
past I did not bother.

Antti




Article: 85583
Subject: Re: computer upgrade time.
From: Jim George <send_no_spam_to_jimgeorge@gmail.com>
Date: Sat, 11 Jun 2005 01:43:08 -0600
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> Time has come for a computer upgrade (I'm currently using a dual Athlon 
> 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, 
> matrox dual head video with a pair of 19" monitors), but I haven't kept 
> up at all with the computer market.  I'm wondering what people are using 
> these days for high end designs (for simulation and PAR especially).  
> I'd like something that doesn't sound like a vacuum cleaner and heat the 
> room like a space heater this time around too, perhaps I need to 
> consider liquid cooling?  ANy comments would be appreciated.  Yes, I 
> admit I am being lazy.
> 

My present FPGA dev "system" is a Dell P4 2GHz laptop (512 MB RAM) with 
a crummy 5400 rpm drive. A 60% utilized XC2V1000 with incremental P&R 
takes about 3-4 minutes. While par.exe is running, nothing else works 
unless I reduce par's priority to "Below Normal".

I will be getting a new one in a week or so, which has an AMD Athlon64 
3800, 2GB memory and two Seagate Baraccuda 80 GB drives in software 
RAID. I dont know why, but I'm also getting a Radeon X800XT... oh well, 
I dont have to pay for it anyway!

My home computer is an Athlon64 3000 (Winchester core), 1GB RAM. The 
idle CPU temp is between 38 and 40 degrees, depending on the ambient 
temp. On-load temp is 44-46 degrees. I use an inexpensive heatsink with 
this CPU, and there's no problem. There are many fans (front fans 
included), but I use SpeedFan to adjust their speed automatically. I 
dont know how true this is, but I have heard that using an Al. chassis 
will tend to keep your box cooler. Here is a link to one such (pricey) 
chassis: http://www.newegg.com/Product/Product.asp?Item=N82E16811112051

-Jim

Article: 85584
Subject: Re: computer upgrade time.
From: "Dave Garnett" <dave.garnett@metapurple.co.uk>
Date: Sat, 11 Jun 2005 08:55:21 +0100
Links: << >>  << T >>  << A >>

"Ray Andraka" <ray@andraka.com> wrote in message 
news:HFiqe.559$FP2.71@lakeread03...
> Time has come for a computer upgrade (I'm currently using a dual Athlon 
> 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, matrox 
> dual head video with a pair of 19" monitors), but I haven't kept up at all 
> with the computer market.  I'm wondering what people are using these days 
> for high end designs (for simulation and PAR especially).  I'd like 
> something that doesn't sound like a vacuum cleaner and heat the room like 
> a space heater this time around too, perhaps I need to consider liquid 
> cooling?  ANy comments would be appreciated.  Yes, I admit I am being 
> lazy.
>

Just bought a 3.6 G P4 system. My supplier provides a 'hush kit' - a very 
large fan on the cpu, a big extractor fan for the case, and lots of 
adhesive/lead stuff stuck on panels to stop them resonating. The cleverest 
thing is a big inlet and duct on the case side - this ensures that the 
incoming air is directed to the right place on the motherboard etc. Serial 
ATA 7200 Maxtors are reasonably quiet - at least they don't have that 
annoying whine. The overall result is an acceptable 'white' noise (at a cost 
of 50 pounds). The next step would be to change the fan on the graphics card 
...




 Posted Via Nuthinbutnews.Com Premium Usenet Newsgroup Services
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Article: 85585
Subject: Re: computer upgrade time.
From: "Marco" <marcotoschi_no_spam@email.it>
Date: Sat, 11 Jun 2005 10:38:06 +0200
Links: << >>  << T >>  << A >>

"Ray Andraka" <ray@andraka.com> wrote in message 
news:HFiqe.559$FP2.71@lakeread03...
> Time has come for a computer upgrade (I'm currently using a dual Athlon 
> 1.8GHz with 4GB memory and 15000RPM scsi raid array running Win2K, matrox 
> dual head video with a pair of 19" monitors), but I haven't kept up at all 
> with the computer market.  I'm wondering what people are using these days 
> for high end designs (for simulation and PAR especially).  I'd like 
> something that doesn't sound like a vacuum cleaner and heat the room like 
> a space heater this time around too, perhaps I need to consider liquid 
> cooling?  ANy comments would be appreciated.  Yes, I admit I am being 
> lazy.
>
> -- 
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com  http://www.andraka.com
> "They that give up essential liberty to obtain a little temporary safety 
> deserve neither liberty nor safety."
>                                          -Benjamin Franklin, 1759
>
>

Avoid WaterCooling, it needs a lot of work. I think you are a professionist, 
so you can't loose time to work on your water cooling system.
It needs really lot of time and experiments to configure and tune up a good 
system.
It needs V3 radiators, a cpu waterblock, a chipset waterblock, gpu 
waterblock, hard disk waterblock, a very good pump, or 2-3 pumps, Kilometers 
of tubing, a reservoir, distilled water and anticorrosion kit.

Tubes must be used with series or parallel.

And you could use peltier to cool your cpu, but in this way you need also a 
dedicated power supply.

I have used it when studying at university: lots of troubles... even if my 
processor was overclocked from 1700+ to 2200+ with peltier cooling.

I was obliged to open case 1 time at month to tupe up system... too much 
time...


Instead I suggest:

Thermalright XP-120 for CPU with a quiet 120x120 fan or XP-90

and some fans into case with a system to regulate the amount of volts, 
Sunbeam Rheobus Kit, tipically a range from 5v to 12v, so you could decide 
the amount of noise.

Use those fans to send air out of case, don't use them to send air into 
case. In this way you can avoid that hot air runs inside case without going 
out.


I can also suggest some sites where you can obtain informations:

http://www.overclockers.com section watercooling

http://www.dangerden.com  great products for watercooling kits, in my 
opinion the best.


PS: sorry for my terrible english.

Marco





Article: 85586
Subject: Re: PowerPC crash down
From: Ben Popoola <ben.popoola@REMOVE.recontech.co.uk>
Date: Sat, 11 Jun 2005 09:14:45 GMT
Links: << >>  << T >>  << A >>
Pierre wrote:
> Aurash,
> 
> That seems to be correct
> 
> (on oscilloscope: 1.5 V, 2.5 V and 3.3 V)
> 
> Pierre
> 
> "Aurelian Lazarut" <aurash@xilinx.com> a écrit dans le message de
> news:d83uk0$ps62@cliff.xsj.xilinx.com...
> 
>>Pierre,
>>First I would check the power supply
>>Aurash
> 
> 
> 

What about the current consumption, especially of Vccio?

Article: 85587
Subject: Re: Selecting FPGA synthesis, place and route and simulation tools
From: Peter TB Brett <peter@peter-b.co.uk>
Date: Sat, 11 Jun 2005 10:00:34 GMT
Links: << >>  << T >>  << A >>
rod.beresford@gmail.com writes:

> However, I noticed simulation might have to be done using ModelSim
> and rather than being free it is provided only with time limited
> licensing. Are there alternatives to ModelSim?

Have you looked at iverilog (http://www.icarus.com/eda/verilog/)?

Peter

-- 
E-mail:  peter@peter-b.co.uk
Website: http://www.peter-b.co.uk

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Article: 85588
Subject: Re: FPGAFLASH
From: "Unbeliever" <alfkatz@remove.the.bleedin.obvious.ieee.org>
Date: Sat, 11 Jun 2005 21:04:13 +1000
Links: << >>  << T >>  << A >>

<edick@hotmail.com> wrote in message
news:1118444991.528207.300710@o13g2000cwo.googlegroups.com...
> Some years ago, a XILINX project was "Designed by Jens Hildebrandt,
> University of Rostock/Germany, 2002", as it says.  The purpose of this
> piece of work was to enable one, by means of a CPLD, to program a FLASH
> memory via an ASYNC serial link, and, after changing the state of RTS,
> to use that FLASH memory to provide the bitstream and controls to
> program a XILINX FPGA.
>
> Unfortunately, the portion of this that I received did not specify
> anything about the external interface.
>
> Has anyone had experience with this project, to the extent that it's
> been implemented?  If so, can you advise me as to how this scheme can
> be implemented in hardware?
>
> thanks in advance
>
Haven't seen this particular APP, but I've used Xilinx's XAPP 800 (with a
95XX series instead of a CoolRunner, up & running in no time).  Worth a
look, though it isn't programmed serially but rather with the Parallel IV
cable.

Cheers,
Alf



Article: 85589
Subject: Re: Selecting FPGA synthesis, place and route and simulation tools
From: Mike Harrison <mike@whitewing.co.uk>
Date: Sat, 11 Jun 2005 12:43:32 GMT
Links: << >>  << T >>  << A >>
On 10 Jun 2005 22:01:48 -0700, rod.beresford@gmail.com wrote:

>Hi,
>
>We're considering using the Xilinx Spartan FPGA series. We plan to use
>the free Web ISE tools for doing our verilog synthesis, place and route
>and simulation. I have several questions about this. I'm  assuming that
>synthesis and pnr are well taken care off by the Web ISE. However, I
>noticed simulation might have to be done using ModelSim and rather than
>being free it is provided only with time limited licensing. Are there
>alternatives to ModelSim? We used to use Cadence's ncsim but we will
>not have funding to use it anymore. We were using verilog and C
>testbenches through PLI to get coverage in our simulations. I'd like to
>hear about what other people and teams have experienced in this area.
>This work is not-for-profit.
>
>Thanks,
>R. Beresford

The Modelsim supplied with Webpack is not time-limited : 

>From the Webpack FAQ : 
http://www.xilinx.com/ise/devsys_feature_guide.pdf
"The limits for Modelsim MXE-III Starter are 10,000 lines of debuggable code. Beyond this limit, the
processing begins to slow down, but does not stop. The usefulness of this software is going to
depend on coding style and type of simulation (either functional or timing) that is desired."

Xilinx have introduced their own simulator in ISE 7 but I don't think it comes with Webpack (yet?)



Article: 85590
Subject: Re: Selecting FPGA synthesis, place and route and simulation tools
From: rod.beresford@gmail.com
Date: 11 Jun 2005 07:05:12 -0700
Links: << >>  << T >>  << A >>
Peter TB Brett wrote:
> rod.beresford@gmail.com writes:
>
> > However, I noticed simulation might have to be done using ModelSim
> > and rather than being free it is provided only with time limited
> > licensing. Are there alternatives to ModelSim?
>
> Have you looked at iverilog (http://www.icarus.com/eda/verilog/)?
>

Yes, I had heard about it and the GEDA suite. The general perception I
got was that it's not yet ready for prime time. Is that a fair
assesment? If there are people using it for real projects and able to
integrate it with PLI testbenches and such, then please by all means
let me know. Thanks.


Article: 85591
Subject: Re: X-Fest devkit order leadtimes & software silliness....
From: Lukasz Salwinski <lukasz@ucla.edu>
Date: Sat, 11 Jun 2005 07:36:13 -0700
Links: << >>  << T >>  << A >>
Mike Harrison wrote:
> On Fri, 10 Jun 2005 12:07:31 +0100, "John Adair"
> <removethisthenleavejea@replacewithcompanyname.co.uk> wrote:
> 
> 
>>If you just need synthesis, p&r, then ISE Webpack can be used as a stop gap 
>>for Spartan-3 devices up to XC3S1500.
> 
> 
> That's what I'm using, but I'm told that BlockRam is difficult to 
 > use if you don't have the CoreGen part which doesn't come with Webpack
> - not looked into this yet though. 

uh ? which part is supposed to be hard ? in the very worst case
one's got to write a tiny script to generate INIT_xx content to
preinitalize BlockRAM contents... otherwise everything's there -
including instantiation templates ready to cut and paste from
Language Templates

lukasz
(happily using tons of BlockRAMs without even touching coregen)

Article: 85592
Subject: Re: initializing fifo pointers to simulate overflow
From: "fpgabuilder" <fpgabuilder-news@yahoo.com>
Date: 11 Jun 2005 08:50:37 -0700
Links: << >>  << T >>  << A >>
Thanks Berty.
It confirms my suspicions about starting off the pointers at some
value.  And good point about running the clock at higher ppm to test
for the overflow and underflows.

-sanjay


Article: 85593
Subject: Re: FPGA or SSE2 ?
From: "John" <john@fpgasoc.org>
Date: 11 Jun 2005 09:21:07 -0700
Links: << >>  << T >>  << A >>
Thanks a lot Sylvain - that's exactly the sort of comparison I needed
:)  I won't just be doing JPEG, but it's pretty typical of the sort of
code so it's a good benchmark, and a speedup of almost 6x is well worth
investigation :)

John


Article: 85594
Subject: Re: Selecting FPGA synthesis, place and route and simulation tools
From: Peter TB Brett <peter@peter-b.co.uk>
Date: Sat, 11 Jun 2005 17:22:40 GMT
Links: << >>  << T >>  << A >>
rod.beresford@gmail.com writes:

> Yes, I had heard about it and the GEDA suite. The general perception I
> got was that it's not yet ready for prime time. Is that a fair
> assesment?

Well, I just used gschem/gnetlist for a 700-component board I just had
made (which I'm currently writing the FPGA cores for).

We use VHDL in our shop, so I can't help out telling you about
iverilog.  How about you just download it and try it out?

Peter Brett

-- 
E-mail:  peter@peter-b.co.uk
Website: http://www.peter-b.co.uk

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Article: 85595
Subject: Re: computer upgrade time.
From: "JJ" <johnjakson@yahoo.com>
Date: 11 Jun 2005 11:07:07 -0700
Links: << >>  << T >>  << A >>
I keep my xp2400 basically open frame, no case, right next to window,
layed flat with variable fan set to 7v or so till goes just quite but
temp is around 60c with AC on. If AC off, its either more noise or
higher temp unless window is open. The HW temp monitor is always on
next to clock.

I noticed the 300w atx supply with 4pin P4/xp 12v power connector was
also pretty noisy so I downgraded to an older 250w supply that is
almost silent but no 4pin 12v cable. Thats easy, just added a splitter
for that. Not all older PSUs like that. In Taiwan and in Microcenter I
see a $200 fanless PSU, nice hunk of extruded Al case.

The 2 vid cards and the 21,19 inch monitors probaby produce far more
heat to the room though atleast the monitors can spend some time off
and don't make noise.

I am not sure about going to LCD, you would really have to go to 1600
res a big drop from 2000 capable CRTs. But at least in the last yr
prices have dropped noticably on the 1280s and a few 1600 LCDs  are
available that are almost same price I paid for these monitors.

I am almost tempted to try hanging the cpu out of the window in an
appropriate enclosure, send the heat & noise outside in 1 go, but the
monitors will still be warm.

For the future I wait to see how the dual cores Athlon64s are and for a
PCIe dual vid card (matrox perhaps).


johnjakson at usa dot com


Article: 85596
Subject: Synplify vs XST...
From: "Austin Franklin" <austin@dark99room.com>
Date: Sat, 11 Jun 2005 15:39:11 -0400
Links: << >>  << T >>  << A >>
I have not use XST, but it is becoming more attractive.  I have been using
Synplify for many years now, and it works pretty well.  XST has come a long
way, especially now that it appears to have an RTL viewer as well as a
"implementation" (gate level) viewer, which are two features I liked about
Synplify (please correct me if I'm wrong about these features...I believe I
read about them in XCell).  I only do Xilinx work, and I pretty much stick
to Verilog.  I am considering dropping Synplicity and using XST.

What have people's experiences been between XST and Synplify?  Is Synplify
still that much better than the competition, or is XST %95 as good (or
better) than Synplify?

Any comments appreciated.

Regards,

Austin



Article: 85597
Subject: Re: Synplify vs XST...
From: "B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com>
Date: Sat, 11 Jun 2005 17:57:36 -0400
Links: << >>  << T >>  << A >>
On Sat, 11 Jun 2005 15:39:11 -0400, Austin Franklin wrote:

> I have not use XST, but it is becoming more attractive.  I have been using
> Synplify for many years now, and it works pretty well.  XST has come a long
> way, especially now that it appears to have an RTL viewer as well as a
> "implementation" (gate level) viewer, which are two features I liked about
> Synplify (please correct me if I'm wrong about these features...I believe I
> read about them in XCell).  I only do Xilinx work, and I pretty much stick
> to Verilog.  I am considering dropping Synplicity and using XST.
> 
> What have people's experiences been between XST and Synplify?  Is Synplify
> still that much better than the competition, or is XST %95 as good (or
> better) than Synplify?
> 
> Any comments appreciated.
> 
> Regards,
> 
> Austin

I used Synplify for many years but I haven't used it recently. I
switched to XST about a year ago when it got to the good enough
level. XST improves with each release, my gut says that it's pretty close
to Synplify's level at this point.

Article: 85598
Subject: Best Practices for Hardware Designers
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 11 Jun 2005 15:03:31 -0700
Links: << >>  << T >>  << A >>
Hello, I'm looking for some information that describes some of the best
practices or habits for successful electronic design or embedded
design. I'm trying to convince some co-workers that it is important to
document their work and follow standards in their designs. Some of my
co-workers are very fast designers and are respected by their peers,
but in their rush to get the design done they often ignore standards
and don't document their work, such as in their schematics or in their
FPGA code. I feel these habits and behavior actually wastes money, by
that I mean that if someone has to take their undocumented work, they
won't know what is going on. I realize that I might not be able to
change more senior engineers, but I might be able to leave an
impression on the newer engineers. If anyone knows of some habits or a
list of some best practices that make a successful design, please pass
them onto me. Most of these habits I would assume fall into proper
system engineering.

thanks,
joe


Article: 85599
Subject: Re: Best Practices for Hardware Designers
From: "JJ" <johnjakson@yahoo.com>
Date: 11 Jun 2005 16:01:26 -0700
Links: << >>  << T >>  << A >>

Perhaps you need the "Synopsys Design Reuse Style Guide".




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