Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 89125

Article: 89125
Subject: Partial vector range in instance warning
From: "Newman" <newman5382@yahoo.com>
Date: 6 Sep 2005 04:14:27 -0700
Links: << >>  << T >>  << A >>
Hi,
  I am getting ready to clean up some XST(Verilog) warnings, and want
to open a discussion on how to eliminate/suppress unused bits coming
from instantiated modules. (e.g. WARNING:Xst:646 - Signal <temp<11:0>>
is assigned but never used.
  To further clarify, say that temp is actually a [35:0] wire that
connects to the output of a coregen 18x18 multiplier, but the lower 12
bits are intentionally not used.  Does anybody have any Verilog type
suggestions on how to eliminate the warning.  I looked at ISE's 7.1
message filtering, but was wondering about reasonable alternatives?

- Newman


Article: 89126
Subject: Re: False values in Quartus In-System Memory Editor
From: ALuPin@web.de
Date: 6 Sep 2005 05:20:47 -0700
Links: << >>  << T >>  << A >>
>The wren port is set to 0, so that no writes occur out of the logic.

But you said in your post before that you write to the memory?

>But when I write any values (including the old memory contents) to
>the memory and read thereafter


Article: 89127
Subject: Final Call for Participants CPA 2005 (18-21 Sept 2005) in Eindhoven
From: "Herman Roebbers" <herman7@iae.nl>
Date: 6 Sep 2005 05:33:27 -0700
Links: << >>  << T >>  << A >>
Hi,

(Sorry if you received this more than once; for some reason I didn't
see it
appear on the news servers I have posted this on earlier).
This is a last call for delegates to CPA 2005 at Eindhoven.  The full
academic programme, including abstracts for all talks and draft
timetable,
are now published at:

  http://wotug.org/cpa2005/programme.shtml

A link is also provided there to the Preface to the conference
proceedings,
which gives some more information about what is happening and what we
hope
will happen!

The Sunday/Monday evening Fringe sessions are getting filled - see the
draft timetable on the above URL.  If any other delegates wish to offer
something, please mail me and the conference (cpa2005@wotug.org)
quickly.

We have a very full programme this year: 4 invited talks and 25
accepted
papers.  The invited talks are from:

  H. Peter Hofstee, the CELL processor chief architect at IBM
  Paul Stravers, Senior Scientist at Philips Research Laboratories
  Ad Peeters, CEO of Handshake Solutions
  Guy Broadfoot, Lead Consultant at Verum

Their abstracts are on the page at the above URL.  Here is the
registration
page:

  http://wotug.org/cpa2005/registration.shtml

Any problems with the registration procedure - please mail Maggy at the
conference address (cpa2005@wotug.org).

We hope to see as many of you as can make it!  :)

Herman Roebbers (Chair CPA 2005)
Peter Welch (WoTUG chair)
Harold Weffers
Maggy de Wert


Article: 89128
Subject: SI newsgroup
From: "blah" <blah@blah.ca>
Date: Tue, 06 Sep 2005 12:43:16 GMT
Links: << >>  << T >>  << A >>
Does anyone here know of any Signal Integrity Newsgroups?




Article: 89129
Subject: Re: XUP Virtex-II Pro "invalid target architecture"
From: "Alex Gibson" <news@alxx.net>
Date: Tue, 6 Sep 2005 23:13:18 +1000
Links: << >>  << T >>  << A >>

<zoinks@mytrashmail.com> wrote in message 
news:1125922969.715822.250980@g49g2000cwa.googlegroups.com...
> ok I think I know what is wrong:
>
> Something went wrong during the installation of the ISE or the SDK. In
> my list of available devices, only some spartans and the Virtex2 and
> Virtex4 are listed. When I select one of the virtex, the program gives
> an error message that it cannot find the specified device size.
>
> Is there a way to add those devices to the system?
>

Sounds like you may have missed a cd ?



Article: 89130
Subject: Re: Modelsim XE and multi-file Verilog projects
From: "gallen" <arlencox@gmail.com>
Date: 6 Sep 2005 06:47:45 -0700
Links: << >>  << T >>  << A >>
Let me be more specific than Marko was.

<= is a non-blocking assign.  It is typically used for sequential
blocks of code.  That means any block of code that has an edge
sensitive element in the sensitivity list:

always @ (posedge clk)
  q <= d;

The above example is how non-blocking assigns would typically be used.

= is a blocking assign and it is used everywhere else.  That is it is
used in initial blocks,  assign statements, parameter assignments,
defparam statements and (typically) combinational always blocks:

reg combout;

always @ (stuff or things)
begin
  combout = 0;
  if(stuff)
    combout = 1;
  if(things)
    combout = 0;
end

Statements such as above can be written using blocking (=) assign.
Basically, you can write code as a c programmer would.  combout takes a
value of zero, then if stuff is set combout gets set to 1, but if then
things is set, combout is set back to zero.  Dispite the sequential
nature of this, it is important to remember that this happens in zero
time.  When this gets synthesized it will be turned into a
combinational block that has the following truth table:
s = stuff
t = things
c = combout
s t c
0 0 0
0 1 0
1 0 1
1 1 0

I hope that clears things up a bit.

-Arlen


Article: 89131
Subject: Re: SI newsgroup
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 6 Sep 2005 10:10:57 -0400
Links: << >>  << T >>  << A >>
"blah" <blah@blah.ca> wrote in message
news:E9gTe.85801$Ph4.2724247@ursa-nb00s0.nbnet.nb.ca...
> Does anyone here know of any Signal Integrity Newsgroups?

There is a SI mailing list:

To administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@freelists.org with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:
http://www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
  http://www.qsl.net/wb6tpu



Article: 89132
Subject: ANN: Altera Power Net Seminar #2
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Tue, 6 Sep 2005 10:11:15 -0400
Links: << >>  << T >>  << A >>
Hi,

On Thursday (Sept 6) Sanjay Rajput and I will be giving a Net Seminar 
entitled "Comparing Stratix II & Virtex-4 Power & Power Estimation 
Accuracy."  This technical seminar is a follow-up to Vaughn Betz & Paul 
Ekas' previous seminar on power.  An abstract and sign-up instructions can 
be found at http://www.altera.com/education/net_seminars/all/ns-power.html.

The talk will begin by describing Altera's PowerPlay power estimation tool 
suite and describe the hardware we designed for performing power comparisons 
between a 2S60 and 4VLX60 device.  We will then present extensive bench 
measurements on dynamic and I/O power, and using these measurements compare 
Stratix II and Virtex-4 power as well as the accuracy of Altera's PowerPlay 
Power Analyzer and ISE XPower.  Our conclusions will be that (1) Stratix II 
has an advantage on dynamic and I/O power, a disadvantage in static power, 
and overall has equal or better total power, and (2) that Altera's PowerPlay 
Power Analyzer consistently predicts power within a +-20% band, while XPower 
is less accurate.

We will be answering questions at the end of the seminar, and I look forward 
to any follow-up in the newsgroup.

Regards,

Paul Leventis
Altera Corp.




Article: 89133
Subject: Re: False values in Quartus In-System Memory Editor
From: "Sebastian Schmidt" <fpga@gmx.de>
Date: Tue, 06 Sep 2005 16:23:34 +0200
Links: << >>  << T >>  << A >>
Yes, in Quartus I instanciate a 1-Port RAM from the megawizard plugin  
manager.
There I select, that I want to be able to access the memory from the  
Quartus In-Systme Memory Content Editor. In the design you see the memory  
as a 1-Port memory, the second port is not seen in the Verilog source, it  
is inserted on compile time by Quartus. I have disabled the write enable  
port of the first port, the write enable port of the second port is  
handled by Quartus.

Am 06.09.2005, 14:20 Uhr, schrieb <ALuPin@web.de>:

>> The wren port is set to 0, so that no writes occur out of the logic.
>
> But you said in your post before that you write to the memory?
>
>> But when I write any values (including the old memory contents) to
>> the memory and read thereafter
>



-- 
Erstellt mit Operas revolutionärem E-Mail-Modul: http://www.opera.com/mail/

Article: 89134
Subject: Re: Modelsim XE and multi-file Verilog projects
From: "johnp" <johnp3+nospam@probo.com>
Date: 6 Sep 2005 07:37:04 -0700
Links: << >>  << T >>  << A >>


For more info on blocking vs non-blocking assignments, look at
www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

In general, the previous advice is good, ie if you use posedge or
negedge,
you probably should use <=.  For combinatorial, you probably want to
use =.

You really need to *understand* the differences between the two!  The
simple
rule is fine, but rules sometimes need to be broken.

John Providenza


Article: 89135
Subject: Re: Partial vector range in instance warning
From: "Newman" <newman5382@yahoo.com>
Date: 6 Sep 2005 08:11:42 -0700
Links: << >>  << T >>  << A >>
After reviewing the LogiCore Multiplier Generator v7.0, it looks like I
can just specify a smaller width for the Output Option.  Any other
suggestions are welcomed.

-Newman

Newman wrote:
> Hi,
>   I am getting ready to clean up some XST(Verilog) warnings, and want
> to open a discussion on how to eliminate/suppress unused bits coming
> from instantiated modules. (e.g. WARNING:Xst:646 - Signal <temp<11:0>>
> is assigned but never used.
>   To further clarify, say that temp is actually a [35:0] wire that
> connects to the output of a coregen 18x18 multiplier, but the lower 12
> bits are intentionally not used.  Does anybody have any Verilog type
> suggestions on how to eliminate the warning.  I looked at ISE's 7.1
> message filtering, but was wondering about reasonable alternatives?
> 
> - Newman


Article: 89136
Subject: Any GOSPL Docs?
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Tue, 06 Sep 2005 16:34:39 +0100
Links: << >>  << T >>  << A >>
Hi All,

Despite the demise of the GOSPL project, I'm wondering if there are any 
documents available from when the project was still running.

The website www.gospl.org seems to be refusing connections.

Surely there was some initial work done that would be of benefit to 
those interested.

Thanks
Andy

-- 
Dr. Andrew Greensted      Department of Electronics
Bio-Inspired Engineering  University of York, YO10 5DD, UK

Tel: +44(0)1904 432379    Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224    Web: www.bioinspired.com/users/ajg112

Article: 89137
Subject: Re: Strange warning "WARNING:MapLib:701 - Signal P_GPIO_3 connected
From: Duane Clark <dclark@junkmail.com>
Date: Tue, 06 Sep 2005 15:53:48 GMT
Links: << >>  << T >>  << A >>
VSP wrote:
> Hello All,
> 
> I am facing a very bugging problem while using XILINX ISE 7.1i with SP4
> installed.
> 
> Some of my top level ports has been removed by the MAP utility of
> ISE.The synthesis is successfully completing without any errors or
> warnings. The post synthesis simulation model shows all the ports and
> its related logic.
> 
> However after the MAP process has been completed, its throws up a
> warning saying that some top level ports has been
> removed.(WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level
> port P_GPIO_3 has been removed.")
> 
> Please respond if any one has encountered such problems before.

In the directory where ISE puts all the report files, look for a file 
named <project_top>.mrp. This is the mapper report file. Search through 
the file for the name of the pin that was removed. Search backwards 
through the file for the first line before this that is not indented. 
This should be the source of the reason why the pin is being removed.

Article: 89138
Subject: Re: PPC405 32 bit aligned accesses
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Tue, 06 Sep 2005 08:59:12 -0700
Links: << >>  << T >>  << A >>
If the data cache is in write-back mode and is turned on for a certain 
memory region you will not see byte, halfword or word transactions. All 
you will see are cache-line aligned cache-line transactions.

>>>Hi,
>>>Hmm, that's a shame, It'd be nice to save the I/Os I'd need for byte
>>>masking.
> 
> 
> Exactly what we thought ;O)

Only a good idea for a limited set of applications.
Anyway, before doing anything in the DDR2 memory you need to turn the 
data cache on for the address region where it is mapped. You can do that 
with a small program running from BRAM and the jump to the entry point 
of the application in the DDR2 memory. Here is some code that will do 
that for running Linux later on:

#include "xcache_l.h"

int main()
{
   void (*f)(void);

   // enable I/D cache for first 128 MB
   XCache_EnableICache(0x80000000);
   XCache_EnableDCache(0x80000000);

   f = (void*) 0x400000;   // entry point of the Linux kernel bootloader
   (*f)();

   /* we should never get here */
   return -1;
}



> Ok, I see what you mean... the plan is to use Montavista Linux on the card 
> and I am not sure how easy would be to add such service. I'll check with the 
> software guys.

It is very likely that you will need to patch your card and bring the 
byte masks out. Linux uses the MMU to set up cacheable regions, ie. it 
will/may put descriptors (networks, etc.) into uncacheable areas. Unless 
you plan to modify the Linux kernel heavily it is very unlikely that 
your system will work. You can boot Linux though from a RAM disk to 
least get started.

>>Also, make sure that the compiler knows that the memory region is
>>cachable. In an embedded world it could be that all addresses default to
>>address space with side effects. In that case the compiler has no choice
>>but to perform access to data of type byte as individual byte accesses.

That has nothing to do with the compiler, i.e. the compiler does know 
nothing about caches. The programmer is responsible to maintain memory 
coherency.


Again, please consider to patch your board. IMHO, it's the fastest way 
to make progress.

- Peter


Article: 89139
Subject: Cyclone conf flash - 25p10 !
From: "Luis Cupido" <cupidoREMOVE@REMOVEua.pt>
Date: Tue, 6 Sep 2005 17:09:14 +0100
Links: << >>  << T >>  << A >>
Hi,

I've been using the 25P10 flash to configure cyclone devices,
as far as I can see they are exactly equal to the  EPCS1
(even silicon ID is the same, I suspect it is the same chip inside)

All altera devices (in AS) I tested can read it and configure fine, however
the Quartus II fail to load data into the 25P10...
(I must use another software to load the 25p10 and that is less convenient)

Does anybody knows why... what is the trick used ?

Luis C.




Article: 89140
Subject: Re: PCI on ML310 Xilinx board
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Tue, 06 Sep 2005 09:13:45 -0700
Links: << >>  << T >>  << A >>
Currently, the 2.6 Linux kernel only has very limited support for V2P 
and V4. Please use the Linux 2.4 kernel and consult the ML310 web pages 
(http://www.xilinx.com/ml310) on how to get Linux, including PCI, up and 
running on the ML310.

In the 2.4 kernel these constants are defined in 
arch/ppc/platforms/xilinx_ml300.h

- Peter


Sven Gowal wrote:
> Hello,
> 
> I'm trying to use Linux 2.6 on the ML310 Xilinx board with PCI support.
> After adding the PCI bridge, I generate the BSP headers to compile the
> Linux kernel. I do __make menuconfig__ and add PCI support but when I
> __make__ I get the following errors:
> 
> arch/ppc/syslib/ppc4xx_setup.c: In function `ppc4xx_map_io':
> arch/ppc/syslib/ppc4xx_setup.c:123: error: `PPC4xx_PCI_IO_VADDR'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:123: error: (Each undeclared identifier
> is reported only once
> arch/ppc/syslib/ppc4xx_setup.c:123: error: for each function it appears
> in.)
> arch/ppc/syslib/ppc4xx_setup.c:124: error: `PPC4xx_PCI_IO_PADDR'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:124: error: `PPC4xx_PCI_IO_SIZE'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:125: error: `PPC4xx_PCI_CFG_VADDR'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:126: error: `PPC4xx_PCI_CFG_PADDR'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:126: error: `PPC4xx_PCI_CFG_SIZE'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:127: error: `PPC4xx_PCI_LCFG_VADDR'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:128: error: `PPC4xx_PCI_LCFG_PADDR'
> undeclared (first use in this function)
> arch/ppc/syslib/ppc4xx_setup.c:128: error: `PPC4xx_PCI_LCFG_SIZE'
> undeclared (first use in this function)
> make[1]: *** [arch/ppc/syslib/ppc4xx_setup.o] Error 1
> 
> What do I have to do to get rid of these errors? Is there a patch
> available?
> 
> Thanks a lot,
> Sven
> 


Article: 89141
Subject: Re: Reprogramming one MAXII EPM1270 vs security bit set
From: "Luis Cupido" <cupidoREMOVE@REMOVEua.pt>
Date: Tue, 6 Sep 2005 17:26:25 +0100
Links: << >>  << T >>  << A >>
Hi,

Similar situation happened to a friend of mine.
He found out that while inspecting signals with the scope
or placing the finger over the Jtag lines the MAXII loaded fine.

Altera did release a note about how sensitive some MAX II devices
were regarding the electrical behavior of the JTAG signals...
can't remember where it is but you will find it for sure at the altera site.

Over here all worked fine, but I do have a very long JTAG cable (2m)
with the original byteblasterMV it sometimes fail :(

Looks like silicon versions respond differently... the ES (engineering 
samples)
devices were more picky than the regular ones ! but that is not
scientific knowledge, just my impression.

Since on the long cable (that is more convenient here) it works always
I just  forgot about this issue and keep on developing the VHDL :)

Luis C.


<abeaujean@gillam-fei.be> wrote in message 
news:1125911324.912543.131210@o13g2000cwo.googlegroups.com...
> Hi group,
>
> I would like to share an impression I have.
>
> Trying to erase and/or reprogram one Altera MAXII EPM1270 device using
> the Quartus 5.0 Sp1 Web free edition software and the ByteBlasterII
> programming adapter kept on failing (same thing with ByteBlasterMV and
> previous revision of the soft).
>
> After considering lots of possibilities (missing pullups, pulldowns,
> JTAG clock with glitches, although none observed), I finally decided to
> have the component de-soldered and a new one resoldered.
>
> IT NOW WORKS.
>
> Re-thinking the whole thing from the start, I now wonder if this
> behaviour is not due to the previous use of the security bit. I
> remember I set the security bit once on that device (on two different
> prototypes, both of which were exhibiting the same problem).
>
> The security bit, once set, should I believe not prevent the component
> from being erased and re-programmed (am I right or wrong ?). If you
> read the MAXII specification, it seems so.
>
> The symptoms were :
>
> Error: Can't recognize silicon ID for device 1
> Error: Operation failed
>
> on both prototypes.
>
> Both prototypes are now working with the new soldered components.
>
> Has anyone experienced such a behaviour before ?
>
> So, I do believe that the problem could be once the security bit is
> set.
>
> It could also be due to an incorrect definition of the length of two
> non Altera devices part of this JTAG chain (4 instead of 16), but
> anyway it is so strange that one could set a condition in the component
> that prevents it from being re-programmed.
>
> Software bug ?
>
> Any idea ?
> 



Article: 89142
Subject: Re: PPC405 32 bit aligned accesses
From: "I. Ulises Hernandez" <delete@e-vhdl.com>
Date: Tue, 6 Sep 2005 16:31:58 +0000 (UTC)
Links: << >>  << T >>  << A >>
Peter,

Really appreciatte all your comments, I am going to inform the software guys 
straight away; I think we have caught this problem on time, just before 
prototyping...

I'll keep you informed on how things go.

Regards,
Ulises Hernandez.

"Peter Ryser" <peter.ryser@xilinx.com> wrote in message 
news:431DBCD0.9020200@xilinx.com...
> If the data cache is in write-back mode and is turned on for a certain 
> memory region you will not see byte, halfword or word transactions. All 
> you will see are cache-line aligned cache-line transactions.
>
>>>>Hi,
>>>>Hmm, that's a shame, It'd be nice to save the I/Os I'd need for byte
>>>>masking.
>>
>>
>> Exactly what we thought ;O)
>
> Only a good idea for a limited set of applications.
> Anyway, before doing anything in the DDR2 memory you need to turn the data 
> cache on for the address region where it is mapped. You can do that with a 
> small program running from BRAM and the jump to the entry point of the 
> application in the DDR2 memory. Here is some code that will do that for 
> running Linux later on:
>
> #include "xcache_l.h"
>
> int main()
> {
>   void (*f)(void);
>
>   // enable I/D cache for first 128 MB
>   XCache_EnableICache(0x80000000);
>   XCache_EnableDCache(0x80000000);
>
>   f = (void*) 0x400000;   // entry point of the Linux kernel bootloader
>   (*f)();
>
>   /* we should never get here */
>   return -1;
> }
>
>
>
>> Ok, I see what you mean... the plan is to use Montavista Linux on the 
>> card and I am not sure how easy would be to add such service. I'll check 
>> with the software guys.
>
> It is very likely that you will need to patch your card and bring the byte 
> masks out. Linux uses the MMU to set up cacheable regions, ie. it will/may 
> put descriptors (networks, etc.) into uncacheable areas. Unless you plan 
> to modify the Linux kernel heavily it is very unlikely that your system 
> will work. You can boot Linux though from a RAM disk to least get started.
>
>>>Also, make sure that the compiler knows that the memory region is
>>>cachable. In an embedded world it could be that all addresses default to
>>>address space with side effects. In that case the compiler has no choice
>>>but to perform access to data of type byte as individual byte accesses.
>
> That has nothing to do with the compiler, i.e. the compiler does know 
> nothing about caches. The programmer is responsible to maintain memory 
> coherency.
>
>
> Again, please consider to patch your board. IMHO, it's the fastest way to 
> make progress.
>
> - Peter
> 



Article: 89143
Subject: WARNING:HDLParsers:3481 - No primary, secondary unit in the file
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 6 Sep 2005 10:13:35 -0700
Links: << >>  << T >>  << A >>
I have been using CoreGen to generate the DCMs on a Spartan3 project.  After 
going through the wizzard, I can select the .XCO in the process window, and 
can view two files, the HDL Source and the HDL Instantiation Template.  I 
don't worry about the source file. The template file,  I cut,  paste, and 
fill in the blanks with my signals.

Things went a little different today with an Async FIFO generation.  When 
selecting the fifo.xco source, instead of two files, I can view only one 
file, called the Functional Model.  What's the difference?  I was able, I 
think, to figure out the instantiation of this generated device although I 
am getting a WARNING:HDLParsers:3481 - No primary, secondary unit in the 
file, warning and consequently an excamation point near the check syntex 
process in my top design. How do I get rid of this warning, and where, in 
general, do I look up HDLParsers warnings/errors?

Brad Smallridge
a i v i s i o n . c o m


 



Article: 89144
Subject: Re: Strange behaviour while trying to program MAX II CPLD's
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Tue, 6 Sep 2005 13:36:51 -0400
Links: << >>  << T >>  << A >>
Hi,

I would suggest filing a case with mysupport.altera.com.  I wish I could 
help you, but JTAG programming is outside my area of knowledge!

Regards,

Paul Leventis
Altera Corp. 



Article: 89145
Subject: Re: Low Power RTL Design
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Tue, 6 Sep 2005 13:50:40 -0400
Links: << >>  << T >>  << A >>
Hi Hosni,

There are many techniques for reducing your power consumption.  Those at the 
RTL level have the highest possible impact, since you can change the 
behaviour of your system and make trade-offs that are not possible in later 
stages of the RTL-to-FPGA flow.

The "Stratix II Low Power Design Techniques" handbook section 
(http://www.altera.com/literature/hb/qts/qts_qii51016.pdf) provides some 
suggestions we have found to be helpful on Stratix II devices.

Most hardware designers were taught how to design when power wasn't such a 
big deal.  This means that we often do things such as generate or read 
results even when we don't need them, since logically it doesn't matter (the 
downstream logic will be ignoring those inputs, etc.).  If you can identify 
these cases and insert gating or clock control logic to stop unused pieces 
of logic from toggling when not needed, you can achieve a lot of power 
savings.

One example is RAMs.  Users will often not specify a RAM read enable, thus 
the RAM will be executing a read every clock cycle.  But you probably don't 
need the RAM result every cycle.  By simply making an explicit read enable, 
you can greatly reduce the RAM power since every read operation initiates a 
pre-charge/dis-charge cycle within the RAM, and if the result is different 
than the previous cycle, causes downstream logic to wiggle too.

Regards,

Paul 



Article: 89146
Subject: Re: PPC405 32 bit aligned accesses
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 6 Sep 2005 11:08:09 -0700
Links: << >>  << T >>  << A >>
"Peter Ryser" <peter.ryser@xilinx.com> wrote in message
news:431DBCD0.9020200@xilinx.com...
>
> It is very likely that you will need to patch your card and bring the
> byte masks out. Linux uses the MMU to set up cacheable regions, ie. it
> will/may put descriptors (networks, etc.) into uncacheable areas. Unless
> you plan to modify the Linux kernel heavily it is very unlikely that
> your system will work. You can boot Linux though from a RAM disk to
> least get started.
>
Hi Peter,
Could you explain why Linux puts these things in uncacheable areas?
Also, how does a RAM disk help you boot?
Thanks very much, Syms.



Article: 89147
Subject: Re: Altera Power Net Seminar #2
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Tue, 6 Sep 2005 14:18:13 -0400
Links: << >>  << T >>  << A >>
Quick correction:  The seminar is Thursday, September *8* at 11 AM PST.

"Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message 
news:o6adnTGNtNEfPoDeRVn-vQ@rogers.com...
> Hi,
>
> On Thursday (Sept 6) Sanjay Rajput and I will be giving a Net Seminar 
> entitled "Comparing Stratix II & Virtex-4 Power & Power Estimation 
> Accuracy."  This technical seminar is a follow-up to Vaughn Betz & Paul 
> Ekas' previous seminar on power.  An abstract and sign-up instructions can 
> be found at 
> http://www.altera.com/education/net_seminars/all/ns-power.html.
>
> The talk will begin by describing Altera's PowerPlay power estimation tool 
> suite and describe the hardware we designed for performing power 
> comparisons between a 2S60 and 4VLX60 device.  We will then present 
> extensive bench measurements on dynamic and I/O power, and using these 
> measurements compare Stratix II and Virtex-4 power as well as the accuracy 
> of Altera's PowerPlay Power Analyzer and ISE XPower.  Our conclusions will 
> be that (1) Stratix II has an advantage on dynamic and I/O power, a 
> disadvantage in static power, and overall has equal or better total power, 
> and (2) that Altera's PowerPlay Power Analyzer consistently predicts power 
> within a +-20% band, while XPower is less accurate.
>
> We will be answering questions at the end of the seminar, and I look 
> forward to any follow-up in the newsgroup.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
>
> 



Article: 89148
Subject: Final Call for Participants & fringe CPA 2005 (18-21 Sept 2005) in Eindhoven
From: "Herman Roebbers" <herman7@IAE.nl>
Date: 6 Sep 2005 11:21:09 -0700
Links: << >>  << T >>  << A >>

Hi,

This is a last call for delegates to CPA 2005 at Eindhoven.  The full
academic programme, including abstracts for all talks and draft timetable,
are now published at:

  http://wotug.org/cpa2005/programme.shtml

A link is also provided there to the Preface to the conference proceedings,
which gives some more information about what is happening and what we hope
will happen!

The Sunday/Monday evening Fringe sessions are getting filled - see the
draft timetable on the above URL.  If any other delegates wish to offer
something, please mail me and the conference (cpa2005@wotug.org) quickly.

We have a very full programme this year: 4 invited talks and 25 accepted
papers.  The invited talks are from:

  H. Peter Hofstee, the CELL processor chief architect at IBM
  Paul Stravers, Senior Scientist at Philips Research Laboratories
  Ad Peeters, CEO of Handshake Solutions
  Guy Broadfoot, Lead Consultant at Verum

Their abstracts are on the page at the above URL.  Here is the registration
page:

  http://wotug.org/cpa2005/registration.shtml

Any problems with the registration procedure - please mail Maggy at the
conference address (cpa2005@wotug.org).

We hope to see as many of you as can make it!  :)

Herman Roebbers (Chair CPA 2005)
Peter Welch (WoTUG chair)
Harold Weffers
Maggy de Wert


-- 

Article: 89149
Subject: Re: PCI on ML310 Xilinx board
From: "Sven Gowal" <sgowal@gmail.com>
Date: 6 Sep 2005 11:28:53 -0700
Links: << >>  << T >>  << A >>
Unfortunately I have to use the linux 2.6 kernel... but thanks for the
info.

- Sven




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search