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You could always instatiate the RAM blocks from the unisim library and design the control. The other method is to use attributes variable to tell the synthesis tool to instantiate BRAM for the vhdl code. (See Xilinx documents) Paul mte01 wrote: > Hello, > > The following is said in the documentation of Xilinx ISE (in the > following place for ISE users: > <Xilinx Istallation > path>/doc/usenglish/help/iseguide/iseguide.htm#html/fd_inst_bram_vhdl.htm= ): > > The following VHDL code demonstrates how to infer a Dual Port BlockRAM > component for Virtex=99 devices when synthesizing with XST. Only XST > supports RAM inference. > > > entity dpblockram is > > port (clk : in std_logic; > > we : in std_logic; > > a : in std_logic_vector(4 downto 0); > > dpra : in std_logic_vector(4 downto 0); > > di : in std_logic_vector(3 downto 0); > > spo : out std_logic_vector(3 downto 0); > > dpo : out std_logic_vector(3 downto 0)); > > end dpblockram; > > architecture syn of dpblockram is > > type ram_type is array (31 downto 0) of std_logic_vector > (3 downto 0); > > signal RAM : ram_type; > > signal read_a : std_logic_vector(4 downto 0); > > signal read_dpra : std_logic_vector(4 downto 0); > > begin > > process (clk) > > begin > > if (clk'event and clk =3D '1') then > > if (we =3D '1') then > > RAM(conv_integer(a)) <=3D di; > > end if; > > read_a <=3D a; > > read_dpra <=3D dpra; > > end if; > > end process; > > spo <=3D RAM(conv_integer(read_a)); > > dpo <=3D RAM(conv_integer(read_dpra)); > > end syn; > > > ******************************************************* > > I have used this initialization method of array of std_logic_vector in > trying to use the FPGA's BRAMs when designing a processor in VHDL, but > I got the following info warning (which indicates that BRAMs are not > used): > > INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal > <memory>. You may be trying to describe a RAM in a way that is > incompatible with block and distributed RAM resources available on > Xilinx devices, or with a specific template that is not supported. > Please review the Xilinx resources documentation and the XST user > manual for coding guidelines. Taking advantage of RAM resources will > lead to improved device usage and reduced synthesis time. >=20 > Any help on how to use Block RAMs in VHDL??Article: 89576
john.orlando@gmail.com <john.orlando@gmail.com> wrote: > Hello, Hi! > the PCI interface in a slightly different form factor). Anyway, in > architecting this project, we are discussing how to re-configure the > FPGA from the host machine (in this case, a Processor PMC card running Though I cannot help you, your problem reminds me of firmware upgrades for my RME Hammerfall HDSP (www.rme-audio.com) Wouldn't it be possible to let the FPGA write to its own PROM/Flash? You can still handle the PCI-interface with the FPGA-logic while uploading the firmware to non-volatile memory. Afterwards you'll have to reboot or reload (reconfigure) the FPGA from the flash. Just my $0.02, never done anything like this... -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Was lacostet die Welt?Article: 89577
mte01 wrote:
> Any help on how to use Block RAMs in VHDL??
http://groups.google.com/groups?q=vhdl+block+ram+to_integer
-- Mike Treseler
Article: 89578I use Modelsim MXE Starter. The full version is expensive! What would you suggest to use instead, Simon? I use Modelsim at work so I'm familiar with it, and my own personal designs aren't very large, so I haven't ran into that "speed-limiter" the free version has. Eventually, I suspect I will, and I'm not looking forward to it. Simon Peacock wrote: > Forget Modelsim for Xilinx as its knobbled for large designs.. they want you > to buy the full version > > Simon > > "Frank" <Francis.invalid@hotmail.com> wrote in message > news:432e714e@news.starhub.net.sg... > > > > "Frank" <Francis.invalid@hotmail.com> wrote in message > > news:432e70c9$1@news.starhub.net.sg... > > > I had 2003 version on my PC, but it's giving me performance hassles > > > on yesterday's simulations. What is the latest version of Modelsim for > > > Xilinx? How is the performance? > > > > > > I am writing a 20K+ design for opencores, what free simulator can I use? > > > > > > Thanks for your info. > > > > > > Frank > > > > > > > > > > > > > BTW, I am dumb, so I need GUI to view waveforms during debugging. > > > > > >Article: 89579
Jock wrote: > We have an MCS_86 output file for an Xilinx 4000 series device. However, all > the design files are missing and we need to modify it. > > Is there any software available that would allow me to reverse engineer the > output file? > No. It is a bit stream and there is not way to reverse engineer back to the original design. -SteveArticle: 89580
john.orlando@gmail.com wrote: > These seem to provide a PCI > interface on one end, and a memory-interface on the other, making > them pretty simple to use. But I still don't see how this will bring > the ability to re-program the FPGA image. In the past we used a small CPLD hanging off the back end of a PLX 9054 to bit-bash (not JTAG) the FPGA from an image embedded in the host driver for our card (no reason it couldn't be read from a file). We could also program the CPLD itself by bit-bashing JTAG from a DOS-based JAM player. Regards, MarkArticle: 89581
Thank you Simon. I am doing my opencores design on my home PC as a passtime, so I intend to spend no extra $ only time on it. How does Icarus & IVI combination perform? My design is 10K and vcd dump is as large as 50MB. "Simon Peacock" <simon$actrix.co.nz> wrote in message news:432e8c2a$1@news2.actrix.gen.nz... > Forget Modelsim for Xilinx as its knobbled for large designs.. they want you > to buy the full version > > Simon > > "Frank" <Francis.invalid@hotmail.com> wrote in message > news:432e714e@news.starhub.net.sg... > > > > "Frank" <Francis.invalid@hotmail.com> wrote in message > > news:432e70c9$1@news.starhub.net.sg... > > > I had 2003 version on my PC, but it's giving me performance hassles > > > on yesterday's simulations. What is the latest version of Modelsim for > > > Xilinx? How is the performance? > > > > > > I am writing a 20K+ design for opencores, what free simulator can I use? > > > > > > Thanks for your info. > > > > > > Frank > > > > > > > > > > > > > BTW, I am dumb, so I need GUI to view waveforms during debugging. > > > > > > > >Article: 89582
I can't really recommend IVI. It it's definitely not easy to use or particularly stable. I'm also not a tremendous fan of Icarus. The last version I used 0.8.1 (I think) had a memory leak so the performance was abysmal. It was far outpaced by the slowed down modelsim XE. If you can't spend money, I recommend gpl cver and gtk wave. They aren't great, but they'll do the trick. I find cver to be slower than modelsim by a fair bit, but it's faster once the limit is exceeded. http://www.pragmatic-c.com/gpl-cver/ http://home.nc.rr.com/gtkwave/ I must give the warning that gtkwave loads the whole vcd into memory and then some, so if you're opening 300MB VCD files, you really need to have at least 1 GB of memory (maybe more). I know I have 768MB and it thrashed until I killed it. There is no way you are going to get a free tool with a gui like modelsim. Heck, most commercial tools don't have guis like modelsim. As far as I know vcs and ncverilog don't have nice guis. With those tools you do everything on the command line. Good luck, ArlenArticle: 89583
Garrick wrote:
> Kim, thanks for the information. I have a few follow up questions, but
> I realize now that I should have specified that I am using Modelsim XE,
> the free simulator for Xilinx. I thought the only limitation was
OK, I'm using the SE version and it's manuals :)
> project size, but I am unable to compile a resource library with a
> -nodebug flag, and would be unable to use a -nodebug compiled library if
> one was supplied to me by a 3rd party.
I would be suprised if you couldn't use -nodebug library in XE version.
That is the old way of protecting IP with Modelsim. The problem was that
it protected the whole modules and tied them to some simulator version.
-nodebug just removes all visibility from the design module when compiled.
But I guess you should be asking from Mentor what they suppport in XE.
There are limitations how -nodebug modules can be used in the hierarchy.
If I remeber correctly they must be leafs in the design hierarchy, otherwise
Modelsim can complain quite loudly.
> It appears as if the `protect compiler directive is supported (at least
> initially) in Modelsim XE. I've placed `protect/`endprotect in my
> verilog modules and compiled them using the +protect flag. They compile
> fine with no warnings.
>
> However, it doesn't appear as if anything is being protected. I've
> tried putting the `protect/`endprotect both within the module and around
I just tried and in SE it works just fine. I used the small example below and
then commands
vlib work
vlog +protect foo.v
more work/foo.vp (contains file that has the module definition but everything
else is encrypted).
foo.v:
module D_Flop (q, d, clock, reset);
output q;
input d;
input clock;
input reset;
reg q;
`protect
always @(posedge clock or posedge reset)
if (reset) q <= #1 0;
else q <= #1 d;
endmodule // D_Flop
`endprotect
--Kim
Article: 89584Hi Joe, Thank you very much for your help, but where did you set these parameters as follows: PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 90000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 90000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 100000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 100000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 50000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 0 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 0 I couldn't find them in "add/edit cores" of SRAM_256K*32_FLASH_2M*32, and it is still strange that my flash is only 4M not 8M. Do you add these parameters by software programme? And about how to read data from or write data to the flash, is there any special methods? Do you have any material or example projects and software codes for the flash on P160 module2? could you gave me some? thank you very much! AthenaArticle: 89585
Thank you for the information. I will try that later. Frank "gallen" <arlencox@gmail.com> wrote in message news:1127194129.436216.289820@f14g2000cwb.googlegroups.com... > I can't really recommend IVI. It it's definitely not easy to use or > particularly stable. I'm also not a tremendous fan of Icarus. The > last version I used 0.8.1 (I think) had a memory leak so the > performance was abysmal. It was far outpaced by the slowed down > modelsim XE. > > If you can't spend money, I recommend gpl cver and gtk wave. They > aren't great, but they'll do the trick. I find cver to be slower than > modelsim by a fair bit, but it's faster once the limit is exceeded. > > http://www.pragmatic-c.com/gpl-cver/ > http://home.nc.rr.com/gtkwave/ > > I must give the warning that gtkwave loads the whole vcd into memory > and then some, so if you're opening 300MB VCD files, you really need to > have at least 1 GB of memory (maybe more). I know I have 768MB and it > thrashed until I killed it. > > There is no way you are going to get a free tool with a gui like > modelsim. Heck, most commercial tools don't have guis like modelsim. > As far as I know vcs and ncverilog don't have nice guis. With those > tools you do everything on the command line. > > Good luck, > Arlen >Article: 89586
Hi, I am trying to program the configuration prom (xcf16p) through dedicated pins of my fpga. i.e I connect some GPIO of my fpga to the JTAG inputs of the prom, and try to load a new configuration to the prom. I do the configuration by impementing the jtag command in the .svf file produced by iMPACT. It does not work, and my fpga is erased even when i am only trying to read the IDCODE. Although I put a logic analyzer of the prom jtag input and compared the captured waveforms of 1. jtag programming by iMPACT (that works) 2. programming by my GPIO (.svf file - does not work) and the waveforms look the same (till the point my fpga is erased ....) ThankX NAHUMArticle: 89587
Hi, I've a problem on fitting my vhdl design in a cyclone. The compiler report says "Required P2P time" is longer than actual "P2P time". I can find in the quartus help that we could increase T hold specification to correct this problem.. But I don't really understand what "Thold" mean.. and i'm not sure my solution is to increase it.. So, if anyone could help me to understand what happen... Many thanks..Article: 89588
john.orlando@gmail.com schrieb: > Anyway, in > architecting this project, we are discussing how to re-configure the > FPGA from the host machine (in this case, a Processor PMC card running > Linux that will be doing the PCI bus enumeration). Solutions we have > discussed would be to have the ability to write to a PROM through > custom logic through the PCI bus, and then allow the FPGA to boot from > this PROM. We have also big-banged the serial-loading protocol in the > past from an ARM processor directly connected to the FPGA, but not over > PCI. > > However, with our forray into PCI, being able to load the FPGA through > the PCI bus is quite attractive. Obviously, if the FPGA is providing > the PCI bus interface, we would have the chicken-before-the-egg > syndrome (i.e., no PCI interface to load the FPGA since the PCI > interface is IN the FPGA). So what about using dedicated PCI bus > interface chips? These seem to provide a PCI interface on one end, and > a memory-interface on the other, making them pretty simple to use. But > I still don't see how this will bring the ability to re-program the > FPGA image. > > I don't need to do it on the fly while the system is up and running; I > would simply like to be able to, at power up, have the Processor PMC > card open a bitstream file it has on its local file system, dump the > bitstream down to the FPGA over the PCI interface, and then have the > FPGA start in its normal user mode. > > I've looked around a bunch and people are certainly doing this. But I > can't find many good explanations as to how its working. Are they > bit-bangging JTAG??? If you have a PCI-interface in your FPGA it is relatively easy to add a few I/O-pins to be able to write the configuration flash via PCI. You can indeed bit bang JTAG using an SVF player with SVFs generated with Impact. However, if this process is interrupted somehow you need to physically access the board to bootstrap it again. You really need to make sure that your programming logic works before programming it into the FPGA. Using a dedicated interface chip solves this problem. Most chips have a few general purpose IO pins that can be used for bit banging. Or you add a small CPLD to hook the select map port to the backend bus of the interafce chip. Or you use one 5V tolerant FPGA for the PCI-interface, and another modern FPGA for your user logic. This is the most flexible solution. Kolja SulimmaArticle: 89589
Hello Kolja, do you know a supplier of SRAM-DIMMs? The problem with DRAM-DIMMs (or modules as used in PCs) is that they have too much pins for using with my FPGA-board. Thanks and greetings Udo.Article: 89590
Kolja Sulimma =D7=9B=D7=AA=D7=91: > john.orlando@gmail.com schrieb: > If you have a PCI-interface in your FPGA it is relatively easy to add a > few I/O-pins to be able to write the configuration flash via PCI. > You can indeed bit bang JTAG using an SVF player with SVFs generated > with Impact. This is exactly what I am trying to do (after the PCI jtag idea failed). Unfortunately as I begin the SVF sequence (i.e read IDCODE) the prom seems to erase my fpga ...... then I am stucked with no way continue to configure the flash cause my design is gone. The documentation on the usage of SVF is very poor and I dont understand why, since we payed the money purchase the devices / sw and do legal usage with it. > However, if this process is interrupted somehow you need to physically > access the board to bootstrap it again. You really need to make sure > that your programming logic works before programming it into the FPGA. > > Using a dedicated interface chip solves this problem. Most chips have a > few general purpose IO pins that can be used for bit banging. Or you add > a small CPLD to hook the select map port to the backend bus of the > interafce chip. Or you use one 5V tolerant FPGA for the PCI-interface, > and another modern FPGA for your user logic. This is the most flexible > solution. >=20 > Kolja SulimmaArticle: 89591
Well, John McCluskey and Kamal were right -- the reg code I had was for Foundation with ISIM. A new code for Foundation without ISIM works under Linux! Xilinx: This might be something to add to an FAQ on Foundation ISE Linux installation. Just wondering, is it normal for the installer to finish and not add any icons or anything? I found the ISE binary in one of the folders and executed it and the GUI came up and worked. Next step is the EDK... Thank you all! Ram.Article: 89592
One board is listed at $295, the other at $595. It doesn't take many additional parts and features to take a bite out of $300. The Spartan 3 is in an FG676 package, the V4 in the F363 package. In general, the more IO's, the more $$. The 3S has two expansion slots and on-board flash, and a speaker in addition to the DDR mem, switches and LCD that they have in common. Board pricing from distributors is not totally dependent on the true silicon cost. They receive compensation from supplier marketing groups to promote new parts and features. It is not only the FPGAs that are being promoted but also the other components as well. PipArticle: 89593
I saw an interesting STmicroelectonics' chip which embed an ARM9 core and a FPGA, this is the STW21000. Did someone heard about this chip or an equivalent (=B5proc + FPGA) ? Where can i buy one or more (less than 10)? thanksArticle: 89594
In order to program the V4 I would have to use the jtag cable? Also what is "serial data flash"? an add on? ThanksArticle: 89595
kagior wrote: > I saw an interesting STmicroelectonics' chip which embed an ARM9 core > and a FPGA, this is the STW21000. > > Did someone heard about this chip or an equivalent (µproc + FPGA) ? > > Where can i buy one or more (less than 10)? > > thanks > Xilinx: Virtex-4 FX family, embeds one or two PowerPC, take a look at www.Xilinx.com I suppose ALtera will have a similar porduct, but I am not familiar with itArticle: 89596
> I don't need to do it on the fly while the system is up and running; I > would simply like to be able to, at power up, have the Processor PMC > card open a bitstream file it has on its local file system, dump the > bitstream down to the FPGA over the PCI interface, and then have the > FPGA start in its normal user mode. > > I've looked around a bunch and people are certainly doing this. But I > can't find many good explanations as to how its working. Are they > bit-bangging JTAG??? I'm doing something similar-ish with an Altera Cyclone and an EPCS4 (serial prom). The board this is on is connected to an SBC via a PC104+ interface. The SBC can re-program the EPCS4 over the PCI interface, but you have to re-boot the system to get the updated config file to be used. It's then used on every power on until it's updated again. The risk is that if the system's powered down during config you've got to get in with a programming cable to recover the box, but so far it's been very reliable. I've managed to do this using just the standard serial configuration interface. Nial ------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 89597
On 20 Sep 2005 05:37:37 -0700, "kagior" <gbirot@free.fr> wrote: >I saw an interesting STmicroelectonics' chip which embed an ARM9 core >and a FPGA, this is the STW21000. > >Did someone heard about this chip or an equivalent (µproc + FPGA) ? Atmel has FPSLIC (AVR with FPGA), but the processor is 8bit. http://www.atmel.com/products/FPSLIC/ >Where can i buy one or more (less than 10)? You can buy them at Digi-Key http://www.digikey.com/ http://www.digikey.com/scripts/DkSearch/dksus.dll?Criteria?Ref=127172&Site=US&Cat=32375548 TomArticle: 89598
Ram <r_fpga_dev@yahoo.com> wrote: > Just wondering, is it normal for the installer to finish and not add any > icons or anything? Under Unix? Sure, you cannot know the user's desktop environment. Perhaps there are some recommendations in the FHS (or LSB), but I wouldn't currently rely on it. -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Lieber Gras rauchen als Grass lesen (gesprochen kommt das besser)Article: 89599
On Mon, 19 Sep 2005 12:51:28 -0700, john.orlando wrote: FPGA, but not over PCI. > > However, with our forray into PCI, being able to load the FPGA through > the PCI bus is quite attractive. Obviously, if the FPGA is providing > the PCI bus interface, we would have the chicken-before-the-egg syndrome > (i.e., no PCI interface to load the FPGA since the PCI interface is IN > the FPGA). So what about using dedicated PCI bus interface chips? These > seem to provide a PCI interface on one end, and a memory-interface on > the other, making them pretty simple to use. But I still don't see how > this will bring the ability to re-program the FPGA image. Its possible to use the PLX9054 PCI bridge chip to load Xilinx FPGA in 8 bit slave mode with no added hardware except a resistor or three. We do this on some or our cards. Peter Wallace
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