Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 89550

Article: 89550
Subject: Re: Is a CPLD appropriate for this triple PWM application?
From: David Brown <david@westcontrol.removethisbit.com>
Date: 19 Sep 2005 11:25:48 +0200
Links: << >>  << T >>  << A >>
they call me frenchy wrote:
<snip>

> I appreciate your input.  You will probably hear from me again in the
> coming weeks.  BTW, what is the most appropriate newsgroup for my new
> uC path?
> 
> infinite gratitude,
> frenchy

That would be comp.arch.embedded.  If you go for the AVR, you'll also 
find www.avrfreaks.net to be very helpful.

mvh.,

David

Article: 89551
Subject: Re: Dll device for FPGA
From: Alex <al.lopich@gmail.com>
Date: Mon, 19 Sep 2005 10:36:39 +0100
Links: << >>  << T >>  << A >>
HI

I think for your purposes if I crrectly understood the problem, you can  
find ready to use USB
solutions from http://www.opalkelly.com/ or http://www.dlpdesign.com/usb/.  
If you build your own board
then chips from Cypress or FTDI is what you need. They all provide  
necessary libraries for USB programming.

Regards
-- 
Alex

Article: 89552
Subject: Re: Modelsim XE, what's the latest version?
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Mon, 19 Sep 2005 22:00:09 +1200
Links: << >>  << T >>  << A >>
Forget Modelsim for Xilinx as its knobbled for large designs.. they want you
to buy the full version

Simon

"Frank" <Francis.invalid@hotmail.com> wrote in message
news:432e714e@news.starhub.net.sg...
>
> "Frank" <Francis.invalid@hotmail.com> wrote in message
> news:432e70c9$1@news.starhub.net.sg...
> > I had 2003 version on my PC, but it's giving me performance hassles
> > on yesterday's simulations. What is the latest version of Modelsim for
> > Xilinx? How is the performance?
> >
> > I am writing a 20K+ design for opencores, what free simulator can I use?
> >
> > Thanks for your info.
> >
> > Frank
> >
> >
> >
>
> BTW, I am dumb, so I need GUI to view waveforms during debugging.
>
>
>



Article: 89553
Subject: Testbench failures for Opencores Ethernet mac
From: pei@uwiep.com
Date: 19 Sep 2005 03:01:54 -0700
Links: << >>  << T >>  << A >>
Hello,

I'm fairly new to this - just got started running the testbench for the
Opencores Ethernet core. I'm using Modelsim SE64 Plus 6.0b in a Solaris
5.10 environment.

I get a few test failures when running the testbench:


Heading: MIIM MODULE TEST

At time:              8991769
Test: TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE
REQUEST ( WITH AND WITHOUT PREAMBLE )
*FAILED* because
Data was not correctly written into OR read from PHY register -
control register

*****************************************************
Heading: MAC HALF DUPLEX FLOW TEST

At time:            483196167
    Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND
RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
    *FAILED* because
    Transmit should NOT start more than 1 CLK after CarrierSense and
causing Collision

At time:            484976407
    Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND
RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )
    *FAILED* because
    Transmit should NOT start more than 1 CLK after CarrierSense and
causing Collision

 At time:            955522987
    Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND
RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )
    *FAILED* because
    Transmit should NOT start more than 1 CLK after CarrierSense and
causing Collision

The above tests also failed a number of times for other reasons,  so I
was wondering if I was missing anything. I checked the opencores
forums, and it seemed like someone had similar problems, but there were
no answers to that thread. I also ran it on an earlier version of
Modelsim and got the same failures. I don't know if I perhaps didn't
configure something correctly?

Thanks.

Pei


Article: 89554
Subject: Reverse Engineering Output Files
From: "Jock" <ian.mcneil@nospam.com>
Date: Mon, 19 Sep 2005 11:09:54 +0100
Links: << >>  << T >>  << A >>
We have an MCS_86 output file for an Xilinx 4000 series device. However, all
the design files are missing and we need to modify it.

Is there any software available that would allow me to reverse engineer the
output file?



Article: 89555
Subject: Re: Reading a PAL fusemap with a microscope
From: Ram <r_fpga_dev@yahoo.com>
Date: Mon, 19 Sep 2005 10:52:17 GMT
Links: << >>  << T >>  << A >>
Hi Alex,

Alex Freed wrote:

> I guess I can say I know what I'm talking about: I did a clone of Apple
> 2 in a single FPGA chip for fun. Only took a couple of days. Of course I
> have access to design tools that are a far cry from what was hot in 1980.
> 
> http://www.mirrow.com/FPGApple

This is quite amazing!

Can you give some details on what you did for the CompactFlash interface? 
Did you develop your own IDE controller?

Also, you mention USB 2.0.  How did you handle the hardware/software issues
with getting that to work?

Very impressive design!

You could consider putting some more screen shots or something up.

Thanks,
Ram.

Article: 89556
Subject: FPGA's in bulk and pricing
From: "jai.dhar@gmail.com" <jai.dhar@gmail.com>
Date: 19 Sep 2005 06:07:42 -0700
Links: << >>  << T >>  << A >>
I was wondering where you can obtain 12Q240C8 parts in small
quantities.. but no singles... ie: 10-25, in North America. I usually
get my parts from Digikey, but it is $47 CDN a pop, which I believe is
quite expensive. What price do you guys normally obtain FPGA's for?
Thanks, Jai.


Article: 89557
Subject: Re: USB tranciever + controller in FPGA
From: "John M" <JohnM@newsgroups.nospam>
Date: Mon, 19 Sep 2005 14:12:37 GMT
Links: << >>  << T >>  << A >>
Is your device a USB 2.0 or 1.1?

In either case, USB will use both differential pair and single ended 
signaling, so you need to handle both.

Marc Reinig
System Solutions

"Eric" <desert_fox_properties@yahoo.com> wrote in message 
news:1126719293.478187.104110@g43g2000cwa.googlegroups.com...
> I'm trying to put together a small board design that I can use to
> verify the functionality of a microcontroller that has a USB
> controller/tranceiver built into it.  On the board I would like to have
> only the controller and a single FPGA (say Xilinx Virtex-4), with the
> FPGA hooked to every I/O of the controller I'm trying to test,
> including the USB signals.  From what I can tell the FPGA supports LVDS
> with specs that seem to be in line with the USB differential signalling
> requirements.  My question is, has anyone connected an FPGA like this
> directly to a USB client/host chip, without using a tranciever on the
> board?
>
> Thanks
>
> Eric
> 



Article: 89558
Subject: Re: Xilinx ML403
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 19 Sep 2005 15:27:38 +0100
Links: << >>  << T >>  << A >>
"Brad Smallridge" <bradsmallridge@dslextreme.com> writes:
<snip>
> 
> As far as I understand the Camera Link interface, the
> clock is sent along with the data on a separate LVDS
> pair. The specification wants a National chipset to render
> the LVDS pairs to TTL/CMOS levels, but I'm thinking
> that the Xilinx part should be able to handle it.
> 

The "clock" is actually sent at 1/7th of the rate of the pixel-clock -
it is more like a frame sync signal.

We have Camera Link in a Virtex-II working, so the part can definately
handle it :-)

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 89559
Subject: Two short-term research grants
From: "Davide Anguita" <anguita@dibe.unige.it>
Date: Mon, 19 Sep 2005 16:53:32 +0200
Links: << >>  << T >>  << A >>
Sorry for cross-posting, but I think that this announcement can be of 
interest to many readers.


                         SmartLab
       Dept. of Biophysical and Electronic Engineering
                University of Genoa, Italy

                www.smartlab.dibe.unige.it

is offering TWO short-term research positions for recently
graduated foreign (*) students.

(*) Participation is restricted to foreign citizens residing
in a foreign country (other than Italy).

== Position A
Research Area:
 Nature-inspired Smart Information Systems
Research subject:
 The research will focus on the study of Nature-inspired
 methods and algorithms (e.g. Swarm Intelligence, Membrane and
 DNA computing, Ant Colony Optimization, etc.) for intelligent
 data processing (e.g. Data Mining, Learning from Data, etc.).
 The research will be developed in the framework of the European
 Concerted Action NiSIS (www.nisis.de).

== Position B
Research area:
 Computational intelligence with programmable logic devices.
Research subject:
 The research will focus on the study and implementation of
 machine learning algorithms (esp. Kernel Methods) on Field
 Programmable Gate Arrays (FPGAs) for the realization of
 intelligent embedded systems.

*** GRANT INFO ***

Amount: 1000 Euro/month
Duration: three months
Relocation/travel allowance: 500 Euro (or 1500 Euro
for citizens outside EU)

*** DEADLINE ***

Applications must be received by: 30 September 2005.
Starting date: any date not later than 30 September 2006.

*** APPLICATION ***

Application forms can be downloaded from

http://www.studenti.unige.it/portal/page?_pageid=119,39155&_dad=portal&_schema=PORTAL

or from the web pages of our lab.
Filled forms and documents must be sent by fax to:

Mr. Franco Gabrielli
DIBE - University of Genoa
Via Opera Pia 11A
16145 Genoa, Italy
Fax: +39-010-3532777

followed by snail/express-mail copies.

*** FOR MORE INFORMATION ***

Informal enquires and requests for application forms can
be addressed to:

Davide Anguita
DIBE - University of Genoa
Via Opera Pia 11A
16145 Genoa, Italy
e-mail: anguita@dibe.unige.it
phone: +39 010 353 2800
fax:   +39 010 353 2175 



Article: 89560
Subject: Re: Xilinx ML403
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 19 Sep 2005 09:19:40 -0700
Links: << >>  << T >>  << A >>
> We have Camera Link in a Virtex-II working, so the part can definately
> handle it :-)
> Cheers,
> Martin

Hey thanks. That's what I wanted to hear.

Brad




Article: 89561
Subject: Unknown price difference for xilinx fpga
From: "Hahnsolo" <coreyhahn@gmail.com>
Date: 19 Sep 2005 09:35:03 -0700
Links: << >>  << T >>  << A >>
I have been learning about fpga's for a month now, and stumbled across
the merec web site.

I am looking for a dev board with 20000-30000 LC's and two jumped out
at me.  The DS-KIT-4VLX25LC and DS-KIT-3SMB1500 both are in that range.
 One is a virtex 4 the other a spartan 3.  I cannot figure out why the
spartan board is twice the price of the virtex 4 board.  The spartan
has only 5k more lc's while the V4 has more Dsp/multiplier units and
>twice the block ram.  The boards seem comparable to each other in addon features...
I could see some difference due to the 5k LC's, but twice?

http://legacy.memec.com/devkits/americas.shtml
http://www.xilinx.com/products/tables/selector/index.htm

What am I missing?


Article: 89562
Subject: Re: Is a CPLD appropriate for this triple PWM application?
From: they call me frenchy <solarfrenchyNO@SPAMhouseofharmonystudios.com>
Date: Mon, 19 Sep 2005 12:38:04 -0400
Links: << >>  << T >>  << A >>
On Fri, 16 Sep 2005 23:06:05 +0200, "Falk Brunner"
<Falk.Brunner@gmx.de> wrote:

>For LEDs, PWM is just as good as PDM. PDM has the advantage that you can use
>lower clock frequencies, but this is not a real advantage.
>
>Regards
>Falk
>
>

In battery powered applications I was under the impression that
lowering the clock frequency was one of the main keys to saving
precious power.  Also, the fact that PDM uses less logic resources
than does PWM further tells me that PDM has an edge over PWM for
L..E..D applications.... but I see that most driver ICs for this this
application use PWM pretty much exclusively, hmmmm.

thx,
frenchy

Article: 89563
Subject: Re: Xilinx ML403
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 19 Sep 2005 09:40:13 -0700
Links: << >>  << T >>  << A >>
> And this is where we get off the pre-canned design examples and it
> becomes an "excerise left to the user"....

Are the examples written in VHDL or Verilog?

Thanks,

Brad Smallridge




Article: 89564
Subject: ISE 7.1i incremental synthesis
From: bkuschak@gmail.com
Date: 19 Sep 2005 10:09:17 -0700
Links: << >>  << T >>  << A >>
I'm trying to get incremental synthesis working with the Xilinx tools,
ISE 7.1i.  I applied the most recent service pack, 7_1_04i_lin.zip
which was supposed to fix a fatal bug with this feature.  However, I
still cannot get it to work.  Has anyone had any luck with this?

My .xst file contains these options (along with many others):
 -enable_auto_floorplanning incremental_design
 -uc project.xcf

My project.xcf file contains one line:
 MODEL "top" incremental_synthesis=yes

XST reports the following error:
Reading constraint file project.xcf.
ERROR:Parsers:53 - Error found while parsing the end of the constraints
file.  Check the last entry in the constraint file for valid syntax.
ERROR:Xst:1338 - XCF parsing failed.

The Xilinx docs seems to indicate this should work...

Strangely, even after the service pack, xst still reports the following
version.  Perhaps the sp4 didn't upgrade it correctly??
 bash-2.05b$ /opt/xilinx/bin/lin/xst --version
 Release 7.1.02i - xst H.42

-Brian


Article: 89565
Subject: Re: Xilinx ML403
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Mon, 19 Sep 2005 10:23:44 -0700
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
>>And this is where we get off the pre-canned design examples and it
>>becomes an "excerise left to the user"....
> 
> 
> Are the examples written in VHDL or Verilog?

Ummm, how about in EDK project files (aka MHS)?

Almost all of the IP peripherals that are shipped with EDK are written
in VHDL to handle the necessary parameterization.  You can output the
system generated logic that stitches the PowerPC and peripherals together
in either VHDL or Verilog.  And then of course there's the C or C++
software, drivers and libraries that runs on the PowerPC and pulls the
data from one peripheral and pass it to another.

Since your original request was to use the USB interface to write a
register element in the design.  You could take the USB-to-LCD design
that I mentioned before, open the project in EDK, remove the OPB LCD
peripheral and replace it with a bare bones OPB IPIF peripheral and
tie the write and read buses to your register, modify the software to
write the USB data new memory location, resynthesize, place and route
and try it out on the ML403.

Ed

Article: 89566
Subject: Reprogramming FPGA over PCI???
From: john.orlando@gmail.com
Date: 19 Sep 2005 11:51:28 -0700
Links: << >>  << T >>  << A >>
Hello,
I am working on a new project with a Xilinx FPGA (Virtex 2 or Virtex
4...TBD) on a PCI card (actually, a PCI Mezzanine Card (PMC), which is
the PCI interface in a slightly different form factor).  Anyway, in
architecting this project, we are discussing how to re-configure the
FPGA from the host machine (in this case, a Processor PMC card running
Linux that will be doing the PCI bus enumeration).  Solutions we have
discussed would be to have the ability to write to a PROM through
custom logic through the PCI bus, and then allow the FPGA to boot from
this PROM.  We have also big-banged the serial-loading protocol in the
past from an ARM processor directly connected to the FPGA, but not over
PCI.

However, with our forray into PCI, being able to load the FPGA through
the PCI bus is quite attractive.  Obviously, if the FPGA is providing
the PCI bus interface, we would have the chicken-before-the-egg
syndrome (i.e., no PCI interface to load the FPGA since the PCI
interface is IN the FPGA).  So what about using dedicated PCI bus
interface chips?  These seem to provide a PCI interface on one end, and
a memory-interface on the other, making them pretty simple to use.  But
I still don't see how this will bring the ability to re-program the
FPGA image.

I don't need to do it on the fly while the system is up and running; I
would simply like to be able to, at power up, have the Processor PMC
card open a bitstream file it has on its local file system, dump the
bitstream down to the FPGA over the PCI interface, and then have the
FPGA start in its normal user mode.

I've looked around a bunch and people are certainly doing this.  But I
can't find many good explanations as to how its working.  Are they
bit-bangging JTAG???

Any help is appreciated...

TIA,
John O.


Article: 89567
Subject: FPGA's in bulk and pricing
From: "jai.dhar@gmail.com" <jai.dhar@gmail.com>
Date: 19 Sep 2005 12:08:54 -0700
Links: << >>  << T >>  << A >>
I am posting this again because I don't think my previous one went
through, so my apologies if it did and I lost it... I am looking for
pricing on Cyclone FPGA's in the 10-20 Quantity range. My usual
supplier is Digikey since I'm in Canada, but it costs $50 for a EP1C240
Cyclone, which I think is a lot. What do you guys normally pay for
FPGA's, and where can you get them at some volume discount?


Article: 89568
Subject: Simulation : EDK
From: "EDK Simulation" <cybershakith@hotmail.com>
Date: Mon, 19 Sep 2005 12:09:56 -0700
Links: << >>  << T >>  << A >>
hi,,

I am trying to generate simulation for a edk project. I download the newest MXE files from the xilinx.com and ran Generate Simulation HDL files.

I get the follwing error msg

C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\hdl\vhdl\microblaze_ isa_be_pkg.vhd is distributed by Xilinx encrypted and will not be read by any simulator. Please use compedklib to setup the EDK precompiled libraries and provide the path to them using the -E switch.

But when I try manual compilation using the compedklib, it says for ModemSim XE, use the precompiled libraries..

Any suggestions to get around this?

My setup is EDK7.1.2 + Modelsim Xe starter 6.0a

Cheers Shakith

Article: 89569
Subject: Re: Is a CPLD appropriate for this triple PWM application?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 20 Sep 2005 07:36:25 +1200
Links: << >>  << T >>  << A >>
they call me frenchy wrote:
> On Fri, 16 Sep 2005 23:06:05 +0200, "Falk Brunner"
> <Falk.Brunner@gmx.de> wrote:
> 
> 
>>For LEDs, PWM is just as good as PDM. PDM has the advantage that you can use
>>lower clock frequencies, but this is not a real advantage.
>>
>>Regards
>>Falk
>>
> In battery powered applications I was under the impression that
> lowering the clock frequency was one of the main keys to saving
> precious power.  Also, the fact that PDM uses less logic resources
> than does PWM further tells me that PDM has an edge over PWM for
> L..E..D applications.... but I see that most driver ICs for this this
> application use PWM pretty much exclusively, hmmmm.

  A minus of PDM, is there are more edges, and thus more EMC issues....

  Because Microcontrollers target wider markets, and have timers
with capture/compare from way back, they almost all use PWM.
  In terms of uC die area, the difference is not significant.
  However, (just to keep you on your toes), a few use a mix of PWM
and PDM, and we have done a design that used a UART to
generate PWM+PDM DAC output.


-jg


Article: 89570
Subject: Re: how to set OPB EMC for flash use?
From: "joe4702" <joe4702@hotmail.com>
Date: 19 Sep 2005 13:02:30 -0700
Links: << >>  << T >>  << A >>
These settings worked for me.
I don't know if they are optimal.

 PARAMETER C_MEM1_WIDTH = 32
 PARAMETER C_MEM1_BASEADDR = 0xff000000
 PARAMETER C_MEM1_HIGHADDR = 0xff7fffff
 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 90000
 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 90000
 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 100000
 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 100000
 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 50000
 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 0
 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 0


Article: 89571
Subject: Re: Xilinx ML403
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 19 Sep 2005 13:18:06 -0700
Links: << >>  << T >>  << A >>
Hmm. Sounds a bit complicated.

I was thinking of starting without the OPB because there seems to be
a learning curve there.  I take it that there is already a Cypress program
that communicates to the OPB and PowerPC.  If I want to communicate
directly to the Xilinx fabric, is there an example program to do this, and
does it fit into the Keil compiler linked-4K-byte free evalutation?  It
seems to me that if you could get a report out of a chosen BRAM you
could look inside the chip somewhat like ChipScope.  Although ChipScope
is another tool that I don't have.

> Since your original request was to use the USB interface to write a
> register element in the design.  You could take the USB-to-LCD design
> that I mentioned before, open the project in EDK, remove the OPB LCD
> peripheral and replace it with a bare bones OPB IPIF peripheral and
> tie the write and read buses to your register, modify the software to
> write the USB data new memory location, resynthesize, place and route
> and try it out on the ML403.
>
> Ed 



Article: 89572
Subject: xilinx ML310 board PCI DMA problem
From: "laoshan.zb@gmail.com" <laoshan.zb@gmail.com>
Date: 19 Sep 2005 14:01:24 -0700
Links: << >>  << T >>  << A >>
Hi! all!
I have a problem with runing PCI DMA example provided by Xilinx EDK
install CD on ML310 board. The file xpci_example_level_1.c try to write
destination, source , byte length into DAM control register start at
0x3d000000, but whenever it do that it cause OPB bus error, i
appreciate any help on this. Also another example,
xemac_intr_simple_dma_example, can't even be compiled as some
parameters are not defined, and search in all files, i didn't find it.
So what can i say about Xilix?


Article: 89573
Subject: Re: Generating Modelsim Verilog resource libraries - pointers/questions
From: Garrick <gk@garrickk.net>
Date: Mon, 19 Sep 2005 21:21:30 GMT
Links: << >>  << T >>  << A >>
Kim, thanks for the information.  I have a few follow up questions, but 
I realize now that I should have specified that I am using Modelsim XE, 
the free simulator for Xilinx.  I thought the only limitation was 
project size, but I am unable to compile a resource library with a 
-nodebug flag, and would be unable to use a -nodebug compiled library if 
one was supplied to me by a 3rd party.

Since many of our customers are using Modelsim XE, I won't be able to 
use -nodebug even if we had a purchased license.

Kim Enkovaara wrote:
> As a user of many protected codes, please use the new "vlog +protect"
> functionality. It is supported from Modelsim 5.7 onwards. It's much
> easier for the customers (for example name clases are easier to handle).
> And be prepared to offer many different versions of the library if
> you use precompiled libraries, because -refresh command works only from
> older to newer versions. Everyone is not using the newest and greatest
> versions of the simulator. For example I don't like the new 6.x GUI and
> in many designs 5.8 is faster and consumes less memory.

It appears as if the `protect compiler directive is supported (at least 
initially) in Modelsim XE.  I've placed `protect/`endprotect in my 
verilog modules and compiled them using the +protect flag.  They compile 
fine with no warnings.

However, it doesn't appear as if anything is being protected.  I've 
tried putting the `protect/`endprotect both within the module and around 
the modules, and have even not used the +protect flag during 
compilation.  The compiled libraries, when used by another project, show 
all of the internal signals equally.  Perhaps Modelsim XE doesn't 
support `protect or nodebug, but doesn't flag a warning with protect and 
just doesn't do anything about it.  It would be nice to have some 
protection.

Thanks for any help/suggestions,
Garrick

Article: 89574
Subject: Re: Reading a PAL fusemap with a microscope
From: Alex Freed <alexf@mirrow.com>
Date: Mon, 19 Sep 2005 14:46:00 -0700
Links: << >>  << T >>  << A >>
> 
> Can you give some details on what you did for the CompactFlash interface? 
Not much. I bought a CF to IDE adapter - just 2 connectors and some 
wires as CF can work in true IDE mode. Interfacing a 3.3 v IDE interface 
to an FPGA is rather trivial. I made the CF respond to i/o addreses 
belonging to a "card" is slot 3. On the software side did a simple 
ProDOS driver.
Not my idea and I was not the first - I found a CF interface for an 
Apple 2 on the 'net. The implementation was mine.


> Did you develop your own IDE controller?
IDE doesn't need a controller. An "IDE controller card" for a PC is just 
a bunch of bufferes.

> 
> Also, you mention USB 2.0.  How did you handle the hardware/software issues
> with getting that to work?

I have a USB board form Digilent with a parallel interface that is 
connected to the FPGA. They provide USB drivers. A state machine inside 
FPGA to talk to it was not all that hard to do.

> 
> Very impressive design!
Thanks.
> 
> You could consider putting some more screen shots or something up.
Maybe later when I have time.
> 
> Thanks,
> Ram.



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search