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Messages from 11500

Article: 11500
Subject: Example Code
From: "G. R. Jeffrey" <jeffrey@cs.utk.edu>
Date: Wed, 19 Aug 1998 12:15:05 -0400
Links: << >>  << T >>  << A >>
I am new to the fpga world. I have some Altera flex10k devices that I
want to use to implement a routing protocol.

Does anyone know where I can get some (simple) example codes that use
the ISA bus to interact with fpga/cpld devices. I spent all of
yesterday, unsuccessfully, trying to write/read to/from ram on a device.

Also, is there a web site that explains the ISA bus signals?

Thanks,

Gersham Jeffrey.

Article: 11501
Subject: Re: Example Code
From: Nicolas Matringe <nicolas@dot.com.fr>
Date: Wed, 19 Aug 1998 18:48:47 +0200
Links: << >>  << T >>  << A >>
G. R. Jeffrey wrote:
> 
> I am new to the fpga world. I have some Altera flex10k devices that I
> want to use to implement a routing protocol.
> 
> Does anyone know where I can get some (simple) example codes that use
> the ISA bus to interact with fpga/cpld devices. I spent all of
> yesterday, unsuccessfully, trying to write/read to/from ram on a device.
> 
> Also, is there a web site that explains the ISA bus signals?

The ISA bus is not very complicated, although it's an incredible mess.

For the signals, have a look at http://www.gl.umbc.edu/~msokos1/isa.txt
I'm afraid you won't find the timing specs on the net (spent a lot of
time and never found any), but some 386-compatible microcontrollers
implement an ISA-like bus. There are timings in the data-sheets.
Try for example the AMD Elan SC300

Nicolas MATRINGE                   DotCom SA
Conception électronique            16 rue du Moulin des Bruyères
Tel: 00 33 1 46 67 51 00           92400 COURBEVOIE
Fax: 00 33 1 46 67 51 01
mail reply : remove one dot from the address (guess which :-)
Article: 11502
Subject: Re: Manchester decoding
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 19 Aug 1998 09:54:22 -0700
Links: << >>  << T >>  << A >>
Reza Bohrani wrote:

> Does anyone know of any VHDL implementation of the decoding of a
> manchester-encoded bitstream. If no does anyone have any suggestion of
> how
> to attack teh problem?
>  

I published a very simple circuit ( in schematic form, not in VHDL) in
the Xilinx quarterly magazine XCELL, in 1995, issue number 17.
You can get it on the Xilinx web site by either clicking on the search
button and typing manchester decoder, or you go straight to

http://www.xilinx.com/xcell/xl17/xl17-30.pdf 

Peter Alfke, Xilinx Applications 

Article: 11503
Subject: 30 new pages of embedded products + UK Embedded Show
From: Chris Stephens <sales@computer-solutions.co.uk>
Date: Wed, 19 Aug 1998 18:07:21 +0100
Links: << >>  << T >>  << A >>


    The UKs best embedded development tools site just got BETTER
    ------------------------------------------------------------

COMSOL has added over 30 new pages to its web site.  We now cover 80 
different microprocessor families.

                http://www.Computer-Solutions.co.uk

New products include:
        
        Embedded C & C++ for Motorola micros

        Flash and ROM Emulators

        Super fast Ethernet BDM Emulators

        x86 and Power PC Real Time Executives        

        Embedded TCP/IP, Web Server and Browser

        Embedded DOS & W95 Compatible file system

along with all the old favorites

        In-circuit emulators
        Assemblers
        C & C++ compilers
        Real-time executives
        Software simulators
        186-486 linkers
        Remote debuggers
        EPROM emulators
        EPROM-PAL-GAL-micro programmers
        GANG programmers
        CASE tools
        Forth systems from chips to Windows
        RS232 Debuggers
        PC instruments (Logic Analysers & DSOs)

-----------------------------------------------------------------------
If you would like information on any of our current products, or to be
emailed with info on new embedded products please email to the address 
below
------------------------------------------------------------------------

If you would like an entry ticket to the Embedded Systems Exhibition at 
Ascot, Berks on the 8th & 9th September send me an email

Regards,  Chris

-----------------------------
Chris Stephens                         E-mail: sales@computer-solutions.co.uk
Computer Solutions Ltd.                Phone & Fax: +44  (0)1 932 829 460
1a New Haw Road, Addlestone,
Surrey, KT15 2BZ  England              http://www.Computer-Solutions.co.uk   

For the largest range of embedded microprocessor development tools in the UK
Article: 11504
Subject: Re: Linux Toolz
From: rleir@my-dejanews.com
Date: Wed, 19 Aug 1998 17:58:50 GMT
Links: << >>  << T >>  << A >>
In article <35DA98AF.7104446@virgin.net>,
  tony.cooper@virgin.net wrote:
> Does anyone know where I can source the following tools ALL running
> under LINUX (Direct or under Xwindows).
>
> The TMS320C series of tools (ie. the C compiler, the assembler, linker
> etc etc)
> The Xilinx FPGA Implementation tools.
> The XDS510 JTAG Emulator tools.
>
> I have all the above for Windoze, but I have just about had enough of
> this awfull O/S... I would like some stability in my life, and I am
> fairly sure that LINUX is the way to go. (I used to run Linux all the
> time - it never once crashed on me).

The WINE windoze emulator will likely run those tools on Linux, then you can
use XEmacs and jump to the next compile error. cheers -- Rick



-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11505
Subject: Re: Help on Xilinx !
From: "John L. Smith" <jsmith@visicom.com>
Date: Wed, 19 Aug 1998 14:39:21 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------6ABDE92354A7FF0401DC9D51
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

watm wrote:

>     I designed the blocks in the shematic, simulated them, checked that
> everything was like i expected to be and ....  when i loaded the code
> into the FPGA, nothing happened the expected !

When you simulated, was that a functional simulation ( no device orrouting
delay ), or a timing simulation ( speed back-annotated from
the placed and routed device ) ? It makes a huge difference,
particularly with high-speed synchronous designs and most
asynchronous designs.



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email;internet: jsmith@visicom.com
title:          Principal Engineer
tel;work:       781-221-6700
tel;fax:        781-221-6777
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--------------6ABDE92354A7FF0401DC9D51--

Article: 11506
Subject: Re: Newbie seeks cheap fun w/FPGAs
From: "Tom Burns" <tomburns@worldnet.att.net>
Date: 20 Aug 1998 02:49:19 GMT
Links: << >>  << T >>  << A >>
A reduced version of Altera's Max+Plus II software is available free for
the downloading and it handles several parts, I believe including the FLEX
10K10, a 10,000+ gate SRAM-based device.  You may have to make the PCB that
uses it, but you can download the FPGA program to it over the PC's serial
or parallel ports.  You don't have to buy the BitBlaster or ByteBlaster
download cables; just download the data sheet for them - you can make
either yourself from the info in the datasheet.

Lattice also has free tools but the devices supported for free are more
toward their low-end parts (< 5K gates).

Good luck

mail83870@pop.net wrote in article <6qtirr$ees$1@nnrp1.dejanews.com>...
> 
> 
> Can anyone recommend a little tinkertoy kit ( no less than oh, say, 10K
> gates, tho' ) that I can slap into my intel box ( linux/win* ) and play
> with.  Bonus points for neat graphical interface.  I am hoping to spend
> darn little.....
> 
> Thanks in advance for any help....
> 
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
> 
Article: 11507
Subject: Max+Plus II Ver 8.3 compiler problems?
From: "Tom Burns" <tomburns@worldnet.att.net>
Date: 20 Aug 1998 03:21:41 GMT
Links: << >>  << T >>  << A >>
Has anyone out there had problems compiling a design in ver. 8.3 and found
that some of the logic in the .gdf doesn't show up in the Floorplan Editor?

I am new to Max+Plus II, so this could be a simple case of cockpit error.  
However, Altera's tech support had no explanation after reviewing the
design files.

I have the SIMPLEST thing you can make - a 16-bit input latch feeding data
to a 16-bit bidirectional data bus in a FLEX part.  The thing compiles
fine, but when I look at the Floorplan editor, only the lower byte exists
in logic.  All input pins and bidir pins are allocated, but no fan-in shows
up for the upper byte of the latch, and no logic utilization shows for the
8 FF's for the upper byte.  Go figure.

Also, any problems with Max+Plus II on NT4.0, or editing it briefly on a
Win95 machine and going back to NT?

Thanks for your feedback.

Tom Burns
tomburns@worldnet.att.net


Article: 11508
Subject: "Mike Barnicle, Plagiarism, & DAC'98" (Part 1 of 2)
From: jcooley@world.std.com (John Cooley)
Date: Thu, 20 Aug 1998 06:44:49 GMT
Links: << >>  << T >>  << A >>

     [ part 1 of 2: the conference itself & mostly front-end EDA tools ]


    !!!     "It's not a BUG,                           jcooley@world.std.com
   /o o\  /  it's a FEATURE!"                                 (508) 429-4357
  (  >  )
   \ - /              The Fifth Annual ESNUG/DAC Awards:
   _] [_             "Mike Barnicle, Plagiarism, & DAC'98"
                                   - or -
    "106 Engineers Review DAC'98 in San Francisco, CA, June 15-19, 1998"

                               by John Cooley

        Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
      Legal Disclaimer: "As always, anything said here is only opinion."


           "It is a tale, told by an idiot, full of sound and
            fury, signifying nothing."

                - from Shakespeare's "MacBeth"


 Gentle Readers:

 Living under the Big-Brother-Is-Watching, Politically Correct shadow of
 the Boston Globe (as I do because I live in Eastern Massachussetts), a day
 now doesn't go by where you can't see on TV or read in the press some new
 preachy, self-rightous "journalistic integrity" rant concerning how the
 columnist Mike Barnicle plagiarised eight jokes from comedian George
 Carlin's book, "Brain Droppings".

 And you want to know what *I* think about this?  I very sarcastically say:
 "Big deal.  Big fucking deal.  Who the hell cares?"

 And why I say this is because when I write, I haven't penned an original
 idea in months and I really don't intend to change that way of thinking any
 time soon!  (In fact, I sometimes even go *out* *of* *my* *way* to avoid
 having new ideas!)  Why?  Because truely new ideas are a lot of work to
 cook up, and, most of the time, they turn out to be half-baked anyway.
 God! -- I can't tell you the number of times, as a man, where I've had some
 woman in my life (whether it be my girlfriend-du-jour, me mum, a friend, or
 a co-worker) tell me how my innovative approach to some issue was "in
 error", "wrong", "insensitive" or just plain "dumb-ass stupid".  My male
 married friends tell me the three stock phases that keep them out of the
 divorce courts are:

             1.) "Honey, I'm sorry, I was wrong."
             2.) "Babes, I made a mistake; you were right."
             3.) "No, Sweetie, you don't look fat in that dress."

 Get out of the personal relationship domain, and, say, try bringing up new
 ideas at work, and it gets worst!  Now your female *and* male co-workers,
 bosses, associates, competitors, and even random-people-off-the-street-who-
 don't-even-know-you will all collectively gang up to *publically* tell you,
 in no uncertain terms, how *YOUR* new idea was so totally wrong, so totally
 NOT the solution, and so totally OUT-TO-LUNCH.  I'm not kidding here.  Human
 societies, on RARE occassion, will *sometimes* reward the crackpots who go
 against the herd *if* the herd happens to decide *at* *that* *very* *moment*
 it wants to go in their new direction -- otherwise the *punishment* for
 thinking differently will be swift and sure.  And either way, they're still
 seen as crackpots.

 Some successful crackpots were: Martin Luther (the Protestant Reformation),
 George Washington (the American Revolution), and Bill Clinton (established
 that U.S. Presidents can do *anything* [ including chubby interns ] as long
 as the U.S. economy is thriving).  Some examples of failed crackpots: the
 thousands of "heretics" burned at the stake for disagreeing with the Church;
 the millions of "terrorists" who fought on the wrong side of revolutions;
 and the millions of husbands and wives *immediately* divorced after being
 caught cheating.  And there's even an "Honorable Mention" group -- crackpots
 who changed the world but paid for thinking differently anyway: Jesus Christ
 (formed new religion; died on cross), Joan of Arc (liberation of France;
 burned at stake), Socrates (founded Western philosophy; convicted pedophile
 forced to drink poison), and again, Bill Clinton (two term US President
 during sizzling ecomonic boom; forced to remain married to Hillary Clinton).

 So, the message here for anyone with half a brain is clearly: "Keep your
 yap shut and stop using that half of your brain that does work -- if you
 don't want to be taking some SERIOUS risks with your life, liberty, and
 pursuit of happiness!"  

 The real wisdom *I've* found that works comes from the newspaper columns
 "Hints From Heloise", "Ann Landers", "Dear Abby", and "Miss Manners" -- and
 that wisdom is it's always best to print *OTHER* people's letters, their
 quotes, their problems with their solutions, and their new ideas _waaaaaay_
 before you even think of toying with the idea of presenting your own
 original material.  To me, it's obvious that Mike Barnicle knew this smart
 money approach to writing columns when he published George Carlin's jokes.

 I do it, too, with the 1,000 (or so) user letters I republish in ESNUG
 every year and even in this DAC'98 Trip Report.  In this very DAC'98 Trip
 Report you'll be lucky if you'll get 2 percent original material from me;
 the remaining 98 percent of the ideas, opinions, and even the explainations
 of how the new EDA technologies supposedly work have all been unabashedly
 clipped/quoted/stolen by me from the 106 *other* DAC'98 Trip Reports *other*
 people wrote when they returned home.  This particular DAC Trip Report
 doesn't just emit a faint odor of plagiarism -- it reeks of it!  And I wish
 to personally thank Mike Barnicle and George Carlin for finally making this
 style of column writing now publically acceptable!

 Or at least that's the way I see it.  I could be wrong.


    "Hypothetical Question: If married man speaks out loud in a forrest
     and there's no woman there to hear him, is he still wrong?"

         - joke overheard in local bar

    "It's a good thing Bill Clinton finally confessed.  The investigation
     was getting tough when they DNA tested that dress...  because they
     just found out that all the people from Arkansas have the same DNA."

         - another joke overheard in a local bar



 LIVING LIFE LARGE:  Reflecting the economic boom going on in the overall
 U.S. economy, the total DAC'98 attendance grew by about 25 percent compared
 to DAC'97.  That is, DAC'97 had 17,398 total attendance; DAC'98 had about
 21,675 total attendees (+/- 50 people).  But that tells only part of the
 story because total attendance includes EVERYONE -- professors, employees
 of EDA vendors, guests, *and* customers.  An even larger growth of roughly
 41 percent (from DAC'97 to DAC'98) happened if you look at the numbers for
 the DAC "Technical Attendees" -- i.e. the people actually interested in
 *buying* the EDA tools being exhibited.  DAC'97 had 7,387 technical
 attendees; DAC'98 had 10,488 technical attendees.

 Comparing this year's and last year's exhibitor list yields DAC'98 grew
 by 21 percent with 38 new companies showing -- if you just counted names
 on the exhibitor list.  Do a little digging and you'll find that 31 of
 those exhibitors were semiconductor houses -- so, looking at totals, the
 number of *EDA* exhibitors has actually remained at around a constant 190.
 But that 190 has had 40 vendors disappear and 44 new vendors replace them;
 making the yearly turnover of EDA companies of around 22 percent.  Of those
 who have disappeared, some (like Cascade, Compapass, CCT, & Wellspring)
 were bought out by the bigger EDA fish; a few (like Speed Electronic, &
 KBS) simply went out of business; a couple did name changes (like Indus);
 and, for a good number of the MIAs (like DS Diagonal, Emultek, Nextwave,
 Neuw, & Technical Data Freeway) it's not widely known why they no showed.

    "We believe that genuine technology innovation in the EDA market emerges
     from focused startups rather than the major public players.  One
     non-scientific measure is the presence of at least 40 new startups at
     DAC'98 compared with a year ago in DisneyLand."

         - from a financial analyst's report of DAC'98

    "The best giveaways were Dilbert toys from a bogus company whose demo
     I only virtually observed (luckily).  My daughter will be pleased!"

         - a well-known Silicon Valley ASIC designer


 MONEY _CAN_ BUY YOU LOVE:  For the past two years, the DAC Plenary Sessions
 (otherwise commonly known as the "DAC CEO Panels") have been totally lame-o
 events.  Prior to then, it was completely different.  For example, at
 DAC'95, Joe Costello (then CEO of Cadence) blurted out: "We're stuck in a
 fixed-pie model.  Have you seen three big dogs hovering over one bowl of
 dog food?  It's not a pretty picture."  Aart De Geus (then CEO of Synopsys)
 came back with: "If you think of yourself as a dog, you deserve dog food!"
 Alain Hanover (then CEO of ViewLogic) said about his rebellious Chronologic:
 "Our founding forefathers guaranteed us the right to life, liberty, the
 pursuit of happiness and the right to sue each other."  Gerry Hsu (then CEO
 of ArcSys) took pot shots at Cadence by describing how bureaucratic it was
 when he used to work there.

 But amougst these rancorous exchanges we also got to openly discuss EDA
 bugs, interoperability issues, pricing models, EDA vendors becoming
 consulting houses, Verilog vs. VHDL, and much more.  Yes, sometimes egos
 were bruised, and sometimes people laughed -- yet we all walked away
 knowing a bit more about the other guy's moccassins than before the event.

 But, for the past two years, the DAC CEO panels have become controlled,
 scripted affairs where more and more, less and less is being said.  They've
 replaced actual EDA users on the panel with academics and CEO "users" who
 use bullshit management words like "paradigm shift", "resources", and "P&L
 statements" in their day-to-day vernacular instead of engineering TLAs like
 "ECO", "LRM", or "BFD".  The audence is no longer allowed to ask questions.
 And the soft, safe, fluffy questions asked of the CEOs were asked weeks in
 advance so their staffs could craft long-winded soliloquies carefully
 showing how *their* company's approach would save the day.  Even a problem
 child CEO like Gerry Hsu of Avant! (who has been embroilled in a long legal
 spat with Cadence) was nowhere to be seen -- lest he accidently cause a
 free exchange of ideas to happen.

 "Why are they doing this?", you ask.  The answer is Wall Street.  Never
 before has DAC seen so many investment bankers, analysts, and financial
 types running around in an *engineering* conference.  They're all trying
 to get the inside scoop on chip design software.  And the EDA execs are
 trying to parlay that interest into higher stock prices by now *appearing*
 to play nice with each other in public.  Frank discussions with EDA CEOs
 are a thing of the past now that Wall Street is here.

 The Beatles were wrong with their song "Money Can't Buy Me Love".  In the
 EDA industry, we all love each other.  Honest.  Money *can* buy you love
 these days.  Or at least on DAC CEO panels it can.


    "One other panel was of note was Gary Smith's annual DataQuest briefing
     Sunday night where he reported DQ was forecasting a 10-15% downturn in
     EDA tool sales.  Gary indicated that this was due to the users not
     believing the tools coming out could handle leading edge technologies
     and are slowing down their purchases."

         - an anonymous EDA executive

    "Thirty Five Years of Design Automation Panel: It was an interesting
     discussion but there were no real highlights.  They showed some history
     and said their predictions of the future (from the past) were so bad
     that they did not want to do it again.  They discussed tools/methods
     and said (manager version here):

	           Tools have got to get better; so they will. 
	           Engineers have got to get smarter; so they will. 
	           IP happens. 
	           Any questions?

         - a Telecom designer



 TRYING TO MAKE FORMAL BIG: Hoping to capitalize on the severe need for
 verification engineers versus design engineers (with some estimates putting
 the need as high as 5 verifiers for every designer) this year's DAC was
 flooded with new Formal Verification tools all promising A Golden New Way
 To Debug Designs.  There are basically three kinds of formal verification
 tools: equivalence checkers (EC), model checkers (MC), and pie-in-the-sky.
 EC is the most common type of formal verification tool.  Two of the EDA big
 boys, Synopsys and Cadence, are even pitching their brand of EC to be used,
 with their brand simulation and static timing analyzers (of course) as "next
 generation sign-off".  And it's widely rumored that Mentor R&D is in beta
 with an EC tool and a static timing tool to follow suit.

    "The demo of Prime Time and Formality was quite compelling.  (Motive was
     not represented in the booth, verifying that Synopsys is trying to kill
     it ASAP in favor of Prime Time.)  The interface for Prime Time is very
     user friendly, with wizards and tabbed dialog boxes and spreadsheets
     (cribbed from the interface of Synopsys's PC-based FPGA Compiler).
     All this generates scripts that are compatible with the commands that
     control Design Compiler.  Prime Time also has statistical analysis
     tools that are graphically tied into the Design Analyzer generated
     schematics which helps you quickly locate the root cause of timing
     problems.  Formality, a logic equivalency checker, also has quite a
     slick front end, and it is also tied into Design Analyzer.  Their demo
     showed how Formality could be quickly used to verify a hand-modified
     netlist (the netlist was modified to correct a timing fault caught by
     Prime Time).  As a corollary, Formality could be used to check blocks
     that have been implemented in schematics by hand (because of speed or
     efficiency problems with synthesized logic) against the RTL code."

         - a design engineer from a large semiconductor house

 Technically, an Equivalence Checker (EC) works by comparing a golden design
 (RTL or gates) against another design that's supposed to be functionaly
 the "same".  EC can easily deal with whole projects (500k - 1M gates)
 overnight, but it depends heavily on both designs being structurally
 simular.  Designs that are structurally different generally have to be
 broken into 10k gate modules for EC to work.  Most EC tools support VHDL,
 Verilog and EDIF.  Set-up and day-to-day usability are still issues, but
 debugging is really what separates the tools.  Even though EC is used in
 parallel with simulation at most of the bigger semiconductor companies, EC
 tools are still overpriced for most engineers' desktops ($50k to $150k);
 they have to drop to around $20k to go to main stream...   Assuming the
 $12.5 million Formal Verification market (1997 Dataquest est.) really does
 go main stream.  

    "If you draw a big circle to represent verification, simulation as a
     weapon still fills 90% of the job.  Formal verification maybe covers
     5%-15% and again it is hard to measure how much it overlaps with the
     other tools.  For what it costs, it doesn't do much."

         - A West Coast design engineer


    "ASIC flow breakdown:

        Design and block level verification:            27%
        Simulation:                                     46%
        Emulation:                                      15%
        Structural checking:                            12%

     Staffing is 2:1 of verification engineers to design engineers."

         - Al Silbert of Nortel (on the Formal Verification Panel)


    "Chrysalis' Design Verifyer (EC) despite being hard to set up and
     expensive, has a nice Tcl interface for user programmability, and a
     good schematic based debugger.  It has the advantage of being the
     oldest, most debugged EC tool on the market.  They're also trying
     for MC, in a limited but pragmatic way.

     The great advantage Formality from Synopsys (EC) has is it integrates
     nicely into a Design Compiler based design flow.  In addition, Formality
     has one of the best EC debugging interfaces.  The criticism that
     Formality and Design Compiler may contain shared code misses the mark
     slightly, but that's a discussion too long to go into here.

     Cadence's Affirma (EC) is a "me, too" product.  It integrates FV into
     their simulation environment, which makes for only one user interface
     to learn.  Their use of Composer to display a schematic provides a
     familiar user interface, but doesn't allow the user to use the
     schematic to explore the design.

     Abstract (EC and MC) and Verysys (EC and MC) are both repackaged
     Siemens technology.  These tools are not as easy to use, nor as easy to
     integrate into a flow as their major competitors.  Verysys' debugging
     interface to their EC tool that is very competitive, though.  It's
     rumored that Intel has bought stock in Abstract, but that hasn't made
     an impact on their tools yet.

     Avanti's Lynx (EC) is just VFormal from the Compass take-over, & hasn't
     been touched since the take-over.  Verplex (EC), Formalized Design
     (EC & MC) and Fujitsu (EC & MC) are all very late newcomers this year
     to the market.  Mentor is also rumored to be working on an EC tool,
     too.  It's doubtful how any of these tools will fare in this already
     crowded market."

         - Simon Read, a Formal Verification consultant & ex-developer


    "Equivalence Checking is now so mature that they were almost selling
     it from hand carts out in the street like it was hotdogs.  Not so
     sure who was buying though."

       - a European design engineer


    "a) Chrysalis: Oldest, overpriced.
     b) Synopsys Formality: Best interface with Synth and timing
     c) Verisys: Looks promising, but nothing stands out
     d) Abstract FV: Cool debug with auto simulation and waveform output
     e) Bell Labs: Formalcheck V: This looked the best last year
     f) Formal Verification: Small company in the back room

     Too many players for such a niche market. Hopefully one or two of
     them will "do an MTI" and have a useable product at a low price and
     cause a fallout and a launch into mainstream use."

         - Peet James of Qualis Design


 Model Checking (MC) answers "what if?" and "is it possible that?" questions
 about a single design.  MC only works on small designs of about 300
 flip-flops or less because it suffers from "state explosion" -- the time
 and/or memory needed doubles with every state bit you add.  MC can detect
 and help fix subtle interacting FSM bugs -- which is why engineers like
 about MC -- because it catches bugs that would be hard to catch via most
 simulation runs.  Market-wise, Bell Labs, 0-in, and the DAC'98 newbies
 Silicon Forrest and Formalized Design are all basically home grown MC tools.
 Abstract and Versys are reselling warmed-over MC technology they got from
 Siemens years earlier.  (Oddly, it's rumored that Cadence's Ken MacMillan
 put a *free* model checker out on the Cadence web site.)

    "FormalCheck (MC) from Bell Labs (BLDA) can process larger designs than
     its competitors.  Their graphical user interface has very well thought
     out features to help write & manage queries and novel, useful debugging
     features.  They've added a batch oriented interface for automating
     regression tests.  Let's see how they fare after Cadence buys them."

         - Simon Read, a Formal Verification consultant & ex-developer

    "The Bell Labs, 0-in, and Silicon Forrest (MC) tools are different in
     that they let the user query (or they do directed searches) for very
     esoteric bugs in designs which makes them technologically popular.
     Every engineer secretly frets over that one missed Pentium bug that
     haunts them for the rest of their careers."

         - an East Coast design engineer

    "Formal Verification is still sold as insurance. The sales pitch is
     basically a scare tactic. 'You need this $150K tool, or you may miss
     a bug'.  Engineers love finding these hyper elusive bugs, and can
     get lost in the search for them.  It wastes time and robs from
     mainstream target bug finders like simulation.  Again, it is very hard
     to see if Formal Verification is cost-effective or not."

         - Peet James of Qualis Design

    "The best way to change methodologies is to start slowly, as Synopsys
     did when it came to market with gate-level optimization.  Only later
     did Synopsys move people upstream to RTL synthesis.  Contrast that to
     Silc, which tried to introduce behavioral synthesis in the mid-1980s,
     which turned out to be 10 years too early."

         - Richard Goering of EE Times


 SYNTHESIS GOES FORMAL?  In ancient Greek mythology "centaurs" were creatures
 who were half-human & half-horse.  Other than being novelties, "centaurs"
 never partook in anything of consequence in Greek myths.  The EDA world's
 version of centaurs is "Formal Synthesis" -- a useless beastie that's
 half-formal and half-synthesis.  Normal synthesis works by running
 step-by-step transforms on RTL code to eventually convert it to optimized
 gate level designs.  A typical synthesis transform may be "initial mapping
 of RTL to gates" or "inserting extra buffers according to specific fan-out
 rules" or "doing specific boolean optimizations on logic cones".  Formal
 Synthesis anal retentively ensures that each transform used is "proven"
 mathematically so no possible errors going from spec to gates ever happen.

     "Nobody makes designs with flawless specs.  We sort of craft the spec
      and the design along the way with the verification guys looking over
      our sholders.  We know 90 percent of what we're trying to design going
      in.  It's that last 10 percent that makes designing interesting.  I
      don't want errors in my designs, but the promises and limitations of
      formal synthesis are about as useful as tits on a bull."

         - a design engineer from Research Triangle Park, North Carolina

     "Abstract and Derivation Systems both market formal synthesis tools,
      both claim that their tools allow designers to 'explore the solution
      space'.   To most designers, who are often unskilled in mathematical
      techniques, these tools will 'constrain the solution space' rather
      than simply 'prevent mistakes'.  Formal synthesis is really only
      applicable where a lack of bugs is a paranoid, overriding concern."

         - Simon Read, a Formal Verification consultant & ex-developer


 "IP", YOU PEE, WE ALL PEE ON "IP": Remember how at last year's DAC each EDA
 vendor annoyingly somehow found a way to work the phrase "Deep Sub Micron"
 into their customer pitches?  Well, this year's Most Tired Phrase used at
 DAC was "IP" -- Intellectual Property.  Everyone and their grandmother
 somehow fenagled a way to work *their* product as being somehow absolutely
 *critical* for IP use and/or developement.  "Are you making some IP?"  Call
 Cadence, Mentor, Synopsys, blah, blah, blah, (the list goes on and on) for
 their tools.  "Want to actually *buy* some IP?"  Call Argonaut, Artisan,
 ARM, Aspec, Avanti, Cadence, CAST, CoreEl, CSELT, Denali, Design & Reuse,
 Duet, Eonic, Interra, Mentor, Phoenix, Sagantec, Sierra, Silicon Access,
 Synopsys (and whoever else I've missed.)  And, to make matters worst, now
 all the God Damned foundries and semiconductor houses are getting into the
 same bloody IP game, too!  (2nd try): "Want to buy some IP? "  Call IBM,
 TSMC, Motorola, LSI,...  And, not to be left out of the party, all the
 FPGA/CPLD vendors are sharing in the same terribly unoriginal idea, also!
 (3rd try): "Psst!  Hey, Buddy, Wanna buy some IP?"  Call Xilinx, Altera,
 Actel, Cypress,...   Enough IP already!

    "Great parts produce great vices, as well as virtues."

         - from Plato's fourth letter to Dionysius II, the ruler of Syracuse

    "Parts is parts."

         - the catch phrase to a Wendy's Old Fashioned Hamburger restaurant
           ad campaign of a few years years ago

    "Do you remember a few years ago that televised Republican National
     Convention where the candidates kept strongly supporting 'family
     values' over and over, yet none of them could define what 'family
     values' were?  IP was the 'family values' of [this year's] DAC."

         - a Texas design engineer


    "Personally, I don't get it -- all this hype around IP.  Essentially
     the IP vendors want to be tax collectors.  They want a nickle a chip
     for every chip their IP is in.  We've seen dozens of IP vendors but
     haven't invested in any of them."

         - Mark Stevens of Sequoia Capital, a venture capital firm


    "Cadence had a special meeting for all their big time customers in
     which they were spreading their propaganda of the future of the IC
     industry.  In this meeting they discussed how the future industry
     will require more system integrators than logic designers because of
     the IP industry.  Their projection is that IC suppliers will incorporate
     more third party IP cores and less custom designs.  After they were
     done, several Cadence marketing guys were seated at each table to
     discuss our reaction to their presentation.  At that point several
     people at our table began to turn their theory into swiss cheese."

         - a Lucent engineer

    "Sand Microelectronics: I could not bare to talk to these guys in
     light of all the problems the [name deleted] team has had."

         - an anon design engineer


 IN LAWYERS WE TRUST: Very traumatically at this year's DAC, the IP business
 has run into its very first technological breakdown.  The funny thing is
 that many engineers may have not picked up on this yet.  The Great
 Divide that has separated IP has been how it has been delivered to the
 end customer; it's either soft core IP (like Verilog or VHDL source code
 or netlists) or hard core (like polygon oriented GDS-II files).  Soft cores
 have traditionally had protection/reverse-engineering problems concerning
 how to keep questionable characters from simply copying it, tweaking it a
 bit, and then reselling it as their own unique IP.  To fight this, LEDA's
 Kypton does confusing VHDL-to-VHDL scrambling; Chronologic's VMC converts
 Verilog into unreadable compiled code, and now Topdown offers something
 simular.  But all these solutions each have some technical or business
 Achilles' heel leaving soft core IP vendors still nervously relying on legal
 threats to protect their family jewels.  Conversely, hard cores, being
 essentially polygons, have been much, much harder to reverse-engineer, and,
 as a result, have been intrinsically more secure.  That is, until now...

 Laughingly, the one EDA company most plagued with lawsuits from day one of
 its inception, Avanti, is now widely marketing a tool it got from the
 Compass aquisition called Lynx-LB that REVERSE COMPILES full-custom block
 implementations (i.e. GDS-II files) back into synthesizable Verilog or VHDL
 RTL!  Formalized Design also offered a reverse compiler that reads in EDIF
 or SPICE files and regenerates RTL Verilog or VHDL.  And it's rumored that
 Cadence and Sagantec might be working on something similar.  Ostensively
 such tools are to make design migration of old IP into new applications
 doable -- but now what's to stop a Cadence or Synopsys Consulting Services
 or even your TSMC support engineer from using these very same tools to
 "migrate" your hot IP into their own cache of designs?  Now the hard core
 IP vendors (and now even *anyone* submitting designs to foundries) have to
 do what the soft core vendors have been doing all along: nervously rely on
 legal threats to protect your IP family jewels.

    "Circuit Semantics has a tool called DynaBlock that can take an Hspice
     netlist (extracted from a full-custom layout using Arcadia or Star-RC),
     recognizes functional gates from the transistor connectivity, and
     characterizes the functional gates.  The user gets a gate-level Verilog
     netlist and a Synopsys timing library (*.lib) for the gates in the
     netlist.  This tool is useful to extract functionality and timing
     from legacy cores or hard IP's.  They claim it can process 100k
     transistors in three hours.

     Compared to Avanti's Lynx-LB:

       Dynablock extracts a gate-level Verilog netlist, not an HDL boolean
       model like Lynx-LB.

       Dynablock extracts timing models that are acceptable to standard cell
       methodologies, such as Synopsys' Design Compiler.

     Avanti claims that SGS Thompson has used Lynx-LB successfully on designs
     of 900k transistors in about 20 minutes.

     Synopsys/Epic's Coremill is supposed to be similar to Lynx-LB and
     DynaBlock, but we never get a chance to see it."

         - a Silicon Valley chip designer


    "Lay not up for yourselves treasure upon earth, where moth and rust
     doth corrupt, and where thieves break through and steal."

       - Matthew 6:19


 "YES, WE HAVE NO BANANAS"  Take a college course in logic & sematics
 sometime and you'll find yourself in a final exam analyzing Venn diagrams
 about apparently contradictory statements like "Yes, we have no bananas".
 Yes, while in the full scan world, Mentor's Fastscan and Synopsys' Test
 Compiler still remain the biggest technology contenders; the biggest splash
 at DAC came from ATG Technology with its powerful NO SCAN ATPG tool.  And
 again, yes, Sunrise is quite well known in the partial scan world, from some
 customer's reports it appears ATG Tech's NO SCAN ATPG tool seems to be
 getting very good results generating significant coverage for designs that
 have NO SCAN access whatsoever.  Whoa!  The only other no scan solution more
 popular was BIST, which has improved dramatically in the last few years.

    "Logicvision was by far the most impressive.  While having all our
     buffers defined as BiDi's could be somewhat of a task for the tool,
     the ability to add BIST to an analog cell was very impressive.  They
     demonstrated the tool's accuracy by adding BIST to a PLL.  The algorithm
     would measure and characterize the PLL, including the very to difficult
     to measure jitter.  While the simulation demo was enough to convince me,
     Logicvision went even farther by setting up a demo board with an
     off-the-shelf PLL which the tool characterized by downloading the BIST
     logic into an FPGA (sorry guys, it was "X").  While the BIST logic
     tested the PLL, an oscilloscope was setup to probe the various points
     on the PLL to show how closely the waveforms matched the simulated
     results.  The accuracy looked to be within 5%.  The advantage of this
     is that only one tester is needed to test both analog and digital."
	
         - an East Coast engineer (Lucent)

    "I'm curious about Duet's automatic scan chain insertion for IP blocks.
     I'll be over at their booth."

         - an anon engineer while on the DAC floor

    "TSSI presented their test insertion product and test vector preparation
     product in which their demo hung.  The test insertion product was poor
     compared to Sunrise or Synopsys test compiler.  The test vector product
     looked state of the art in terms of automation, capability, flexibility
     etc.  Functional blocks are selected in a GUI, interconnected and the
     process kicked off from the GUI, although the most capable this is the
     demo that hung.  Something bothers me when demos of test products hang."

         - an Arizona chip designer


 DARWIN GOES ESDA AWARD: Goes to Summit Design.  With i-Logix gone, Speed
 dead, KBS gone, Vista gone, Mentor redoing Renior to have the *exact*
 look & feel of Summit's Visual HDL, and Escalade not capturing even a
 fraction of the ESDA market share they originally bragged they'd have,
 Summit design has moved on to expanding into code coverage, HW/SW co-design,
 waveform viewing, text2graphics, and is even flirting with behavioral
 synthesis by sharing its DAC bed with its new live-in girlfriend, Dasys.
 While some of the new ESDA players, like the awkwardly named mouthful "China
 Integrated Circuit Design Center" (offering it's Panda VDE visual design
 capture/debug/sim toolset) aren't being taken seriously because nobody wants
 to risk *their* career on EDA software of questionable support & reliability
 -- one new set of ESDA tools, Novas' DeBussy, surprisingly caught the fancy
 of many user's eyes.  On top of all the usual ESDA FSM stuff, users were
 wowed at how Debussy recognizes synthesis elements early in the design
 process and checks for synthesis syntax errors; how nSchema annotates a
 schematic with SDF info plus clock tree analysis plus having asynchronous
 signal paths recognized; how nTrace displays memory contents plus driver
 and load tracing.

    "Novas' Debussy is a major leap forward in GUI's, compared to Virsim
     (which I sell) and SignalScan, which still looks like the old
     SunWindows.  Debussy takes the best ideas from many tools and adds in
     synthesis to make a real winner.  I don't know how it performs on large
     designs, but the demo looked great.  The source code browser annotates
     the code with signal values, as does the schematic tool.  The schematic
     for their simple circuit was made very readable by doing partial
     synthesis to recognize muxes and ALUs.  Lastly, their state machine
     tool did a nice job of creating a diagram, but the example only had
     5 states.  How good was the tool?  I saw the Virsim project manager
     watching a demo!

       - a Virsim salesman

    "The best niche tool?  Debussy by Novasoft.  It was a really cool
     Verilog debugging tool.  You could even capture the contents of memory
     and view it through time.  All the windows are very well integrated."

       - a design engineer from Texas


    "Escalade: I am going to bring Escalade in to demonstrate their
     DesignBook front end HDL design tool.  This product competes with
     Renoir and VisualHDL.  I am a little concerned because they have
     focused on building tools to protect Intellectual Property this year.
     The new tools are based on DesignBook but they refocused their target
     market this year.  If they spread themselves too thin (like MicroSim
     did last year) they will be gone next year.  In my opinion, DesignBook
     is one of the top three front end tools.

     Summit: When I checked out Summit's VisualHDL, I told them they had
     the best graphical front end design tool for Verilog.  The only problem
     was that I couldn't afford it.  They said to let them work on a way to
     solve that problem.  (Don't hold your breath. <G>)

     Renoir: We had an in house demo of Renoir two weeks before DAC so I
     didn't look at it at DAC. Renoir is my first choice right now.  It is
     less risky than Escalade's DesignBook and more affordable than Summit's
     VisualHDL."

         - a Telecom oriented designer


    "John, I just wanted to express my thanks for the jump-start your ESDA
     design shoot out of two years ago had on Mentor.  Renoir, our high-level
     design capture tool, has now passed the 25% market share point and is
     rapidly displacing Summit.  It wouldn't have happened without the
     wake-up call your contest gave to our "System Architect" product.  It
     is now a multimillion dollar per year high profit generator for Mentor.
     My thanks."

         - Wally Rhines, CEO of Mentor Graphics, in ESNUG 278 #3


 BIG IRON VS. LE TOUR DE FRANCE: Two years ago at DAC'96, at least a dozen
 companies (SpeedSim, Frontline, Fintronic, Synopsys, Vantage, Chronologic,
 Pendulum, Cadence, Cadence Alta, Synopsys, Mentor (rumored), and CAE Plus)
 had or were working on a cycle-based simulator.  It was like the R&D staffs
 from these companies all called the same psychic hotline for advice.  Now,
 two years later, Pendulum disappeared, Fintronic & CAE Plus are still
 around, and the rest of the cycle-based simulators have been gobbled up
 in the EDA food chain to end up either in Cadence, Synopsys, Avanti, or
 Zycad -- with the major players being Synopsys and Cadence in a weird way.

 Cycle-based simulators evaluate boolean equations -- which means they're
 great at simulating gate-level logic as long as you're ONLY interested in
 FUNCTION and NOT TIMING.  Non-cycle-based simulators handle TIMING very
 well, but generally aren't nearly as fast as cycle-based simulators.  As
 a result, there are very few EDA users of pure cycle-based simulators.  (For
 example, Cadence's COBRA only has seven customers).  But, the Chronologic
 whizkids found a way to merge Roadrunner cycle-based technology within their
 compiled Verilog VCS such that VCS runs cycle-based on the non-timing parts
 of simulations and compiled on the remaining parts.  (It's rumored that
 Cadence is trying to do this with NC-Verilog but no one can confirm it.)

 Now let's look at the hardware emulation/acceleration world which is in
 essence a speeding up of the simulation of gates.  Quickturn, Mentor, Aptix,
 IKOS, and Zycad all got into this business *before* cycle-based simulation
 was widely used.  Now that EDA software has found a savvy way to speed up
 gate simulation, those old half-million dollar Big Iron solutions suddenly
 aren't so appealing to EDA users.  (It's not that software simulation
 beats Big Iron in performance -- it's that software now has sped up
 simulation enough to make pricey Big Iron more of a luxary than necessity.)
 The Big Iron guys are fighting for their survival.  That's why Quickturn
 sued Mentor to block them from selling Big Iron in the US.  (And that
 lawsuit is why Mentor has recently put out a takeover bid on Quickturn.)
 Survivial is also why Quickturn bought out ARKOS from Synopsys last year
 (even after aquiring equivalent an ARKOS-like technology, IBM's COBALT)
 -- and it's why Quickturn did a If-You-Can't-Beat-Them-Join-Them purchase
 of little old 33 employee SpeedSim in Jan '97 for the inflated price of $55
 million.  It's also why Quickturn wrapped this all together to squeeze out
 its Mercury Design Verification system which is essentially an event-driven
 Verilog behavioural simulator with 74 FPGAs and 2 PowerPCs tacked on to
 speedily simulate a million gate design (w/ pricing of $395K for 500K gates
 and around $1 million for a 2 million gates.)  Gotta fight to survive!

 Big Iron old timer IKOS and Big Iron DAC newbies Axis and VeriPOD have all,
 more or less, mimicked Quickturn technologically in trying have customers
 simulate RTL on some type of reconfigurable hardware.  So far, financially
 Quickturn and IKOS have announced revenue drops.  Nobody knows how the
 newbies Axis and VeriPOD will fare.


    "Subject: For Sale -- One QUICKTURN hardware emulator

     We have a Quickturn hardware emulator which we no longer wish to
     support in our flow.  Anyone interested in this device should contact
     my boss, David Burleson at: David.Burleson@Sciatl.com"

         - Tom Coonan
           Scientific Atlanta (from ESNUG 295 #9)


    "Axis: combines debuggability and speed.  Look, Act and Feel like a
     software simulator running at hardware speed.

        - Simulates up to 2M gates on 8 boards plugged into PCI bus on Sun.
        - Costs around $250K.  Limitation is cost of high end Altera parts.
        - Speed 10K - 100K cycles/sec
        - No synthesis - directly executes behavioral RTL.
        - Start simulation with $rccon to run fast, then switch to $rccoff
          shortly before failure to do a pure software debug.

     Would be great to have this for $10K so that every designer could have
     one.  Its value at $250K is a lot harder to justify."

         - a Silicon Valley chip designer


    "I think it stinks how easily EDA companies can chop and change their
     product line leaving customers high and dry.  It has happened so
     many times in the last 10 years I am suprised anyone wants to buy
     CAD tools any more!

         - a European EDA user commenting on Synopsys selling ARKOS to
           Quickturn two weeks after DAC'97


    "Mentor is OEMing QuickHDL-XLC from Topdown Design.  Topdown calls it
     Cyclops.  According to TD salesman, it's a Verilog pre-processor
     that levelizes even-driven simulations to make them cycle-based.
     Sells for $23,000 which is cheaper than NC-Verilog or VCS."

         - an anon engineer


 NICE HORSEY!  In the early days of EDA, when the dinosaurs roamed the Earth
 and people knew who Carver Mead was, before synthesis, there used to be
 something sorta like proto-synthesis that was called "datapath compilation".
 In fact, there was even a company called Silicon Compilers that used to sell
 datapath compilers.  And, it being the Age of EDA Dinosaurs and all, Mentor
 Graphics was around and Mentor did what it does best.  It bought Silicon
 Compilers and destroyed it.  Time went by.  Synthesis was discovered.  Silc
 and Synopsys and Synergy and Exemplar and Booledozer and Veribest and
 Synplicity and ACEO and Ambit came along.  Some died, a few thrived, and a
 few are still struggling to survive even today.  And datapath compilation
 suddenly reappeared out of nowhere.  A very small company, Silerity, down
 in Los Angeles, offered a nascent tiling datapath compiler, PathBlazer, in
 '94.  Viewlogic then bought Silerity in '95, and after a failed attempt at
 trying to market PathBlazer, View followed that time honored Mentor
 tradition and killed it.  Time passed.  Synthesis giant, Synopsys, bought
 SiArc and found it had accidentally acquired a SiArc in-house datapath
 compiler in the purchase.  Secret microphones planted within Synopsys R&D
 at the time picked up the following: "Ewww...  A datapath compiler...  How
 disgusting!  Let's erase the hard drive and pretend we never found it...",
 then there's a garbled disagreement, followed by the sounds of a physical
 struggle.  Months later, Synopsys markets an equation-based/non-tiling-based
 SiArc datapath compiler under the name "Module Compiler".  And around the
 same time, two other unrelated companies, Tera Systems and Arcadia, also
 introduce their own tiling-based datapath compilers, and a long lost EDA
 niche is reborn.  And, although Module Compiler appears to be making a lot
 of money for Synopsys, it appears that a lot of users at this DAC were
 quite mesmerized by Arcadia's Mustang.  Nice horsey!

    "Additionally, our pulse of field contacts on which new products are
     hot revealed some surprises: ... [ stuff deleted ] ...  Module Compiler
     (datapath synthesis tool) is enabling SNPS sales reps to exceed quota.
     We were skeptical about SNPS' marketing claims when the product was
     announced 1-2 quarters ago, that Module Compiler could sell 1-for-1
     with Design Compiler (control logic synthesis).  Most SNPS' field reps
     agree that the 1:1 ratio is too generous, but the product is ramping
     exceedingly well and customers like it (we independently discussed
     with users)."

         - from a financial analyst's report of DAC'98

    "The most interesting tool was Arcadia Mustang because the approach is
     so novel.  It takes your regularly synthesized netlist and deduces the
     regularity from it to do datapath placement.  I'm surprised it could
     work, but apparently they have success with it.  IBM included the tool
     in their ASIC flow.  There was also an interesting paper in the DAC
     Proceedings evaluating the results of commercial datapath compilers.
     They don't name names, but you can have fun trying to figure out which
     vendor they're talking about :-)"

         - a California engineer


 A BATTLE OF PROXIES:  Whereas Synopsys likes to see itself as a "serious"
 player in the FPGA/CPLD synthesis game, the truth is that the real players
 in that market are Exemplar, Synplicity, the freeware FPGA synthesis tools
 that the FPGA vendors give out themselves (like Altera's MaxPlus II), and
 the it-might-as-well-be-freeware software that Minc/Synario/IST "gives" out.
 Last year's DAC was Synplicity's "coming out party" -- literally they had
 grown to the point where they were sponsoring parties big enough at DAC
 that other EDA rivals were attending uninvited -- Synplicity had finally
 arrived in EDA.  This year's DAC was no different: Bob Russo, the Synopsys
 Senior VP of Worldwide Sales & Services, was unexpectedly seen at the
 Synplicity after hours Top Of The Marriott party!  On the technical side,
 Synplicity announced an FPGA floorplanning tool that caught the interest of
 many engineers -- but no one reported on it in technical detail.  Another
 company that has a well-known FPGA floorplanner is Morphologic with its
 "MorphMCFP".  Targeting the big FPGA's (like the Lucent 2C, 2T, 3C, & 3T
 series plus the Xilinix XC4000E/EX/L/XL series), MorphMCFP lets engineers
 automatically translate/partition designs between FPGAs with complete
 compliance to each device's design rules.  It does automatic I/O allocation
 and de-allocation (as needed) and the floorplanner instantly retimes the
 newly placed design as feedback to the engineer.  Is Synplicity's new FPGA
 floorplanner this sophisticated?  We don't known.  On the business side,
 Synplicity also demostrated a wee bit of business acumen in cutting a deal
 to OEM ModelTech's combined Verilog-VHDL simulator.  (Model Tech & Exemplar
 are both divisions of Mentor!  Talk about each division being its *own*
 profit & loss center within Mentor!  Whoa!)


    "I spent some time in Synplicity's booth looking at their new release.
     They have added a bunch of new debug features but nothing drastic.
     Symplicity and Exemplar keep pushing each other.  Their fight for
     marketshare based on features and price is great for users.

     Exemplar still has the best value in Synthesis.  The new Spectrum
     release looks great.  I will have to play with it before I pass
     judgement on whether it works as well as it looks.  It has orders of
     magnitude more control of the synthesis process than Synplicity at a
     fraction of the cost of Synopsys.  The new constraint editor is the
     first usable one I have seen on any synthesis tool.  I heard from an
     Exemplar wheel that Exemplar's growth last year was equal to
     Synplicity's total revenue.  Both Exemplar and Synplicity have realized
     that the quality of their synthesis is often compromised by FPGA place
     and route tools.  They are integrating the vendor specific P&R tools
     into their GUIs and linking the synthesis and floor planning tools.

         - a West Coast designer

    "Marketing and marketing clout will beat technology every time."

         - Mark Stevens of Sequoia Capital, a venture capital firm


 "THE MAN WITHOUT A COUNTRY"  In American folklore there's a famous story
 about some poor sap who committed a horrible crime and flippantly told the
 judge that he wished he didn't have a country.  The guy was sentanced to
 spending the rest of his life aboard sailing ships never setting foot in
 *any* country.  ACEO is like this, but it's "A Company Without A Customer". 
 For over seven years I've run a quasi-guerilla style mailing list (ESNUG)
 that has over 6,000 EDA users (worldwide) reading and responding to it
 weekly.  In its entire seven year history I have, as of yet, to find anyone
 "on" or "off the record" ever talk about or even hint at having thought of
 trying ACEO's "Gatran" synthesis tool.  Not one.  Never.  Nada.  "Yes, we
 don't know what you're talking about."  And yet ACEO claims to have had
 *hundreds* of customers over these past four years!  And now ACEO annouced
 "Asyn" -- a "one pass hierarchical synthesis tool" -- and "Softwire" -- a
 multi-FPGA partitioning tool -- at this year's DAC.  Hello, McFly!  Is
 anyone home?  Hello!


    "Again, this is a loaded question.  Richard, I don't have an answer
     for all of that.  Two year have passed.  The last time I was on the
     CEO panel was two years ago.  During these two years a lot things
     have happened.  OK, many people think, uh, said things about me,
     about us.  But one thing you not says is that I have not brought
     entertainment value to you, this industry."

         - Gerry Hsu, CEO of Avanti, while on the DAC'97 CEO Panel,
           responding to the question of why EDA start-ups seem so
           successful in developing new technologies so quickly.

 
    "You've had a lot of fun -- a *lot* of fun -- that you've had an
     opportunity to attack me.  Just think how much you're going to be
     missing.  You won't have Nixon to kick around any more, because,
     gentlemen, this is my last press conference."

         - Richard Nixon after he lost the 1962 election to be
           the governor of California


 Next Week: [ part 2 of 2: the back-end & the other new EDA tools/ideas ]

===========================================================================
 Trying to figure out a Synopsys bug?  Want to hear how 6,000+ other users
   dealt with it?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

Article: 11509
Subject: 4PPM Algoritm
From: watm <watm@asterix.ist.utl.pt>
Date: Thu, 20 Aug 1998 15:32:28 +0100
Links: << >>  << T >>  << A >>


    I need to find the algoritm or the block diagram of the 4PPM (Pulse
Position Modulation). If someone has the algoritm inplemented in VHDL or
ABEL, its perfect.

   If someone give a hand, i will appreciated.


Thanks in advance,
Rui Pinto

Article: 11510
Subject: vector product minimization problem
From: benyamin@my-dejanews.com
Date: Thu, 20 Aug 1998 14:56:26 GMT
Links: << >>  << T >>  << A >>
I would like to see if there are existing algorithms to solve the following
minimization problem.

Consider the expression:

x1 + 2 * x2 + 3 * x3 + 4 * x4 + 5 * x5 +
6 * x6 + 7 * x7 + 8 * x8

If only multiplications by powers of two are allowed, how can this expression
be re-written (using associativity, distributivity, etc.) such that the number
of additions is minimized?  You can use a subexpression, like a=x1+x2, in the
final expression.  I have several slightly different answers that use 11
additions, but none fewer.  For example, one such set of expressions that uses
11 is:

z=x6 + x7
y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)

Can you get less than 11?
More importantly, is there an algorithm that solves minimization problems of
this nature?

The purpose of it is for circuit synthesis, and I have come up with a simple
algorithm which yeilds results that are linear in size.  The closest method to
it is Distributed Arithmetic, but the ROM size in DA grows exponentially.
Anything like this out there?


Thanks,
Dan Benyamin
benyamin@ulca.edu

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11511
Subject: Re: Data I/O Chiplab and NT
From: Barry Brown <barry@sr.hp.nospam.com>
Date: Thu, 20 Aug 1998 10:15:31 -0700
Links: << >>  << T >>  << A >>
Tim Forcer wrote:
> 
> We have two Data I/O Chiplab 48 "project" programmers, which are nice
> units.  But they are unusable under Windows NT due to the dreaded port
> access problem.  Data I/O's UK agents state that no software upgrade
> will allow function under NT, and we've tried various tricks involving
> public-domain drivers such as giveio.sys without success.
> 
> Anybody got any bright ideas?  If not, we'll have to maintain a couple
> of Win95 machines just for these units.
> 
>

Or you could purchase Partition Magic or System Commander and set up
your machines with "dual-boot" options for Win NT and 95.
-- 
Barry A. Brown
Microwave Instruments Division
Hewlett-Packard Company
****  Remove the "nospam" from my email address  *****
Article: 11512
Subject: Re: vector product minimization problem
From: qed@pobox.com (Paul Hsieh)
Date: Thu, 20 Aug 1998 10:54:54 -0700
Links: << >>  << T >>  << A >>
benyamin@my-dejanews.com says...
> I would like to see if there are existing algorithms to solve the following
> minimization problem.
> 
> Consider the expression:
> 
> x1 + 2 * x2 + 3 * x3 + 4 * x4 + 5 * x5 + 6 * x6 + 7 * x7 + 8 * x8
> 
> If only multiplications by powers of two are allowed, how can this expression
> be re-written (using associativity, distributivity, etc.) such that the number
> of additions is minimized?  You can use a subexpression, like a=x1+x2, in the
> final expression.  I have several slightly different answers that use 11
> additions, but none fewer.  For example, one such set of expressions that uses
> 11 is:
> 
> z=x6 + x7
> y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)
> 
> Can you get less than 11?
> More importantly, is there an algorithm that solves minimization problems of
> this nature?

Yes, there is an algorithm (as to whether or not you can beat 11, I have 
no idea).  It takes some imagination to write it, but its not impossible.  
I have solved a couple very similar problems to this using purely 
algorithmic methods.  

The idea is to simply enumerate all operations possible, on some initial 
state of registers in an orderly fashion.  After each operation, a new 
state is achieved as some incremental cost.  Suppose these represents 
vertex's of a graph.  Then it is a matter of reaching a certain node (or 
any node with a certain property) of your graph with the minimum cost.  
This reduces it to a graph theory/network flow problem.  See:

    http://www.pobox.com/~qed/amult2.html

for one example.

Depending on how many auxilliary register you assume, your problem space 
is fairly large, so I'm not sure you could directly search through the 
space to find the answer, unless you have a super computer with a ton of 
memory at your disposal.

It may be that there is a pattern for (x1 + 2*x2 + ... + n*xn) so you 
could solve the problem for small n first to try to extrapolate the 
solution for n=8.

--
Paul Hsieh
qed@pobox.com
http://www.pobox.com/~qed/
Article: 11513
Subject: Re: vector product minimization problem
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 20 Aug 1998 14:14:01 -0400
Links: << >>  << T >>  << A >>
Distributed arithmetic immediately came to mind, and as I read down, I see you
also considered it.  You can use a combination of distributed arithmetic, bit
serial and scaling accumulators to minimize the look up table size.  Your example
below could be done with a 256 x 6 look-up table followed by a scaling accumulator
(the feedback on the accumulator shifts one bit with respect to the input).  The
eight variables are serialized so that table address is one bit from each.  So for
each execution, you do n table lookups (n is the number of bits in your
variables).  The results from each lookup are added to the shifted sum of the
previous partial results.  After n cycles you have the complete result in the
accumulator.

If you require more speed (less clock cycles), you can duplicate the table as
needed to do 2 or more bits at a time.  Now, the table itself can be broken down
too.  Since each table entry is  1*a + 2*b + 3*c + ... + 8*g, you can break this
into two smaller tables: 1*a + 3*c + 5*e + 7*h  and  2*b + 4*d + 6*f + 8*g and
then use an adder to combine the look up results.  This results in two 16 x 5
tables and a 6 bit adder instead of one 256 * 6 table.  This decomposition can be
extended as needed to reduce the size of the tables to a convenient size.

I hope this helps!


benyamin@my-dejanews.com wrote:

> I would like to see if there are existing algorithms to solve the following
> minimization problem.
>
> Consider the expression:
>
> x1 + 2 * x2 + 3 * x3 + 4 * x4 + 5 * x5 +
> 6 * x6 + 7 * x7 + 8 * x8
>
> If only multiplications by powers of two are allowed, how can this expression
> be re-written (using associativity, distributivity, etc.) such that the number
> of additions is minimized?  You can use a subexpression, like a=x1+x2, in the
> final expression.  I have several slightly different answers that use 11
> additions, but none fewer.  For example, one such set of expressions that uses
> 11 is:
>
> z=x6 + x7
> y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)
>
> Can you get less than 11?
> More importantly, is there an algorithm that solves minimization problems of
> this nature?
>
> The purpose of it is for circuit synthesis, and I have come up with a simple
> algorithm which yeilds results that are linear in size.  The closest method to
> it is Distributed Arithmetic, but the ROM size in DA grows exponentially.
> Anything like this out there?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka

Andraka Consulting is a digital hardware design firm specializing in high
performance FPGA designs for signal processing, computing and control
applications.  See us at WESCON'98 and the Military Applications for PLDs
Conferences.


Article: 11514
Subject: Re: vector product minimization problem
From: Pat Kling <klingp@ct.picker.com>
Date: 20 Aug 1998 16:43:13 -0400
Links: << >>  << T >>  << A >>

This solution can be implemented in a slightly different order
to minimize the total delay to 4 adders.  All solutions will 
require at least 4 adder delays. (assuming only full adders
are allowed)

C+2F     E+G    A+2B    4D+8H
 |        |      |        |
3C+6F   5E+5G   A+2B+2G   |
  |       |      |        |
 3C+5E+6F+5G    A+2B+4D+2G+8H
      |               |
    A+2B+3C+4D+5E+6F+7G+8H


Pat Kling <klingp@ct.picker.com> writes:
>
> Form A + 2B + 3C + 4D + 5E + 6F + 7G + 8H with 10 additions
> 
> I = C + 2F
> J = I + 2I = 3C + 6F
> K = E + G
> L = K + 4K = 5E + 5G
> M = L + 2G = 5E + 7G
> N = M + J  = 3C + 5E + 6F + 7G
> O = N + A  = A + 3C + 5E + 6F + 7G
> P = O + 2B = A + 2B + 3C + 5E + 6F + 7G
> Q = P + 4D = A + 2B + 3C + 4D + 5E + 6F + 7G
> R = Q + 8H = A + 2B + 3C + 4D + 5E + 6F + 7G + 8H
> 
> I've got no idea if it can be done in less.  Certainly it would require
> a minimum of 8.
> 
> Patrick Kling (klingp@ct.picker.com)
Article: 11515
Subject: Re: vector product minimization problem
From: "John L. Smith" <jsmith@visicom.com>
Date: Thu, 20 Aug 1998 18:31:35 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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benyamin@my-dejanews.com wrote:

> I would like to see if there are existing algorithms to solve the following
> minimization problem.
>
> Consider the expression:
>
> x1 + 2 * x2 + 3 * x3 + 4 * x4 + 5 * x5 +
> 6 * x6 + 7 * x7 + 8 * x8
>
> If only multiplications by powers of two are allowed, how can this expression
> be re-written (using associativity, distributivity, etc.) such that the number
> of additions is minimized?  You can use a subexpression, like a=x1+x2, in the
> final expression.  I have several slightly different answers that use 11
> additions, but none fewer.  For example, one such set of expressions that uses
> 11 is:
>
> z=x6 + x7
> y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)
>
> Can you get less than 11?

I don't think so Dan, add up the number of 1-bits (or 0-bits +1 if this isless) in
the co-efficients, then subtract 1 (because you always start with
one):

coef:               1 2 3 4 5 6 7 8
#of adds(or subs):  1 1 2 1 2 2 2 1  -> Total-1 = 11

> More importantly, is there an algorithm that solves minimization problems of
> this nature?

I'm sure there are, but don't have any ref's, hopefully someone else will.

> The purpose of it is for circuit synthesis, and I have come up with a simple
> algorithm which yeilds results that are linear in size.  The closest method to
> it is Distributed Arithmetic, but the ROM size in DA grows exponentially.
> Anything like this out there?

DA is nice, it is a regular design technique, easily implementedby program, and
sometimes you want that regularity.
But, I've been seeing through experience that
most (all I've tried so far) fixed arithmetic circuits can be
worried into a more compact format, if you have the time
to pull the numbers apart and find patterns. A hand-crafted
color-space converter I did saved ~30-35 CLBs (30%)
over the DA equivalent circuit. I don't know if this is
always the case.

I'd be very interested if you get any ref's.


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<HTML>
&nbsp;

<P>benyamin@my-dejanews.com wrote:
<BLOCKQUOTE TYPE=CITE>I would like to see if there are existing algorithms
to solve the following
<BR>minimization problem.

<P>Consider the expression:

<P>x1 + 2 * x2 + 3 * x3 + 4 * x4 + 5 * x5 +
<BR>6 * x6 + 7 * x7 + 8 * x8

<P>If only multiplications by powers of two are allowed, how can this expression
<BR>be re-written (using associativity, distributivity, etc.) such that
the number
<BR>of additions is minimized?&nbsp; You can use a subexpression, like
a=x1+x2, in the
<BR>final expression.&nbsp; I have several slightly different answers that
use 11
<BR>additions, but none fewer.&nbsp; For example, one such set of expressions
that uses
<BR>11 is:

<P>z=x6 + x7
<BR>y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)

<P>Can you get less than 11?</BLOCKQUOTE>
I don't think so Dan, add up the number of 1-bits (or 0-bits +1 if this
isless) in the co-efficients, then subtract 1 (because you always start
with
<BR>one):<TT></TT>

<P><TT>coef:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
1 2 3 4 5 6 7 8</TT>
<BR><TT>#of adds(or subs):&nbsp; 1 1 2 1 2 2 2 1&nbsp; -> Total-1 = 11</TT>
<BLOCKQUOTE TYPE=CITE>

<P>More importantly, is there an algorithm that solves minimization problems
of
<BR>this nature?</BLOCKQUOTE>
I'm sure there are, but don't have any ref's, hopefully someone else will.
<BLOCKQUOTE TYPE=CITE>The purpose of it is for circuit synthesis, and I
have come up with a simple
<BR>algorithm which yeilds results that are linear in size.&nbsp; The closest
method to
<BR>it is Distributed Arithmetic, but the ROM size in DA grows exponentially.
<BR>Anything like this out there?</BLOCKQUOTE>
DA is nice, it is a regular design technique, easily implementedby program,
and sometimes you want that regularity.
<BR>But, I've been seeing through experience that
<BR>most (all I've tried so far) fixed arithmetic circuits can be
<BR>worried into a more compact format, if you have the time
<BR>to pull the numbers apart and find patterns. A hand-crafted
<BR>color-space converter I did saved ~30-35 CLBs (30%)
<BR>over the DA equivalent circuit. I don't know if this is
<BR>always the case.

<P>I'd be very interested if you get any ref's.
<BR>&nbsp;</HTML>

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Article: 11516
Subject: Re: vector product minimization problem
From: tim@jumpnet.com (Tim Olson)
Date: Thu, 20 Aug 1998 17:41:51 -0500
Links: << >>  << T >>  << A >>
In article <6rhdeq$dh4$1@nnrp1.dejanews.com>, benyamin@my-dejanews.com wrote:

| Consider the expression:
| 
| x1 + 2 * x2 + 3 * x3 + 4 * x4 + 5 * x5 +
| 6 * x6 + 7 * x7 + 8 * x8
| 
| If only multiplications by powers of two are allowed, how can this expression
| be re-written (using associativity, distributivity, etc.) such that the number
| of additions is minimized?  You can use a subexpression, like a=x1+x2, in the
| final expression.  I have several slightly different answers that use 11
| additions, but none fewer.  For example, one such set of expressions that uses
| 11 is:
| 
| z=x6 + x7
| y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8)
| 
| Can you get less than 11?

Are subtractions also allowed (invert "b" operand and set carry in)?

y = x1 - x3 + x5 - x7 + 2*(x2 + x6) + 4*(x3 + x4 + x5 + x6) + 8*x8

-- 

     -- Tim Olson
Article: 11517
Subject: Video 256 colors interface HELP!
From: "Dj" <dejan@versilia.toscana.it>
Date: Fri, 21 Aug 1998 00:44:55 +0200
Links: << >>  << T >>  << A >>
Hello to everybody : - )

I am New on fpga programming and I try to implement
simple video interface whitch I already do it with real componets, is there
somebody can help me with some
very simple examples.

THANKS :  )



Article: 11518
Subject: Video 256 colors interface HELP!
From: "Dj" <dejan@versilia.toscana.it>
Date: Fri, 21 Aug 1998 00:44:55 +0200
Links: << >>  << T >>  << A >>
Hello to everybody : - )

I am New on fpga programming and I try to implement
simple video interface whitch I already do it with real componets, is there
somebody can help me with some
very simple examples.

THANKS :  )



Article: 11519
Subject: Video 256 colors interface HELP!
From: "Dj" <dejan@versilia.toscana.it>
Date: Fri, 21 Aug 1998 00:44:55 +0200
Links: << >>  << T >>  << A >>
Hello to everybody : - )

I am New on fpga programming and I try to implement
simple video interface whitch I already do it with real componets, is there
somebody can help me with some
very simple examples.

THANKS :  )



Article: 11520
Subject: half full flag in a xilinx async fifo?
From: "Dan Kuechle" <dan_kuechle@i-tech.com>
Date: Thu, 20 Aug 1998 22:57:08 GMT
Links: << >>  << T >>  << A >>
Anybody out there got a good solution for a half full flag for a fifo?  I
was planning on using Xilinx sync dual port ram to get a 16 deep fifo.  The
write clk and read clk are app the same frequency (~53 mhz) but are from 2
different xtal sources so are async to each other. 

My fifo basics are rusty...I've always used a full u/d counter to do this
in the past, but can't with this design due to the different clocks.  I
know that when the read pointer = the write pointer the fifo is either full
or empty, but don't know what relationship indicates half full.  Could
someone help me out?  The flag does not need to be exact, and I can re-sync
to eliminate any glitches.  Even a false half full indication would not
cause a problem as long as it happens right around the half full point.

Thanks
   Dan
Article: 11521
Subject: Silicore announces 8-Bit RISC uP / VHDL IP Core for FPGA
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Thu, 20 Aug 1998 23:21:23 GMT
Links: << >>  << T >>  << A >>
Press Release / For Immediate Release

Silicore Corporation Releases 8-Bit RISC Microprocessor - VHDL IP Core
----------------------------------------------------------------------

August 17, 1998 - Minneapolis, MN  USA.  Silicore Corporation
announced today the release of its latest VHDL microprocessor IP core.
Called the Silicore(TM) SLC1655, the core provides a complete 8-bit
RISC processor solution for use on FPGA or ASIC devices.  Typical
applications include sensors, medical devices and consumer
electronics.

The core is unique because it allows the user to create a complete,
single chip microcontroller right at their own desk.  The Silicore(TM)
SLC1655 requires only 10% - 25% of an FPGA part (including RAM and
instruction ROM), leaving plenty of room for added peripherals.
Furthermore, the core can be fabricated using a wide variety of
package types, speeds and temperature ranges.  For high volume
production, the core can be moved into an ASIC device.

Wade Peterson, President and CEO of Silicore, stated that: "This
product opens up exciting new possibilities for electronic designers.
It creates a whole new genre of solutions available to the end user.
They can completely control the design, and add whatever peripherals
and I/O's they want.  With this product they no longer have to pay
expensive NRE charges, or wait weeks or months for prototype
microcontrollers."

The Silicore(TM) SLC1655 core includes an 8-bit RISC processor, RAM,
ROM, counter/timer and powerdown logic.  A complete evaluation kit,
using a Lucent Technologies ORCA(R) FPGA, is available.  Typical
operating speeds are 5-10 MIPS.  It is delivered as a VHDL
'soft-core', and is portable across many brands of FPGA parts such as
those available from Lucent, Xilinx and Altera.

The Silicore(TM) SLC1655 is software compatible with the PIC(R) series
of microcontrollers from Microchip Technology, Inc.  [Over 600 million
PIC(R) processors have been sold since 1990].  Many third party
software tools such as assemblers, simulators and 'C' compilers are
available for the Silicore(TM) SLC1655.  Furthermore, the core runs at
twice the speed of the Microchip parts.

For more information see the Silicore web site at
http://www.silicore.net, or contact: Jeff Pearson at 800-583-7484.

Silicore is a service mark and trademark of Silicore Corporation.
ORCA(R) is a registered trademark of Lucent Technologies Inc.  PIC(R)
is a registered trademark of Microchip Technology, Inc.  Silicore
Corporation is not affiliated with Microchip Technology, Inc.


Article: 11522
Subject: Re: Video 256 colors interface HELP!
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 20 Aug 1998 21:08:01 -0400
Links: << >>  << T >>  << A >>
Dj wrote:

> I am New on fpga programming and I try to implement
> simple video interface whitch I already do it with real componets, is there
> somebody can help me with some
> very simple examples.

 Soo, FPGA's aren't real components??  Shhh, don't tell my clients!
As far as your problem, can you be more specific.  I doubt anyone is going to
post a complete video controller design as an example.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11523
Subject: Re: Video 256 colors interface HELP!
From: YongKook Kim <likepunk@secsm.org>
Date: Fri, 21 Aug 1998 10:21:01 +0900
Links: << >>  << T >>  << A >>




Dj wrote:

> Hello to everybody : - )
>
> I am New on fpga programming and I try to implement
> simple video interface whitch I already do it with real componets, is there
> somebody can help me with some
> very simple examples.
>
> THANKS :  )
>

Hi,.

Try this ... http://www.acte.no/freecore/vga_sync.htm

I hope it can be helpful...

If you have a more specific ideas on implementing VGA,  let  us  know.

Good luck to you!



--
˙Ĝ˙à


Article: 11524
Subject: Re: half full flag in a xilinx async fifo?
From: Jim Peterson <jspeter@birch.ee.vt.edu>
Date: Thu, 20 Aug 1998 21:41:49 -0400
Links: << >>  << T >>  << A >>
Dan Kuechle wrote:
> 
> Anybody out there got a good solution for a half full flag for a fifo? 

[snip]

> ... I
> know that when the read pointer = the write pointer the fifo is either full
> or empty, but don't know what relationship indicates half full.

I believe this occurs when write_ptr - read_ptr = fifo_size / 2.
The subtraction has to be performed modulo fifo_size.

--Jim


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