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Messages from 91400

Article: 91400
Subject: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
From: Kolja Sulimma <news@sulimma.de>
Date: Sat, 05 Nov 2005 12:51:11 +0100
Links: << >>  << T >>  << A >>
air_bits@yahoo.com schrieb:
> Kolja Sulimma wrote:
> 
>>Yes, but Java and C# have essentially the same syntax without any of the
>>defunct side effect issues that make C so damn hard to synthesize but do
>>not have any real use anyway.
> 
> 
> The issue is having to subset a language and it's expected runtime
> environment.
> Both Java and C# barrow heavilty from the same subset of C syntax, and
> both
> have similar problems of porting arbitrary code from a traditional
> sequential
> execution environment to FPGA's. The lack of "real addressable memory"
> results in difficulties in dynamic allocation, and runtime
> architectures that
> expect pointers to create and manage data objects.

You are perfectly right. As I wrote in my post I think that you need
some features like explicit parallelism that none of the mainstream
languages offer, albeit there are languages available that would be
suitable.

But apparently all those highly trained clever software engineers can
not be bothered to learn another language. At least this argument
allways comes up at that point. (Maybe I can find an engineer in india
that is still capable of learning?)
So if your really need C-syntax as many believe - I don't - at least use
a modern C derived language that is easier to compile.
With java essentially only the "new" operated is a problem. With C, well
look at the System-C restrictions.

On the other hand: What's so hard about dynamic allocation? Tell the
designer that it will be slow, and if he uses it simply synthesize to a
microblaze implementation. You will not meet the timing constraint, but
it can be synthesized.
Or even use profiling to find a typicall number of allocated objects and
create them in hardware. If more are used halt execution. That is
exeactly what a sequential processor would. You can't call malloc a
billion times in C and maybe you can not call it 16 times in hardware C.
It is the same type of constraint that is not imposed by the language
but by the implementation fabric and the designer needs to know the
capabilities of his system before implementing.


Kolja Sulimma

Article: 91401
Subject: Why Spartan-3e is the best
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 5 Nov 2005 13:05:48 +0100
Links: << >>  << T >>  << A >>
Why Spartan-3e is the best
==================
  Antti Lukats
  4.Nov 2005

(I was asked about why I think so in private, but I think
my response could have more general interest so I am posting
the reply to c.a.f.)

-------------------------------------------------------------

At first look there differences between S3 and S3e may not
be so significant however there are several small things
that make Spartan-3e my fist choice (from current low-cost
RAM based FPGA offerings).

1) as Spartan-3 was the first Xilinx silicon on new technology
its kind of logical that Xilinx has fixed in Spartan-3e some
issues related to the use of the new technology. So even if those
are minor, there are still chances that S3e is somewhat better
simply because Xilinx has had more experience with the technology
being used.

2) pricing is promised a little lower, this is not so big deal,
but still, its pretty much logical to prefer silicon with best
price/performance ratio.

3) S3e configuration options are WAY superior over all other RAM
based FPGAs currently in production. S3e is the only FPGA that:

* can load not only from SPI Flash but also from Atmel Dataflash
meaning that a it is the only FPGA around that can directly use
an MMC (Atmel MMC form factor packaged 2/4/8 MByte Dataflash cards)
like Flash card as its main configuration media. So a design with
S3e and MMC Card socket can boot from the removabale flash media
card. Note that the MMC Card socket inserion switch could overide
the 'enable' of the additional on board memory so the SoC loaded
from the inserted into socket Dataflash card could copy a new
bitstream and OS image onto onboard flash, so next 'boot' without
card inserted could come from on board DataFlash. Nice little
feature.

* can load from Parallel Flash, just like the oldies (eg Xilinx first 
FPGA's).
This is VERY good feature as it allows cheap Flash ROMs to be used for both
config and OS image.

* has 'multi boot' option. In Parallel Flash loading mode S3e can
request its own reconfiguration from alternative image.

---

compared to S3, S3e configuration interface allows the use
of SPI or Platform Flash for firmware storage without the
use of extra FPGA IO pin workaround.

S3e configuration is still way less flexible than I could
have designed, but its still the industries best at the moment.


4) S3e has LVDS input onchip termination. I have to admit that
I first found the low cost LVDS onchip termination feature in
Altera Cyclone-II but then I did re-found it in Spartan-3e as
well. It may not so sound like a nig deal, but its a nice
little additional feature that may save some PCB space.

5) Some nice new (compared to other Spartan FPGAs)
package combinations like:
*Largest fabric in VQ100
*Largest fabric in chip-scale package
*Largest fabric in FT256
*Largest fabric in non-BGA package

5) S3e starterkit from Avnet is selling at almost all
time low price of 69USD. (Futre did sell Cyclone kits
for $49 for a while but that kit did not look anything
I would spend money for). To get an eval board with
HS USB chip + FPGA for total cost of $69? Real candy.

6) There are possible some other nice new features
I have not discovered yet :)


Antti Lukats 



Article: 91402
Subject: Re: FPGA : PCI-CORE
From: Ram <r_fpga_dev@yahoo.com>
Date: Sat, 05 Nov 2005 12:14:53 GMT
Links: << >>  << T >>  << A >>
Hi Antti,

Antti Lukats wrote:
> 
> YES. it also includes a LPT connected logic analyzer (uses BRAM's).
> so original software written for LPT connected logic analyzer does run on
> the PCI board.
> 
> the PCI LPT is 'Lava PCI LPT' it is recognized by Windows XP nativly no
> extra driver
> just regular LPT (with 16 base address !!!) any software that can talk to
> LPT can talk
> to the PCI core, and whatever is connected to the virtual LPT wires.
> 
> I am using the same PCI-LPT with xilinx cable III emulation in MAX2
> starterkit
> as PCI Xlinx Cable III :)

How did you create a PCI core compatible with the Lava drivers?  Did you
develop or reverse engineer the Lava PCI bridge?  Or did you use the Lava
Xilinx FPGA in a design?

I'd really be interested to hear how you got this working.

Thanks,
Ram.

Article: 91403
Subject: Re: FPGA : PCI-CORE
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 5 Nov 2005 13:34:32 +0100
Links: << >>  << T >>  << A >>
"Ram" <r_fpga_dev@yahoo.com> schrieb im Newsbeitrag 
news:1n1bf.4575$QM5.3200@tornado.socal.rr.com...
> Hi Antti,
>
> Antti Lukats wrote:
>>
>> YES. it also includes a LPT connected logic analyzer (uses BRAM's).
>> so original software written for LPT connected logic analyzer does run on
>> the PCI board.
>>
>> the PCI LPT is 'Lava PCI LPT' it is recognized by Windows XP nativly no
>> extra driver
>> just regular LPT (with 16 base address !!!) any software that can talk to
>> LPT can talk
>> to the PCI core, and whatever is connected to the virtual LPT wires.
>>
>> I am using the same PCI-LPT with xilinx cable III emulation in MAX2
>> starterkit
>> as PCI Xlinx Cable III :)
>
> How did you create a PCI core compatible with the Lava drivers?  Did you
> develop or reverse engineer the Lava PCI bridge?  Or did you use the Lava
> Xilinx FPGA in a design?
>
> I'd really be interested to hear how you got this working.
>
> Thanks,
> Ram.

Hi Ram,

http://ebook.openchip.org/
its all explained there :)

but really there was no need to RE anything.
I do not do RE unless there is a real need in that.
The change of an exisiting PCI IP core to look
like Lava LPT card was maybe 10 changed
HDL code lines in total. Why do extra work?
I am rather prefer to be lazy in creative way :)

You can either choose to change those 10 lines
of source code, or buy the E-book for 10 USD.

Ah - as special agreement with Enterpoint Ltd.
http://www.enterpoint.co.uk/
this E-Book and 'book resources' are free for
ALL owners of the RaggedStone-1 Spartan-3
PCI FPGA Board. And yes ready to use
.BIT and .MCS files for this board are
also supplied with the E.book.

or if you want to say the penny and do it all
by yourself then just look at PCI specs for the LPT class
codes, and choose some VID/PID that works. Thats it.

BTW I have never owned or hold in my hands any Lava
PCI cards. I just adjusted the PCI config space so that
the PCI card gets configured by WindowsXP 'silently'
without the need of additional drivers.

Antti




Article: 91404
Subject: Re: Why Spartan-3e is the best
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Sat, 05 Nov 2005 13:49:19 +0100
Links: << >>  << T >>  << A >>
Antti Lukats schrieb:

> Why Spartan-3e is the best
 > ==================
 >   Antti Lukats
 >   4.Nov 2005

[snipped Lord's prayer]

Amen, Reverend Atti.
Is it possible that you are obsessed by S3E??
C'mon, life goes on with and without S3E!!
There other things that are important. Even in an engineers life, right?

Just my two(euro)cents
Falk

Article: 91405
Subject: Re: Why Spartan-3e is the best
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 5 Nov 2005 14:04:07 +0100
Links: << >>  << T >>  << A >>
"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag 
news:3t3o7bFr3hddU1@individual.net...
> Antti Lukats schrieb:
>
>> Why Spartan-3e is the best
> > ==================
> >   Antti Lukats
> >   4.Nov 2005
>
> [snipped Lord's prayer]
>
> Amen, Reverend Atti.
> Is it possible that you are obsessed by S3E??
> C'mon, life goes on with and without S3E!!
> There other things that are important. Even in an engineers life, right?
>
> Just my two(euro)cents
> Falk

Hi Falk,

sure! Like going to movies with the family.
"Little Ice-bear II"  is on our family menu this afternoon,
when Anna (2 years) wakes up from beaty sleep we go.

Antti 



Article: 91406
Subject: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
From: air_bits@yahoo.com
Date: 5 Nov 2005 05:25:14 -0800
Links: << >>  << T >>  << A >>

Kolja Sulimma wrote:
> You are perfectly right. As I wrote in my post I think that you need
> some features like explicit parallelism that none of the mainstream
> languages offer, albeit there are languages available that would be
> suitable.

The reality is that forms of parallelism emerge when using C as
an HLL for FPGAs. The first is that the compiler is free to parallel
statements as much as can be done. This alone is typically enough
to bring the performance of a 300MHz fpga clock cycle near the
performance of a several GHz RISC/CISC CPU for code bodies that
have a significant inner loop. Second, explicit parallelism is
available
by replicating these inner loops by creating threads with the same
code body and using established MPI code structures and libraries.
Third the compiler is free to unroll inner loops. Fourth the compiler
is free to flatten the netlists to gain additional parallelism. All
this
and more is obtained without abandoning stable mature development
tools, without learning a new development environment that might add a
few percent higher performance, and without significant unwarranted
risks for many projects.

After several decades of managing large development projects across
multiple facility and platform evolutions we have learned to mitigate
risks and maximize human potential across a large number of projects,
teams, and technologies while repeatedly delivering results with
acceptable tradeoffs judged by our experience.

Many have also advocated radical changes in language and
development styles.  We have the gained the experience in
this process after watching radical changes fail for human and
technology elements not considered by the radical technologies
as proposed. We do learn from those that do succeed and incorporate
with reasoned process to mitigate risks.

One critial risk not forseen by many of these brash proposed changes
is observing that individuals have different degrees of ability to
manage
state in designs. Some with high natural ability can learn tosafely
manage
a very large amount of state with concurrency, and many more lack this
ability and after the best training can only handle significantly
smaller
amounts of concurrency in a design. This is not a training issue, this
is
not an experience issues, this is natural ability that is developed
with
training and experience, but the maximum for each individual is
independent of training and experience. Managing these differences in
natural ability causes tradeoffs in complexity that may not be the best
for some, but are best for organizations over time. It's not uncommon
to see briallant designs to be completely unmaintainable by mortals.

Time, and time alone, judges sucesses and failures. Not idealism
and insults.


Article: 91407
Subject: Re: icarus verilog
From: panteltje@yahoo.com
Date: 5 Nov 2005 05:31:00 -0800
Links: << >>  << T >>  << A >>

Kevin Brace wrote:
> Hi Jan,
>
> Although I understand the usual "your mileage may vary," but recently I
> spent two days trying to run a PCI IP core (Xilinx LogiCORE PCI
> compatible BDS XPCI PCI IP core) I developed with IVI (Icarus Verilog
> Interactive).
> The binary of IVI I used was ivi-0.4-pre-20031121-setup.exe from
> sourceforge.net
> (http://sourceforge.net/project/showfiles.php?group_id=53425), the last
> version without Eclipse.
> The reason I picked IVI instead of the regular Icarus Verilog was that I
> have not been successful running Icarus Verilog from Windows 2000's
I had a look at that, and then linked to the Eclipse site, and looked
at that.
Honestly :-) if withing 10 minutes or so I cannot figure out what
exactly it does
(Eclipse) and how it works and [how it] could speed up or improve the
whole process,
then I am out of there!
IBM must have dumped it into the public domain for the same reason, and
then
they can claim 'millions of dollars donations to open source'.....
So, you know, my sort of dream of GUI based FPGA software would be
something
that allowed me to drag and drop objects on a form (the FPGA), say a
filter, an IO block,
a Viterbi decoder, a multiplier, a FIFO, all sort of things.
And then click on it and specify its parameters
Make your own blocks too.
Do some interconnect by drawing a line and indicating number of bits,
add some processor
and code perhaps, and press 'realize', and it would recommend a FPGA
from some manufacturer, and generate a bitfile for it.

I do not usually check object code gcc produces, I trust it.... nor use
asm as output.
for inspection, gcc produces output for many processors.
In such a case anyways I could see the use of a GUI tool like that.
Maybe a dream...


Article: 91408
Subject: USB host
From: "Mich" <michiel.vanderlinden@gmail.com>
Date: 5 Nov 2005 06:07:11 -0800
Links: << >>  << T >>  << A >>
Hi,

I want to connect a webcame to a Virtex II pro and do some real time
processing on it. Can someone give me some tips how to use a Virtex II
pro as an USB host?

Greets
Mich


Article: 91409
Subject: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
From: air_bits@yahoo.com
Date: 5 Nov 2005 06:10:11 -0800
Links: << >>  << T >>  << A >>

Kolja Sulimma wrote:
> But apparently all those highly trained clever software engineers can
> not be bothered to learn another language. At least this argument
> allways comes up at that point. (Maybe I can find an engineer in india
> that is still capable of learning?)
> So if your really need C-syntax as many believe - I don't - at least use
> a modern C derived language that is easier to compile.
> With java essentially only the "new" operated is a problem. With C, well
> look at the System-C restrictions.

Open source know no boarders, no race, no religion, no ethnic, no
political, no barriers to who can contribute to the world.

Since you KNOW the answer, share it. We will be looking for your
work on sourceforge, and your announcement here. Good ideas which
are never realized, always ways worthless failures.

> On the other hand: What's so hard about dynamic allocation? Tell the
> designer that it will be slow, and if he uses it simply synthesize to a
> microblaze implementation. You will not meet the timing constraint, but
> it can be synthesized.

Good designs have excellent space time tradeoffs. CPU cores are large,
and take you right back to serial execution with poor parallelism, that
in
many cases would have been done better with a VLSI cpu, either as a
hard core, or external device. Likewise, pointer based memory takes
you right back to serial access of that memory as a critical path
resource. Dynamic allocation is implicitly serial by design.

> Or even use profiling to find a typicall number of allocated objects and
> create them in hardware. If more are used halt execution. That is
> exeactly what a sequential processor would. You can't call malloc a
> billion times in C and maybe you can not call it 16 times in hardware C.
> It is the same type of constraint that is not imposed by the language
> but by the implementation fabric and the designer needs to know the
> capabilities of his system before implementing.

A language designed around dynamic allocation of objects and classes
is implicitly unusable if limited to 16 such allocations, if only
trivial
code body invocations can be realized.

The multiplexors to emulate a memory pool of statically allocated
objects
are both huge and implicitly serial once hazzard free for conncurrent
access.
This takes us right back to poor space time tradeoffs and a lack of
implict
parallism that static objects offer.

Obviously you see right past these problems, and we are waiting for
your
magic to be realized as a much better language offering on
sourceforge.net.

Since the programmers in India are by your assertion superior, please
show
us by results, and time may prove you right.


Article: 91410
Subject: Re: Anybody understand this ISE 7.1 error, and what to do about it???
From: John_H <johnhandwork@mail.com>
Date: Sat, 05 Nov 2005 16:50:41 GMT
Links: << >>  << T >>  << A >>
"The RPM cannot have shift registers or distributed CLB SelectRAM 
(single port or dual port) in both odd AND even RLOC columns.  The 
SLICEL has a lookup table that's logic only while the SLICEM has LUTs 
that can be loaded and read as a single port memory, a dual-port memory, 
or a shift register."

So 1) find all your memory elements, and 2) move them around so they're 
either all in even RLOC columns or they're all in odd RLOC columns.

This will allow all you memory elements to be RLOCed into SLICEM slices.

- John_H


Andrew Lohbihler wrote:

> Thanks John,
> 
> The code did work for a Virtex-II and the details of the packing don't 
> indicate which column constraint was used. Any idea what constraint should 
> be changed to make it work in a Virtex-4? There must be a way to tweak the 
> design for the V4 to make it pack similarily as a V2. Any help will do.
> 
> Thanks,
> Andrew
> 
> "John_H" <johnhandwork@mail.com> wrote in message 
> news:YMQaf.57$Ge6.296@news-west.eli.net...
> 
>>Unlike earlier Virtex family devices, the Virtex-4 has half the slices 
>>allowed as memory-capable.  The RPM cannot have shift registers or 
>>distributed CLB SelectRAM (single port or dual port) in both odd AND even 
>>RLOC columns.  The SLICEL has a lookup table that's logic only while the 
>>SLICEM has LUTs that can be loaded and read as a single port memory, a 
>>dual-port memory, or a shift register.
>>
>>If the RPM was done for a project in a Virtex-IIPro or older device, 
>>you'll need to tweak it for the "odd or even column only" constraint of 
>>the Virtex-4.  If your RPM is fresh for this design, simply reconfigure it 
>>for the constraint you now know is getting in your way.
>>
>>- John_H

Article: 91411
Subject: Re: The HLL GUI multi-fpga DIME design environment
From: "Mike Treseler" <mike_treseler@comcast.net>
Date: Sat, 05 Nov 2005 09:38:21 -0800
Links: << >>  << T >>  << A >>
air_bits@yahoo.com wrote:

> For those that haven't looked at this stuff, it's the next generation
> HLL
> FPGA environment, two steps above C with a cute GUI based system level
> abstraction tool .... very cool :)
> 
> http://www.nallatech.com/mediaLibrary/images/english/4063.pdf


Yes. All of the next-gen websites are cute.
Why is a working code example so hard to find?

   -- Mike Treseler

Article: 91412
Subject: Re: Clock J4
From: johngalil@hotmail.com
Date: 5 Nov 2005 12:06:30 -0800
Links: << >>  << T >>  << A >>
Hi again,

After extensive reading and searching in documentation and board
schematic. I found the place of R15 and R13. It looks like these 2
resistors play the role of the controller of the multiplexer which
choose between the Y2 oscillator and the SMA connector. The question
is:

Does anyone know how to do the change asked in the note below? This
note is copied from the "Nios Development Board Reference Manual,
Stratix Edition"

Note to Figure 1-21:
(1) An external clock can be enabled by stuffing location R15 with a
49.9 ohm 0603 resistor and stuffing location R13 with a 330 ohm 0603
resistor.

Thanks in advance,
John


johngalil@hotmail.com wrote:
> Dear,
>
> I have a question regarding the "SMA connector J4" available on the
> Nios Development board, Stratix Edition. Can we use it only for an
> external clock? would it be possible to read any input signal from it,
> I have an idea how to get the clock so this is not an issue.
> 
> Thanks in advance,
> John.


Article: 91413
Subject: Re: The HLL GUI multi-fpga DIME design environment
From: air_bits@yahoo.com
Date: 5 Nov 2005 14:12:05 -0800
Links: << >>  << T >>  << A >>

Mike Treseler wrote:
> Yes. All of the next-gen websites are cute.
> Why is a working code example so hard to find?

You can always ask the various sites, or some user. Robin seems to
be using and happy with the DIME stuff, email him for some samples.
Have you tried talking with the company?

Impluse C offers a full featured 30 day trial, and they are pretty cool
to
talk with, and have done a good job of productizing Streams C.

Streams C is free for non-commercial use, and is available from
http://www.streams-c.lanl.gov/

SA-C by the Colostate team (Wimm Bohm) looks like they don't
intend to make it publically available, except to companies funding
their research projects.

ASH by the CMU guys, isn't likely to get open source released either,
and is likely to end up licensed to someone for a revenue stream
from what I was told by one person last year ... but I haven't seen
even that yet. Mihai Budiu appears to now be at Microsoft,
and publishing papers from there on the technology, so maybe
Microsoft will be licensing the technology, or working from Mihai's
development independent or in partnership with CMU. The papers
have been very cool, but until it's publicly available or a product
it's hard to judge just how useful for others. The ASH team offered
training at a conference earlier this year, and may do more.

Celoxica isn't quite as easy to get a demo copy from, but some Xilinx
reps seem to have a copy, and they were offering training seminars with
Xilinx across the country.

FpgaC has some examples in the download image, and is free to run
your own tests with, and has no restrictions against commerical use.

It seems pretty easy to get working examples simply by downloading
or asking the sales guys ... who didn't respond to your asking?


Article: 91414
Subject: Font requirements for patent applications
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 5 Nov 2005 19:04:24 -0800
Links: << >>  << T >>  << A >>
Hi,
In page 57, Chapter 600 of "Manual of Patent Examining Procedure", it
specifies what fonts can be used in an application for patent:
"(ii) Text written in a nonscript type font (e.g., Arial, Times Roman,
or Courier) lettering style having capital letters which are at least
0.21 cm (0.08 inch) high;"

I have been using "Times New Roman" font, because I cannot find "Times
Roman" in Microsoft Word software.

Is there any problem? Any advices or suggestions?

Thank you.

Weng


Article: 91415
Subject: Re: Anybody understand this ISE 7.1 error, and what to do about it???
From: "=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=" <taileb.mehdi@gmail.com>
Date: 5 Nov 2005 21:38:46 -0800
Links: << >>  << T >>  << A >>
But why were these changes done ? is it a sacrifice made by Xilinx to
allow adding XtremeDSP and other hard cores inside the Virtex-4 ?
Or is it simply because a few people use the CLBs as memory or shift
registers?


Article: 91416
Subject: Re: Font requirements for patent applications
From: "mindenpilot" <weissfamily97@charter.net>
Date: Sat, 5 Nov 2005 21:47:40 -0800
Links: << >>  << T >>  << A >>
I have submitted patent applications with Times New Roman with success.

Regards,

Adam

"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:1131246264.369823.4880@g47g2000cwa.googlegroups.com...
> Hi,
> In page 57, Chapter 600 of "Manual of Patent Examining Procedure", it
> specifies what fonts can be used in an application for patent:
> "(ii) Text written in a nonscript type font (e.g., Arial, Times Roman,
> or Courier) lettering style having capital letters which are at least
> 0.21 cm (0.08 inch) high;"
>
> I have been using "Times New Roman" font, because I cannot find "Times
> Roman" in Microsoft Word software.
>
> Is there any problem? Any advices or suggestions?
>
> Thank you.
>
> Weng
> 



Article: 91417
Subject: Re: icarus verilog
From: google@gornall.net
Date: 5 Nov 2005 22:29:44 -0800
Links: << >>  << T >>  << A >>
> mmm, my server, runs Linux 24/7:
> panteltje:~# uptime
> 10:36pm  up 52 days,  8:15,  7 users,  load average: 0.20, 0.60, 1.44
> It is pretty secure now with many bad guys in ipchains :-)

Mmm. I think he was being tongue-in-cheek. I have a linux cluster that
performs faultlessly, needing no human hand to guide it, running every
hour of every day of the year. The instant I take a holiday, however,
two disks on the RAID array will fail, or lightning will strike the
building, or something.

Both of the above have actually happened. When I was on holiday.

I'm beginning to believe in anti-magic.

Simon.


Article: 91418
Subject: Re: Anybody understand this ISE 7.1 error, and what to do about it???
From: Sylvain Munaut <com.246tNt@tnt>
Date: Sun, 06 Nov 2005 09:04:10 +0100
Links: << >>  << T >>  << A >>
GaLaKtIkUs™ wrote:
> But why were these changes done ? is it a sacrifice made by Xilinx to
> allow adding XtremeDSP and other hard cores inside the Virtex-4 ?
> Or is it simply because a few people use the CLBs as memory or shift
> registers?
> 
I'd say it's more because even if you do use the slice as memory & shift
egister, it's unlikely that you need ALL of them to be capable of that ...

So by only making half of them with this capability, you don't loose
much but I'd guess you win quite some space & complexity.


	Sylvain

Article: 91419
Subject: Re: Anybody understand this ISE 7.1 error, and what to do about it???
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Sun, 6 Nov 2005 22:28:51 +1300
Links: << >>  << T >>  << A >>
I believe it been said before by Xilinx.. that it was done to reduce the
silicon size.  Most designers don't use them so its no great loss.
And you shouldn't be using RLOCs from an older version silicon with a new
version anyway... the mapping is usually done for optimum timings and/or
placement... it doesn't automatically follow that what was best for a Vertex
2 is best for a vertex 3 or 4.

Simon


"Sylvain Munaut" <com.246tNt@tnt> wrote in message
news:436db9da$0$20585$ba620e4c@news.skynet.be...
> GaLaKtIkUs™ wrote:
> > But why were these changes done ? is it a sacrifice made by Xilinx to
> > allow adding XtremeDSP and other hard cores inside the Virtex-4 ?
> > Or is it simply because a few people use the CLBs as memory or shift
> > registers?
> >
> I'd say it's more because even if you do use the slice as memory & shift
> egister, it's unlikely that you need ALL of them to be capable of that ...
>
> So by only making half of them with this capability, you don't loose
> much but I'd guess you win quite some space & complexity.
>
>
> Sylvain



Article: 91420
Subject: Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!
From: "Alex Gibson" <news@alxx.org>
Date: Sun, 6 Nov 2005 23:48:09 +1100
Links: << >>  << T >>  << A >>

"Robert" <robertsolanki@gmail.com> wrote in message 
news:1131034844.173053.146390@f14g2000cwb.googlegroups.com...
> Hi,
> I am using the Spartan-3 development kit from Memec. I can't find my cd
> and need to use the USB. Can anyone send me the drivers. The file is
> supposed to be CP2101.exe or CP2101_Drivers.exe on the CD.
>
> Thanks in advance,
> Robert.

Sounds like the silabs (exCygnal) usb to usart chips.
may be able to use these
http://www.sparkfun.com/tutorial/USB-Drivers/ 



Article: 91421
Subject: Re: Anybody understand this ISE 7.1 error, and what to do about it???
From: "=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=" <taileb.mehdi@gmail.com>
Date: 6 Nov 2005 06:20:43 -0800
Links: << >>  << T >>  << A >>
:-O  Vitex 3 ?? never heard about it !!


Article: 91422
Subject: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
From: yusufilker@gmail.com
Date: 6 Nov 2005 07:15:50 -0800
Links: << >>  << T >>  << A >>
Hi,
I take a look at xapp807-Minimal Footprint Tri-Mode Ethernet MAC
Processing Engine.
Performance test results are at Table 5 of the document.

What i understand from the table TEMAC works at 90mbps.(max speed)
it is  supposed to work at least 990mbps, isn't it?
Where is the bottleneck , TEMAC , ultracontroller, FIFOs ?
How can we improve performance?

thanks,

yusuf


Article: 91423
Subject: Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
From: hmurray@suespammers.org (Hal Murray)
Date: Sun, 06 Nov 2005 10:08:15 -0600
Links: << >>  << T >>  << A >>
>What i understand from the table TEMAC works at 90mbps.(max speed)
>it is  supposed to work at least 990mbps, isn't it?
>Where is the bottleneck , TEMAC , ultracontroller, FIFOs ?
>How can we improve performance?

The limit is CPU cycles.  Software guys have done lots of work on
that area - mostly in the context of a full OS which normally
has the extra overhead of copying data between user and kernel
address spaces.

How you make it go faster depends upon what you want to do.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 91424
Subject: Re: icarus verilog
From: "gallen" <arlencox@gmail.com>
Date: 6 Nov 2005 10:42:11 -0800
Links: << >>  << T >>  << A >>
IVI is a mediocre GUI for icarus verilog.  I've used it before, but it
had problems (mostly with documentation).

Eclipse is a Java IDE.  It is written in Java and it is for making Java
programs.  There are extensions(C/C++, verilog, etc) that allow it to
edit other things with syntax highlighting and "intellisense," but they
are nowhere near as complete as the Java portion.

I have tried the eclipse verilog extension.  Quite frankly, it just
didn't come anywhere close to being as useful as verilog-mode for
emacs.  It may be better some day, but right now, I recommend using
emacs and verilog mode.  Perhaps Vim 7 will support "intellisense" like
operations in verilog and bring Vim verilog support up to at least
close to emacs.  Honestly though, I don't know what this has to do with
Icarus Verilog's website not working...

Anyway, I suggest folks try gpl-cver (it was linked in a previous post
in this thread).  Also of interest may be veriwell:
http://sourceforge.net/projects/veriwell .  Veriwell appears to have
been open sourced last month.  I know it's kind of old, but it has been
a well known verilog sim for a long time.

Good Luck,
Arlen




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