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Messages from 20875

Article: 20875
Subject: FPGA Express Synthesis Now Available Over The Internet
From: anup kumar raghavan <anup@elec.uq.edu.au>
Date: Fri, 25 Feb 2000 08:28:52 +1000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------417D43C4D5ECF592BE136BC2
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Content-Transfer-Encoding: 7bit


   Date:
        Thu, 24 Feb 2000 12:46:34 -0800
   From:
        Synopsys <Synopsys@nationalmailing.com>




Dear Actel, Altera, Atmel, Cypress, Lattice, Lucent, Quicklogic,
Triscend
and Xilinx FPGA designers.

Synopsys is proud to announce a new channel for its industry-leading
FPGA
Express synthesis tool. Synopsys has made FPGA Express available through

Toolwire, Inc. to run FPGA designs over the Internet. To run your VHDL
or
Verilog design through Synopsys' FPGA Express, go to
http://www.toolwire.com/gofpga.

No downloads, installations, or licenses are required, nor are there are

any minimum hardware requirements for the PC that you are using. All you

need is a browser(Internet Explorer version 4.72 and higher, or Netscape

version 4.06 and higher)because Toolwire's server farm, with FPGA
Express
installed on it, takes care of the whole process. The server farm takes
the
design you enter and runs it through FPGA Express itself, completely
offloading all processing from your PC. The synthesis flow, which you
specify, is also completely administered by the Toolwire process. When s

ynthesis is completed, Toolwire's server farm will automatically e-mail
you
with the results.

Other advantages of using FPGA Express from the Toolwire web site are:

- Ability to launch several designs or iterations simultaneously
- Ability to launch multiple synthesis strategies on a design
simultaneously
- Benchmarking: launch a design on multiple devices simultaneously
- Large resources: Leverage Toolwire's large server farm when your
resources
  aren't adequate (especially useful for large complex designs)
- Availability: Up and running 24 hours a day

FPGA Express users can also take advantage of Lucent's ORCA Foundry
place
and
route software which is also supported on Toolwire's site.

AND for a limited time (expires March 24, 2000), use of Synopsys FPGA
Express from Toolwire is available at no charge. After expiration, a
nominal charge will be applied on a per run basis (can be charged to a
credit card).

Look for additional tool support and productivity services to be
introduced
regularly from Toolwire.

Synopsys and Toolwire, Inc. are working together to eliminate the
barriers
between FPGA designers and industry-leading tools like FPGA Express.

To find out more about Synopsys FPGA tools, contact us at
mailto:fpga_sales@synopsys.com,
or call 1-800-441-1439.

We look forward to providing further Internet-based services to you.






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n:Anup Kumar;Raghavan
tel;home:0061-7-38761962
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url:www.csee.uq.edu.au
org:University of Queensland;Computer Science and Electrical Engineering
adr:;;;;;;Australia
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--------------417D43C4D5ECF592BE136BC2--

Article: 20876
Subject: Re: Xchecker schematic?
From: alex65536@my-deja.com
Date: Fri, 25 Feb 2000 00:46:48 GMT
Links: << >>  << T >>  << A >>
Sorry, this is not an XChecker cable. This is only a simple download
cable.

Tibor Szolnoki
szolnoki2@feemail.hu

In article <38B48C0C.3389135F@netscapeonline.co.uk>,
  rfbrw <rfbrw@netscapeonline.co.uk> wrote:
> try this.   www.pjrc.com/tech/xdownloader/
>
> Fuzesi Arnold wrote:
>
> > Hi All!
> >
> > I want to make my own xchecker cable.
> >
> > Is it possible ?
> >
> > Can I copy an original cable?
> >
> > Thanks,
> > Arnold
> > /Electrical Engineer Student/
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20877
Subject: Re: Design security
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 24 Feb 2000 17:08:50 -0800
Links: << >>  << T >>  << A >>


"Keith Jasinski, Jr." wrote:

> Some vendors of RAM based devices will try to pitch design security to you,
> but there is no way to truly secure a design that uses a bit-stream to
> program it.

Pages 14-41 and 42 in the Xilinx data book cover ( and have covered for years )
this subject.
Before you get into details, you must evaluate what level of security you need,
how high the barrier needs to be against reverse engineering or data theft. If
your attacker has unlimited resources ( like the former KGB  or other spooks),
a battery-backed-up SRAM-based FPGA might be the safest of all implementations.
Even antifuses and EEPROM-based designs can be cracked with enough effort.

And you don't want to put a $1000 lock on a $100 bike.

Peter Alfke, Xilinx Applications


Article: 20878
Subject: Re: Bit Serial Arithmetic De-mystified
From: rk <stellare@nospam.erols.com>
Date: Thu, 24 Feb 2000 20:51:43 -0500
Links: << >>  << T >>  << A >>
Bob Cain wrote:

> The first "home computer" that I know of was built by Don Hitt of IBM in
> the early sixties out of a recirculating acoustic delay line with a
> discrete component one bit ALU.  The architecture was ingeniously simple
> and it was at least a Turing.  Programming it so that the data and
> instruction you needed next was always close upstream was quite a
> challenge though.

More silly trivia ...

The computer in the Saturn V launch vehicle was a serial machine - for example,
a 26-bit add would take 82 us.

Also, glass ultrasonic delay lines were used to improve reliability.  The main
memory was duplex core.

And, lastly, the computer was designed by IBM.

Have a good evening,

rk

Article: 20879
Subject: Re: PWM implementation in Flex 10K.
From: steve (Steve Rencontre)
Date: Fri, 25 Feb 2000 03:00 +0000 (GMT Standard Time)
Links: << >>  << T >>  << A >>
In article <891nql$178s@r02n01.cac.psu.edu>, karapampuchi@yahoo.com 
(Balaji Rangaswamy) wrote:

> Can anyone direct me to a design example for implementating a pulse 
> width
> modulation (PWM) circuit in an Altera Flex 10K?  Design handbooks,
> tutorials,
> appnotes?

lpm_counter? Or is that too obvious?

--
Steve Rencontre, Design Consultant
http://www.rsn-tech.demon.co.uk
Article: 20880
Subject: $6 32 bit/33 MHz PCI Xilinx: Fact or Fiction?
From: "Ken Schmidt" <kenschmidtNOSPAM@earthlink.net>
Date: Fri, 25 Feb 2000 03:35:42 GMT
Links: << >>  << T >>  << A >>
What's the word on the street about Xilinx's recent annoucement regarding
their PCI offering. Two years ago, I was thrilled that I could build a PCI
bridge for $19 (although this required hardening the Xilinx). Now, $6 seems
too good to be true.

Who has the cheapest PCI target out there?

--Ken Schmidt
    Peerless Systems Corp.


Article: 20881
Subject: Re: Xilinx PCI pinout ?
From: "Ken Schmidt" <kenschmidtNOSPAM@earthlink.net>
Date: Fri, 25 Feb 2000 03:37:05 GMT
Links: << >>  << T >>  << A >>
Do you mind my asking you a couple of questions? First, what is your cost
target for your PCI Xilinx? Second,
are you planning on turning the Xilinx into a hard ASIC?

Thanks,
--Ken Schmidt
    Peerless Systems Corp.

"Nicolas Matringe" <nicolas@dotcom.fr> wrote in message
news:38B56158.3C805F18@dotcom.fr...
> Hi
> I plan to buy a Xilinx PCI Core for a SpartanII device but I can't find
> any information about the core pinout. I'd like to start working on the
> PCB layout as soon as possible.
> The planned device is an XC2S50-FG256.
>
> Any help, link... is greatly appreciated
>
> Thanks in advance,
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE


Article: 20882
Subject: Re: MRP systems
From: "Ralph Weir" <ralph@hunteng.demon.co.uk>
Date: Fri, 25 Feb 2000 09:22:00 -0000
Links: << >>  << T >>  << A >>
Hi Rick, this is just one of those diverse skills you're gonna need!  We're
fortunate in having infrastructure - a couple of people running purchasing
and stores, but we know how stressed they get...

Have you considered a kitting house?  You issue the BOM to them, they send
you a big box with all the bits in.  Easy, they cost a little more, but like
many things in life, you get what you pay for.

All the best,
Ralph Weir
Hunt Engineering
http://www.hunteng.co.uk

Rickman wrote in message <38B4BA0D.100D05D1@yahoo.com>...
>Fred Marshall wrote:
>>
>> Rickman,
>>
>> Saying QuickBooks (which is what I use) and MRP / integrated capabilities
>> seems quite a stretch when you consider the price of the packages.  If
>> you're just starting out, what's really wrong with simply buying in two
>> categories:
>> 1) reeled parts that come in relatively large quantities but aren't cost
>> drivers.
>> 2) all the others that you'll probably buy for each production lot.
>>
>> Just buy them off the BOM.  It's not that big a deal.
>>
>> If you really want to be prepared to be a much bigger company then you'll
>> probably be investing in all sorts of infrastructure around the MRP
system.
>>
>> It all revolves around how much you're willing to invest in software and
>> infrastructure.  I'll be interested to see if someone recommends an
>> inexpensive MRP package here as well.
>>
>> I had a survey article that I may be able to retrieve.  email me if
you're
>> interested.
>>
>> Regards,
>
>You make it sound so simple. I have found that the parts procurement
>process is the single most difficult part of running a company. I am
>planning on bringing an assitant on board to perform the office duties
>and will train for procurement. But this is not an easy process. The big
>problem has to do with the multiple part numbers and suppliers for each
>line item we need. Then all of the orders have to be tracked and with
>lead times of up to 12 weeks for some parts, it becomes a lot of work to
>make sure that all the parts will be in by the scheduled manufacturing
>start date. For just three small boards, I have 100 different passive
>components and 50 active ones. This also includes mechanical components
>and the PCBs.
>
>I am not trying to be rude, but if you don't see the difficulty of
>procurement, it is likely that you are not doing it. Or maybe I am just
>not doing it right... I know that I have a new found respect for buyers!
>
>If you have some info on this process, I would love to read it. Let me
>know!
>
>
>--
>
>Rick Collins
>
>rick.collins@XYarius.com
>
>remove the XY to email me.
>
>
>
>Arius - A Signal Processing Solutions Company
>Specializing in DSP and FPGA design
>
>Arius
>4 King Ave
>Frederick, MD 21701-3110
>301-682-7772 Voice
>301-682-7666 FAX
>
>Internet URL http://www.arius.com


Article: 20883
Subject: Re: Xilinx PCI pinout ?
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Fri, 25 Feb 2000 10:28:19 +0100
Links: << >>  << T >>  << A >>
Ken Schmidt a écrit :
> 
> Do you mind my asking you a couple of questions? First, what is your cost
> target for your PCI Xilinx? Second,
> are you planning on turning the Xilinx into a hard ASIC?

The PCI is only a part of the design and it needs the functionnalities
of the SpartanII family (especially BlockRAM)
We might turn to an ASIC later, at least for one design.

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 20884
Subject: DISTRIBUIDOR
From: "PEDRO C. GUILLEM VALENTIN" <GRUBER@TELELINE.ES>
Date: Fri, 25 Feb 2000 09:42:50 GMT
Links: << >>  << T >>  << A >>
MSGSL
¡BUSCAMOS DISTRIBUIDORES O INSTALADORES EN TODO EL MUNDO PARA NUESTRA GAMA
DE PRODUCTOS RELACIONADOS CON LA SEGURIDAD!
CAJAS FUERTES HOMOLOGADAS
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ARMARIOS DE SEGURIDAD
DESTRUCTOR DE DOCUMENTOS
TRANSMISORES TELEFONICOS
TRANSMISORES DE SONIDO AMBIENTE
RECEPTORES SERIE ALEX
ANULADOR DE TRANSMISORES
LOCALIZADORES DE TRANSMISORES
SCANNER
RADIO RECEPTORES
TRANSMISION RECEPCION DE VIDEO CAMARAS
TRANSMISION DE VIDEO POR LINEA TELEFONICA
TRANSMISION RECEPCION
DETECTORES RADAR
DISPOSITIVOS TELEFONICOS
DETECTORES DE ESCUCHAS TELEFONICAS Y ANULADORES
GRABADORAS DE CASETTE
ANTIESCUCHAS SECRAFONOS
CAMARAS DE VIDEO EN BLANCO Y NEGRO
GRABADORES DE VIDEO
CAMARAS DE VIDEO EN COLOR
SECUENCIADORES Y GENERADORES DE CUADRANTES
MONITORES DE VIDEO
RADIOLOCALIZACION
AMPLIFICADORES
DETECTORES DE METALES Y MINAS
SISTEMAS INFRARROJOS-LASER
MICROFONOS Y GRABACION POR CABLE
MICROFONOS Y AURICULARES PARA TRANSMISORES RECEPTORES
EQUIPOS PARA VEICULOS
SISTEMAS DE VISION NOCTURNA
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ANTENAS ESPECIALES PARA NUESTROS EQUIPOS
El perfil de las empresas que buscamos corresponde a empresas no muy grandes
y que ya vendan o instalen alguno de los artículos aquí expuestos.
Los distribuidores recibirán un código para acceder a nuestra tienda ON LINE
recibiendo el mismo trato comercial que los grandes distribuidores
establecidos.
Rogamos a los candidatos se dirijan a MSGSL por e-mail  especificándonos que
tipo de establecimiento regenta, si disponen de servicio técnico para
algunos de nuestros productos, zona geográfica de influencia, antigüedad en
la zona y naturalmente todos sus datos comerciales para poderle remitir su
código por e-mail en el caso de que sea seleccionado.
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con los primeros 100 artículos testados en laboratorio y con las
homologaciones pertinentes. Cada semana, se irán incorporando artículos a
dicha tienda a medida que superen nuestras exigencias, hasta alcanzar al
final de este año los mas de 3000 artículos que ya tenemos referenciados.
Los distribuidores seleccionados se irán agregando a nuestra lista que
aparecerá en nuestra pagina Web en el apartado de distribuidores oficiales.
Nuestra dirección provisional en Internet es gruber@teleline.es  y nuestra
direccion de la tienda ON LINE es msgsl.com





Article: 20885
Subject: Re: Design security
From: Andreas Heiner <Andreas.Heiner@de.bosch.com>
Date: Fri, 25 Feb 2000 11:29:36 +0100
Links: << >>  << T >>  << A >>



Peter Alfke <peter@xilinx.com> schrieb in im Newsbeitrag:
38B5D61E.5A53CE6@xilinx.com...
>
>
> "Keith Jasinski, Jr." wrote:
>
> > Some vendors of RAM based devices will try to pitch design security to
you,
> > but there is no way to truly secure a design that uses a bit-stream to
> > program it.
>
> Pages 14-41 and 42 in the Xilinx data book cover ( and have covered for
years )
> this subject.
> Before you get into details, you must evaluate what level of security you
need,
> how high the barrier needs to be against reverse engineering or data
theft. If
> your attacker has unlimited resources ( like the former KGB  or other
spooks),
> a battery-backed-up SRAM-based FPGA might be the safest of all
implementations.
> Even antifuses and EEPROM-based designs can be cracked with enough effort.
>
You're right, but the major problem is the copying of your design by
"normal" criminals. We're using a copy protected small CPLD (e.g. 9572XL)
and implement a back-coupled shift register and compares the behaviour of
this CPLD inside the FPGA. Of course, if you want to reverse engeneer the
design you can eleminate the design security. But this is a lot of work.
Even if we can't protect our design 100% we should protect it as much as
possible with possibly low cost. The external CPLD solution is such a
solution.

Best regards,

Andreas Heiner


Article: 20886
Subject: Re: Xilinx PCI pinout ?
From: Andreas Heiner <Andreas.Heiner@de.bosch.com>
Date: Fri, 25 Feb 2000 11:45:33 +0100
Links: << >>  << T >>  << A >>



Nicolas Matringe <nicolas@dotcom.fr> schrieb in im Newsbeitrag:
38B64B33.4B6F0234@dotcom.fr...
> Ken Schmidt a écrit :
> >
> > Do you mind my asking you a couple of questions? First, what is your
cost
> > target for your PCI Xilinx? Second,
> > are you planning on turning the Xilinx into a hard ASIC?
>
> The PCI is only a part of the design and it needs the functionnalities
> of the SpartanII family (especially BlockRAM)
> We might turn to an ASIC later, at least for one design.
>
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE


You should ask XILINX directly. There exists a retargetting guide for the
devices (at least for the virtex, but it should be the same for S2). Maybe
Xilinx can support you directly, if they already have the pinout for the
design.

Regards,

Andreas Heiner


Article: 20887
Subject: Re: Xilinx PCI pinout ?
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Fri, 25 Feb 2000 13:21:25 +0100
Links: << >>  << T >>  << A >>
Andreas Heiner a écrit :

> You should ask XILINX directly. There exists a retargetting guide for the
> devices (at least for the virtex, but it should be the same for S2). Maybe
> Xilinx can support you directly, if they already have the pinout for the
> design.

I got a response from Xilinx support. The FG256 pinout is not available
yet.

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 20888
Subject: Re: A FPGA hickup
From: Tim Tyler <tt@cryogen.com>
Date: Fri, 25 Feb 2000 13:51:51 GMT
Links: << >>  << T >>  << A >>
Hal Murray <murray@pa.dec.com> wrote:

: Try more heat/cold to make it fail more often.

Goodness!  I bet I won't find that advice in many manuals ;-)
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

The bigger they are, the harder they hit you.
Article: 20889
Subject: Re: Design security
From: "Keith Jasinski, Jr." <jasinski@mortara.com>
Date: Fri, 25 Feb 2000 07:58:59 -0600
Links: << >>  << T >>  << A >>
I have read the information you refer to in the Xilinx databooks.  In
addition, we are a Xilinx customer for our non-anti-fuse applications.

For a large majority of people, a battery backed FPGA is not an acceptable
solution.  The cost to add the battery and supply switching adds cost to the
product.  In addition, the concept that the product will cease to function
after a period of time (3-4 years maybe) is unacceptable.  It's not the same
situation as needing to reset a real-time clock when the battery expires.

To crack an anti-fuse device (at least the Quicklogic we use), you would
need to de-cap the device and die probe it.

And you MIGHT decide to put a $1000 lock on a $100 bike if someone who
steals the bike can make your bike and sell it to someone else for $10
because he didn't have to do the design work, essentially putting you out of
business.  If you are inplying that anti-fuse FPGAs are 10X as expensive as
RAM based, I would disagree with the argument.

It does not take someone with "KGB" type technology to capture and copy a
programming datastream to the FPGA.  The argument of suing someone if they
simply copy your datastream is valid, why would someone put themselves in
that position if you can simply eliminate that possibility?

My 2 cents...

--
Keith F. Jasinski, Jr.
kfjasins@execpc.com

Peter Alfke <peter@xilinx.com> wrote in message
news:38B5D61E.5A53CE6@xilinx.com...
>
>
> "Keith Jasinski, Jr." wrote:
>
> > Some vendors of RAM based devices will try to pitch design security to
you,
> > but there is no way to truly secure a design that uses a bit-stream to
> > program it.
>
> Pages 14-41 and 42 in the Xilinx data book cover ( and have covered for
years )
> this subject.
> Before you get into details, you must evaluate what level of security you
need,
> how high the barrier needs to be against reverse engineering or data
theft. If
> your attacker has unlimited resources ( like the former KGB  or other
spooks),
> a battery-backed-up SRAM-based FPGA might be the safest of all
implementations.
> Even antifuses and EEPROM-based designs can be cracked with enough effort.
>
> And you don't want to put a $1000 lock on a $100 bike.
>
> Peter Alfke, Xilinx Applications
>
>


Article: 20890
Subject: Re: Xilinx PCI pinout ?
From: "David Hawke" <dhawke@skynow.net>
Date: Fri, 25 Feb 2000 14:40:16 -0000
Links: << >>  << T >>  << A >>
Hi all,

The pinout for Spartan II by default supports the PQ208. Other density and
package combinations can
be supported by retargetting the core. The same rules apply as they did for
the Virtex parts.

There is a Retargetting guide available, but if you ask one of your local
Xilinx FAE's they can provide a
pinout for a particular package.

Sp2 is fast enough for this capability to retarget, similar to Virtex, but
unlike the SpartanXl or 4K.

Dave Hawke
Xilinx UK


Nicolas Matringe wrote in message <38B673C5.938E55A@dotcom.fr>...
>Andreas Heiner a écrit :
>
>> You should ask XILINX directly. There exists a retargetting guide for the
>> devices (at least for the virtex, but it should be the same for S2).
Maybe
>> Xilinx can support you directly, if they already have the pinout for the
>> design.
>
>I got a response from Xilinx support. The FG256 pinout is not available
>yet.
>
>Nicolas MATRINGE           DotCom S.A.
>Conception electronique    16 rue du Moulin des Bruyeres
>Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
>Fax 00 33 1 46 67 51 01    FRANCE


Article: 20891
Subject: Re: fpga
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 25 Feb 2000 07:34:56 -0800
Links: << >>  << T >>  << A >>
Serial PROMs use less board space in systems that do not already have a
processor.

However, if you look at their stand-alone cost, you might think that a cheap
processor plus a byte-wide processor is a cheaper solution, assuming you
have the board space.


--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------





<elynum@my-deja.com> wrote in message news:881me1$lln$1@nnrp1.deja.com...
> Thanks, guys!
> What would the benefits be to using a serial eeprom over an
> microprocessor or vice versa to program the fpgas?
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 20892
Subject: Re: Spartan-II Pricing - What gives?
From: "Ulf Samuelsson" <ulf.samuelsson@atmel.spamme.com.not>
Date: Fri, 25 Feb 2000 17:09:39 +0100
Links: << >>  << T >>  << A >>
The new AT94K40 FPSLIC from Atmel has 36 kByte of SRAM internally.
20kB is allocated to instructions for the internal Micro
and 4 kB is allocated to data for the same,
but it leaves you with 12 kB of SRAM for the FPGA +
the distributed SRAM which is part of the AT40K FPGA architecture.

--
This is a personal view which may or may not be shared
by my employer         Atmel Sweden
Ulf Samuelsson         ulf 'a't atmel 'd'o't com

Andy Krumel skrev i meddelandet ...
>Hi all,
>
>My company is working on a networking product that uses an FPGA for
>performing some analysis of Ethernet packets. The algorithms require quick
>access to some RAM based tables and dual port on-chip block Ram structures
>fit the bill perfectly. The final product is for a price sensitive market
so
>Xilinx's Spartan-II line looks perfect, but...
>
>I called a distributor to get pricing for 50,000 XC2S100 Spartan-II chips
>and received a quote of $58.65 (down from a single chip at $77). Yet
>Xilinx's literature claims this chip to cost under $10 in volume.
>
>What constitutes "volume" to get this kind of price?
>Is there an FPGA with 30-40K dual port RAM blocks that costs <= $10 in
>volumes of 50,000?
>
>Quote from http://www.xilinx.com/products/spartan2/index.htm:
>
>"Say hello to a new level of performance. The Spartan-II family delivers
>100,000 system gates for under $10, at speeds of 200 MHz and beyond,
>giving you design flexibility that's hard to beat."
>
>Also, I looked and looked and could not find any disclaimers or volume
>quotes for these prices. There are plenty of flashing GIFs proclaiming this
>price though.
>
>Thanks,
>Andy
>
>
>


Article: 20893
Subject: Re: MRP systems
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 25 Feb 2000 12:40:27 -0500
Links: << >>  << T >>  << A >>
Ralph Weir wrote:
> 
> Hi Rick, this is just one of those diverse skills you're gonna need!  We're
> fortunate in having infrastructure - a couple of people running purchasing
> and stores, but we know how stressed they get...
> 
> Have you considered a kitting house?  You issue the BOM to them, they send
> you a big box with all the bits in.  Easy, they cost a little more, but like
> many things in life, you get what you pay for.
> 
> All the best,
> Ralph Weir
> Hunt Engineering
> http://www.hunteng.co.uk

Yes, I have considered letting someone else do the kitting. This is not
a panacea since there are a number of parts that are long lead time or
that require you to be very creative as you beg on the phone. My concern
is that passing this responsibility off to a contract house will
increase my turn around time on these boards. Once I get into a steady
production rate this will be easier since I will be able to plan ahead. 

But the procurement is not my only problem. A good software package will
make many parts of running a business much easier. A lot of it has to do
with tracking vendors, invoices and the other office paperwork. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 20894
Subject: Re: Design security
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Fri, 25 Feb 2000 10:00:07 -0800
Links: << >>  << T >>  << A >>
Those concerned about design security against determined crackers with well equipped labs
will find little reassurance in the following survey paper: "Tamper Resistance - a Cautionary Note"
http://www.cl.cam.ac.uk/users/rja14/tamper.html

regards, tom

Peter Alfke wrote:
> 
> Before you get into details, you must evaluate what level of security you need,
> how high the barrier needs to be against reverse engineering or data theft. If
> your attacker has unlimited resources ( like the former KGB  or other spooks),
> a battery-backed-up SRAM-based FPGA might be the safest of all implementations.
> Even antifuses and EEPROM-based designs can be cracked with enough effort.
> 
> And you don't want to put a $1000 lock on a $100 bike.
> 
> Peter Alfke, Xilinx Applications

-- 
Tom Burgess
-- 
Digital Engineer
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3
Article: 20895
Subject: Foundation 2.1i device support?
From: milne@hi.com (Ewan D. Milne)
Date: 25 Feb 2000 18:09:06 GMT
Links: << >>  << T >>  << A >>
The Xilinx Online Silicon Xpresso Cafe allows you to
purchase Foundation 2.1i software in three packages:

    DS-FND-BAS-PC         $95.00
    DS-FND-BSX-PC         $495.00
    DS-FND-EXP-PC         $2495.00

These prices are presumably for 1-year renewable licensing.

However, the product details pages and the product comparisons
page contain different information about which devices are
supported.  In particular, the product comparisons page shows
that only XC4000 series parts are supported by any of these
packages.  However, the product details pages claim that
other device families are supported, such as XC3000, XC5200,
Spartan, and Virtex XCV50.

So, what devices are really supported by these packages?
The DS-FND-BAS-PC package at $95.00 is very inexpensive, much
like the Student Edition.  But the Student Edition device
support was somewhat limited.

I would be extremely pleased if the Base package contained
support for all of the above mentioned device families.

-Ewan

Article: 20896
Subject: Re: Using JTAG on XC4k
From: "Alain Cloet" <alain_cloet@hotmail.com>
Date: Fri, 25 Feb 2000 19:12:05 +0100
Links: << >>  << T >>  << A >>

Tim Forcer <tmf@ecs.soton.ac.uk.nojunk> wrote in message
news:38B4E4AB.DB0@ecs.soton.ac.uk.nojunk...
> Also implies that JTAG
> isn't used that much?
>
I can't remember your post exactly, although I know I read it, but I wasn't
able to answer to your question, so I didn't reply, but I wouldn't take it
so far that JTAG isn't used that much.  We do as much as possible, but more
for testing-purposes.

Greetings,
Alain



Article: 20897
Subject: Xilinx in system programmable proms and JTAG
From: Tom McLaughlin <tomm@arl.wustl.edu>
Date: Fri, 25 Feb 2000 14:24:07 -0600
Links: << >>  << T >>  << A >>
All,
We are planning on using the Xilinx 1800 series proms to program our
FPGAs.  Our plan is to solder them to the board and use the JTAG
interface to program them.  We are using some large and some small
FPGAs.  Some FPGAs need 2 PROMS.

Now, can I string all the PROMs together in a JTAG chain and select
which PROM I want to program via the JTAG software.

Now, assuming the above will work, I have another question.  Will the
FPGAs that require 2 proms have 2 separate bit files that I will
associate with the 2 different proms in the jtag software or is there
one bitfile and one logical device inside the software even though it is
2 proms???

I know you can string several FPGAs together and selectivly program
them, but how about the PROMs with their "in system
programability"??????
--
Tom

Article: 20898
Subject: Re: Foundation 2.1i device support?
From: "David Hawke" <dhawke@skynow.net>
Date: Fri, 25 Feb 2000 21:55:01 -0000
Links: << >>  << T >>  << A >>
Ewan,

BAS supports upto 4010/5210 in density, all Spartan(XL) and all the older
families.
It also supports all the Spartan2 range and the XCV50 and XCV50E.

BASX as above except you have Synopsys FPGA Express for VHDL and Verilog
support.

EXP everything upto the V1000(E)

Dave Hawke
Xilinx Apps


Ewan D. Milne wrote in message <896gg2$l4f$1@sunfish.hi.com>...
>The Xilinx Online Silicon Xpresso Cafe allows you to
>purchase Foundation 2.1i software in three packages:
>
>    DS-FND-BAS-PC         $95.00
>    DS-FND-BSX-PC         $495.00
>    DS-FND-EXP-PC         $2495.00
>





Article: 20899
Subject: Re: Looking for a small, fast CPU core for FPGA
From: Jamie Lokier <spamfilter.feb2000@tantalophile.demon.co.uk>
Date: 25 Feb 2000 23:42:22 +0100
Links: << >>  << T >>  << A >>
Nicholas C Weaver writes:
>>> It is under the LGPL, so you can use this in a commercial product.
>> 
>> A core for FPGAs under LGPL.  Now that has some interesting
>> implications.  Like, you can't just give someone a bitmap for your
>> commercial product.
>> 
>> You have to give them the source to the LGPL'd core _and_ files which
>> allow the recipient to change the LGPL'd core and reconstruct the FPGA
>> program.  E.g., a netlist EDIF for the application part.

> 	The important part about it being under the LGPL instead of
> the GPL is that you ONLY need to release the source for the core
> itself, not your whole design.  The LGPL, unlike the GPL, removes the
> viral nature or firewalling necessary to use GPL code in a larger
> project. 

You must release more than just the LGPLed core source.

Normally you provide finished hardware, either as a programmed FPGA, or
a bitstream, as a completed ASIC.

That's not enough if you used an LGPL core.  You don't have to provide
source for the rest of the design, but you must provide, or offer to
provide, these things:

  - Source for the LGPL core
  - A "linkable" form of the rest of the design.
    It must be enough information for the recipient to reconstruct
    the finished hardware with the LGPL core modified, or replaced.

A linkable form might be an EDIF netlist which can be combined with
recompiled LGPL core, for example, even if your design started from VHDL
or schematics.  Any obfuscation of the design source would also do.

The point is, that's a much harder constraint than is normally required
for hardware designs.

[ The precise rules are laid down in the COPYING.LIB document.  They
pertain to software, and are couched in terms like "compiling" and
"linking".  For hardware using standard EDA tools, a natural analogy
would have to apply. ]

If anyone uses an LGPL core written by me without satisfying the
licensing conditions, I *will* consider suing.  (But don't worry; I
haven't written any LGPL cores :-)

have a nice day,
-- Jamie


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