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"Steve Casselman" <sc@vcc.com> wrote in message news:5M0O9.1472$W34.116600010@newssvr21.news.prodigy.com... > I did a study for Xilinx once on accelerating their ppr code. I implemented > part of the placer (30% of the performance) and got it to go 9.8x faster. It > took about 1500 gates. From my analysis I thought you could put most > everything in about 50K-100K gates. They were just coming out with the > xc4028 at the time. I just pitched putting all of Mentors EDA tools in > hardware but they have a big NIH problem (actually even when they invent > something ala Butts et. al. they have a problem;-). I'm sure I could design > a system that could sell for about $5K that would speed up Par by 10x-20x > but I don't think Xilinx would go for it. It would be about a $2 Million > project most of it man power. Steve, Though that sounds nice, what about today? A 4028 is a many year old technology. The speed increase I'd rather have is the tool set (P&R specifically) being able to work with multiple processors. It's cheaper and far more robust. AustinArticle: 51051
In article <9d031b1e.0212271415.4873190f@posting.google.com>, Mike Butts <reconfigurable_logic@yahoo.com> wrote: >Hey Steve, how about using JBits? I'm surprised no one's mentioned >it in this thread. Part of the reason Xilinx makes JBits available >is so you can implement your own place & route tools. > >(JBits SDK is a Java toolset and API to the Virtex bitstream Xilinx > makes available to researchers. http://www.xilinx.com/products/jbits/) Actually, JBits frankly, SUCKS for that purpose. JBits is a nice direct access to bitfile API, and a very good one at that. But it could really use some more abstraction layers and similar utility features. But even if it did, its the wrong place, as you can't leverage Xilinx's router in the process. If you want to carry around/muck with the PPR/trace/bitgen flow, you really want to be working at the .xdl level. The big GOTCHA there is that the RPM placements (RLOC_ORIGINS) and similar constraints are not included in the .xdl file, so getting in between mapping and placement doesn't work well. So if you want to muck with the placer, you need to either get Xilinx to give you the documentation for other files in the flow, or write your own EDIF translator & mapping routines. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51052
Hi, I am a newbie in Virtex.I looked at the Virtex architeture recently. What does CE do in the D flip-flop block?I know it's clock enable signal. Does it mean when CE is low, the D flip-flop hold its previous value no matter how the clock switches? Is there any good material describing the interconnect structure of Virtex? Thank you very much! sincerely ------------- Kuan Zhou ECSE departmentArticle: 51054
In article <Pine.SOL.3.96.1021228144704.12169A-100000@vcmr-86.server.rpi.edu>, Kuan Zhou <zhouk@rpi.edu> wrote: >Hi, > I am a newbie in Virtex.I looked at the Virtex architeture recently. >What does CE do in the D flip-flop block?I know it's clock enable signal. >Does it mean when CE is low, the D flip-flop hold its previous value >no matter how the clock switches? Correct. Thats the poitn of a clock enable. > Is there any good material describing the interconnect structure of >Virtex? the datasheet and, for more details, teh Jbits documentation. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51055
Kuan Zhou wrote: > Hi, > I am a newbie in Virtex.I looked at the Virtex architeture recently. > What does CE do in the D flip-flop block?I know it's clock enable signal. > Does it mean when CE is low, the D flip-flop hold its previous value > no matter how the clock switches? Yes! Peter Alfke, Xilinx ApplicationsArticle: 51056
Nachiket Kapre wrote:
> is there a non-FLI based mechanism of probing the interal state of a
> Modlesim simulation? Since the msim kernel is implemented using TCL,
> can we do it through Tcl?
Here's one way.
At the gui tcl shell type:
add wave -r /*
Then run your testbench.
-- Mike Treseler
Article: 51057For some.. The System Gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFU's are used for logic only (No PFU RAM) with 40% EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLL's. For others it's different - Always use the LUT figure if you can... Steve "Steve Casselman" <sc@vcc.com> wrote in message news:eLOH9.3209$ti7.77237430@newssvr13.news.prodigy.com... > I think aoubt it this way: A regular "logic gate" is usually thought of as 2 > input nand gate. Since you can make anything out of nand gates anything you > can make can be expressed in the number of nand gates it would take to build > the design. The total "System Gates" number is the maximum "potential > gates" on the chip. By that I mean if had a design used every feature then > you would need that many nand gates to build the design. > > Steve > > PS if you want to know what kind a area your design will take in a certain > part you need to look at how many LUTs and Flops for a worst case number. > > "Steve" <steve1@mecca.com> wrote in message news:ee7ac4c.-1@WebX.sUN8CHnE... > I have a pre-made USB interface design which claims to use 16K-20K gates, > and I'm looking for an appropriate FPGA for implementing this. It seems that > most FPGA's (I've checked several of the Virtex and Spartan series) report > "system gates", and sometimes include "logic gates" as well. > What is the difference between these two? For example, the SpartanXL XCS50XL > says it has 13K-40K system gates and 20K max. logic gates. Where do the rest > of the system gates go? Are they all for RAM? > Also, what would the USB's gate count be referring to.. system gates or > logic gates? > Thanks! > -Steve > >Article: 51059
I used Xilinx Core Generator to build simulation model for dualport Ram, and it went through the synthesis phase by XTS, but during implementation phase, I got the error message said "dualport_ram is unexpected, ....", dualport_ram is my dualport RAM name. What is the black box name should I put in my code to pass this implementation phase as well as Place/Route phase? Thanks!Article: 51060
Hi, Just wondering if anyone has interfaced ordinary DRAM (72 pin simms) to an FPGA and are series damping resistors required ? Thanks, RobArticle: 51061
Dear Group, I am considering a career in VLSI and I would like to hear your advice on the following: -How sucessfull can a smaller design house from say a developing country (where there is no local demand for ASIC/Fpga) be in marketing and selling own IP designs- can it compete with companies like IBM or ARM..? I notice most of the jobs in tese countries are in design Verification and I wonder if those jobs are going to go elsewhere once our labor becomes much more expensive than for example in a less developed country? I suspect only few big countries can be leaders in CHIP design because US wants to keep its domination in Silicon industry by investing a lot in US universities and thus developing and keeping the know- how in US. Of course VLSI is a great career option but seems it cannot last to retirement? Any input highly appreciated TIArticle: 51062
TI wrote: > Dear Group, > I am considering a career in VLSI and I would like to hear your advice > on the following: > -How sucessfull can a smaller design house from say a developing > country (where there is no local demand for ASIC/Fpga) be in marketing > and selling own IP designs- can it compete with companies like IBM or > ARM..? > I notice most of the jobs in tese countries are in design Verification > and I wonder if those jobs are going to go elsewhere once our labor > becomes much more expensive than for example in a less developed > country? I suspect only few big countries can be leaders in CHIP > design because US wants to keep its domination in Silicon industry by > investing a lot in US universities and thus developing and keeping the > know- how in US. Of course VLSI is a great career option but seems it > cannot last to retirement? You are never going to compete with IBM and the like. And you will never do a Pentium4 or a PowerPC, but since the field is growing, there is plenty to be done. When your cost of labour has risen sufficiently for externals to become unattractive, there will be a local market, otherwise the cost would not have risen. At the beginning of your career you shouldn't think about retirement, there is a lifetime in between. While it 'could' last, keep always an option to something else, perhaps even to combine. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51063
Well what i actually wanted was probing of the simulation state i.e. modelsim variables such as time etc. now the problem is that if a simulation is running then the tcl command line gets disabled till the simulation is manually broken. I want to be able to do this without affecting the state of the simulation in any way.. Later on I also want to be able to break the simulation without having to explicitly click on the Break button. The directive for asserting a break can be given remotrly for example. there is a function vsim_break which does this but i am unable to find a mechanism to invoke this function while the simualtion is in progress. Also this process needs to be fli-free. regards, nachiket. Mike Treseler <tres@fluke.com> wrote in message news:<3E0E25B6.40006@fluke.com>... > Nachiket Kapre wrote: > > > > is there a non-FLI based mechanism of probing the interal state of a > > Modlesim simulation? Since the msim kernel is implemented using TCL, > > can we do it through Tcl? > > > Here's one way. > At the gui tcl shell type: > > add wave -r /* > > Then run your testbench. > > -- Mike TreselerArticle: 51064
anglomont@yahoo.com (TI) wrote in message news:<18a34598.0212290222.54ad6072@posting.google.com>... > Dear Group, > I am considering a career in VLSI and I would like to hear your advice > on the following: > -How sucessfull can a smaller design house from say a developing > country (where there is no local demand for ASIC/Fpga) be in marketing > and selling own IP designs- can it compete with companies like IBM or > ARM..? > I notice most of the jobs in tese countries are in design Verification > and I wonder if those jobs are going to go elsewhere once our labor > becomes much more expensive than for example in a less developed > country? I suspect only few big countries can be leaders in CHIP > design because US wants to keep its domination in Silicon industry by > investing a lot in US universities and thus developing and keeping the > know- how in US. Of course VLSI is a great career option but seems it > cannot last to retirement? > > Any input highly appreciated > > TI If you are in Germany, you can Google for FPGA, VLSI, ASIC, jobs, Stuttgart, Munich etc and many other combinations. On the FPGA board list just posted, there are a couple of German companies in the FPGA board bussiness including Stuttgart. Perhaps the Universities are doing something. There are a few semiconductor giants too, Infineon etc. Since I don't know German, can't say what the economy is like there, EEC is open job market too? http://www.fpga-faq.com/FPGA_Boards.htm As for the VLSI career, I am no longer sure it is long term, by definition it is changing very fast, everything you know has a half life of only a few years maybe 5yrs. Many skills that was once cool, are now hopelessly out of date. When you do retire, you will be retiring from something utterly unknown to today. Analog or RF skills might last longer.Article: 51065
Nachiket Kapre wrote:
> Well what i actually wanted was probing of the simulation state i.e.
> modelsim variables such as time etc.
Consider having the testbench code
compare actual and expected values.
> Later on I also
> want to be able to break the simulation without having to explicitly
> click on the Break button.
Consider using the built-in facilities
for viewing code and setting breakpoints.
-- Mike Treseler
Article: 51066Theron Hicks wrote: > > Jim Granville wrote: > > > Theron Hicks (Terry) wrote: > > > > > > Actually Glen, the device I am building _is_ a hot wire anemometer. The control > > > system is Pulse Width Modulated as opposed to the conventional Whetstone Bridge > > > based constant temperature anemometer. By using PWM we can get a better > > > transfer function and use a simple counter instead of an A/D converter. Also, > > > the system has a few other advantages. (See United States Patent #03603147.) > > > The real problem is that the fan ENI shows up in the Spectral Plot for the > > > recovered data from the anemometer. > > > > I would have expected the two to have different frequency bands - the > > FAN will be 100's of Hz, and the airflow sub-Hz ? > > > > Jim, > As it turns out the frequency of interest for the flow is up to on the order of > several KHz. The frequency of interest is defined by the size of the feature to be > resolved and the velocity of the flow. We look at features on the order of 1mm in a > 10m/S flow. Thus maximum frequency of interest is about 10KHz The fan has spectral > content from as low as about 150Hz to as high as 2.5KHz. The competetive full analog > product has a frequency response of about 30KHz at 10m/s flow velocity. Hmm, there goes that idea... More thermal mass -> Fins seems the best approach, & maybe experiment with a small compressed air cylinder - that will have no EMC :) It will have a finite life, but should tell you where the noise-floor is, for comparitive testing / demonstrations. -jgArticle: 51067
Hi all, Xilinx Answer Record # 15857 says "the input to an IBUF cannot be tied to ground" and if i do so the NGDBuild fails. Can anybody tell me why is it illegal to connect the input of an IBUF to GND? thanks, GanesanArticle: 51068
Hi Dasari, The MPGA project may be of interest: http://ce.et.tudelft.nl/~reinoud/mpga/README.html Best regards Tony Burch http://www.BurchED.biz FPGA boards for System-On-Chip prototyping and education "dasari" <dasariware@yahoo.com> wrote in message news:e1df9052.0212251805.10648805@posting.google.com... > Hai, > > I would like to know any free FGPA(lut based) cores available on net!! > (any architecure!) (VHDL/Verilog RTL/Netlist) > > Also,I would like to know some comparision of Varicore with any of the > xilinx Xc4000/vertex device in performance? > http://www.actel.com/varicore/index3.html > > > > Thanks, > Dasari.Article: 51069
Hai all, Can someone pass some functional info., and vhdl/verilog model for bus keeper, and bus gate logic! Thanks for the help. Valli.Article: 51070
sudharr@myw.ltindia.com (RANGA REDDY) wrote in message news:<37ba429a.0212270115.13517e0d@posting.google.com>... > hi, i am really fed up with this RAMDAC. i am not getting RAMDAC equivalent to one we r using i.e. BT481AKP-J110 bcos those RAMDAC is obsolete now and the manufacturers are completely out of those products. now we decided to use a combination of FPGA And Video DAC for replacing the RAMDAC. that means we r goin to use FPGA for implementing Color/overlay pallete. but the thing is we dont know the exact internal funcionality of the RAMDAC. that means how exactly they are controlling overlay and color information and both the data is given to the common DAC inside RAMDAC. so i would like to have complete information on that. so if any of u worked on that please advise me ASAP.or else if u find any equivalent to that pls tell me immediately to : sudharr@myw.ltindia.com regards, Ranga ReddyArticle: 51072
Do not waist money and time, switch to LATTICE ispLSI ! "Dave" <dfnr2@yahoo.com> wrote in message news:m34r8yao2s.fsf@yahoo.com... > Hello, > > I'm thinking of letting my Data I/O coast on without further software > updates, and put the money into a new BP programmer. I'm frustrated > by the lack of pricing information on the BP website, or any > distributors' sites. Would anyone who recently bought a BP-1200 care > to post some prices for the 1200, any of the extra modules, any > upgrades, and the software upgrade to generate serial numbers. > > Also, is it possible to write your own little program to generate > serial numbers, and have the free BP software call it, or do you still > have to pay for an "advanced features" package? > > It would be great if some kind soul posted some info here; > alternatively, I'd be grateful for a scanned pricelist by email. I've > contacted the local rep, but since there's no reply, I assume he's on > vacation. > > Thanks for any info, > > David. > -- > dave - dfnr2@yahoo.com >Article: 51073
Rob Finch wrote: > > Hi, > > Just wondering if anyone has interfaced ordinary DRAM (72 pin simms) to an > FPGA and are series damping resistors required ? I have not used standard DRAM with an FPGA, only SDRAM. But the electrical issues are the same. The series damping resistors are used for impedance matching to minimize reflections. If your traces are only 3 inches or so you won't need to worry with this. If your traces are 6 inches or more you definitely need to consider the issue. In between it depends on the details of your driver speed. So try to keep all your traces as short as possible. The RAS and CAS lines are of special concern since reflections can cause double clocking of the DRAM. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51074
I didn't know the Lattice ispLSI could program over 3000 different programmable devices. Silly me. Heck, I didn't even know they made a device programmer! ;-) "Mathew Orman" <orman@nospam.com> wrote in message news:aupgb7$157$1@news.tpi.pl... > Do not waist money and time, switch to LATTICE ispLSI ! > > "Dave" <dfnr2@yahoo.com> wrote in message news:m34r8yao2s.fsf@yahoo.com... > > Hello, > > > > I'm thinking of letting my Data I/O coast on without further software > > updates, and put the money into a new BP programmer. I'm frustrated > > by the lack of pricing information on the BP website, or any > > distributors' sites. Would anyone who recently bought a BP-1200 care > > to post some prices for the 1200, any of the extra modules, any > > upgrades, and the software upgrade to generate serial numbers. > > > > Also, is it possible to write your own little program to generate > > serial numbers, and have the free BP software call it, or do you still > > have to pay for an "advanced features" package? > > > > It would be great if some kind soul posted some info here; > > alternatively, I'd be grateful for a scanned pricelist by email. I've > > contacted the local rep, but since there's no reply, I assume he's on > > vacation. > > > > Thanks for any info, > > > > David. > > -- > > dave - dfnr2@yahoo.com > > > >
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