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Messages from 15075

Article: 15075
Subject: Re: High Fanout Signals
From: Khaled benkrid <k.benkrid@qub.ac.uk>
Date: Fri, 05 Mar 1999 03:55:40 +0000
Links: << >>  << T >>  << A >>
Hi!

Thanks for the reply. Actually I am describing the circuit from a high level
environment that I developed.
 It is a lot easier for me to use a single LFSR. Using multiple LFSRs needs
extra development of the my tools to generate the proper layout ( I am
generating placement information myself from a high level programming
environment which generates EDIF netlist). That's why I wanted to use high
fanout signals. May be I'll do an extra effort! - use multiple LFSRs-.



Article: 15076
Subject: Re: Looking for advice on CPLD's
From: ibaggett@bagotronix.com
Date: Fri, 05 Mar 1999 04:03:53 GMT
Links: << >>  << T >>  << A >>
On Thu, 4 Mar 1999 00:13:25 +0100, mesenich@t-online.de (Gerhard
Mesenich) wrote:

>Hi
>I intend to start to start with isp CPLD designs.
>
>My designs are usually quite simple. They are mainly intended for simple
>state machines,  address decoding, input/output buffering of analog
>converters and input capture of digital signals. They will mainly be used
>with 16bit DSP's. Packages should ideally be PLCC 44/84 (easy handling on
>experimental boards). I am already familiar with small PAL's (20v8 etc.).
>
>I have looked already at several chips. These are:
>
>Xilinx - XC 95xx
>Altera - MAX 7000
>Lattice - ispl..
>

I have used the Lattice devices in the 2000 series:  ispLSI2032, 2096,
and 2128.  They work well and the ispDS+ software is easy to use.
Well, at least the ABEL compiler is.  I haven't tried schematic
capture or VHDL with it.

I also have the Xilinx Foundation dev system but have not used it for
an actual product yet, so I can't give you a fair comparison.

>My applications are low volume/ research type. I do design work only very
>infrequently, so the design software should be as simple as possible and
>somewhat foolproof. A simple homebrewed parallel port cable should hopefully
>do the programming.
>

The Synario development system comes with a parallel download cable.
So does the Foundation dev system from Xilinx.

>Are there any suitable free integrated software packages?
>

Not that I know of, but the basic dev software has gotten pretty
cheap.  I got the Xilinx Foundation Base 1.4 for $99 U.S.  It does not
include VHDL - that is an extra cost add-on.

>Which family/ software package is best suited to my need? What are the
>approx. prices and how is availability? How well does schematic capture
>work - is it useful?
>

Have not used the Lattice schematic capture.  The Xilinx schematic
editor is crude and annoying, but it works.

Best regards,
Ivan Baggett
Bagotronix

Article: 15077
Subject: SPI Interface
From: Rinzai Bell <bellr@r-systems.com>
Date: Thu, 04 Mar 1999 20:28:12 -0800
Links: << >>  << T >>  << A >>
Has any one seen (or done) a multi-port parallel to SPI interface?

Thanks,

Rinzai J. Bell

Article: 15078
Subject: Looking for Mexicans working with FPGA
From: Miguel Arias-Estrada <ariasm@cseg.inaoep.mx>
Date: Thu, 04 Mar 1999 22:34:36 -0600
Links: << >>  << T >>  << A >>
Hello there,

This message is intended for mexicans working with FPGAs or
VLSI architectures for their graduate research. Please
forward if you know somebody. Thank you.

Miguel

-----
Hola:

Estoy trabajando en el INAOE-Puebla con tecnologias FPGA
(Field Programable Gate Arrays) y Computo Reconfigurable
Dinamicamente, para el diseno de arquitecturas digitales
orientadas a la vision por computadora. Estamos construyendo

un sitio sobre diseno e investigacion en FPGAs y
arquitecturas VLSI en Mexico y queremos contactar a gente
estudiando posgrados en dicha area (en Mexico o en el
extranjero)
para montar un directorio. Por favor, la gente involucrada
podria
mandarme los siguientes datos?

-----------------------------
Nombre:
Programa y grado de estudio:
Fecha estimada de titulacion:
Universidad y Departamento:
Correo Electronico:
URL:
Titulo de la Investigacion:
Fabricantes de FPGAs que utiliza o mencionar si se trabaja
en otros aspectos relacionados con FPGAs/VLSI (como CAD,
paradigmas de computo reconfigurable, nuevas arquitecturas
para FPGA, etc.):
Areas de interes con los FPGA:
-------------------------------


Gracias y saludos desde Puebla

Miguel Arias Estrada
-----------------------------------------------------------
  Miguel Arias-Estrada      |    Researcher/professor
-----------------------------------------------------------
INAOE - Electronics Dept.   | Tel: +52 (22) 47-2011 #1410
Apdo. Postal 51 y 216       | Fax: +52 (22) 47-0517
72000 Puebla, Pue.          | ariasm@inaoep.mx
MEXICO                      | http://cseg.inaoep.mx/~ariasm
-----------------------------------------------------------

Article: 15079
Subject: Can multiple FPGA share same SPROM for configuration?
From: "J.P.Liao" <jpliao@ms6.hinet.net>
Date: 5 Mar 1999 06:17:11 GMT
Links: << >>  << T >>  << A >>
I have 16 Xilinx 4010 FPGA in a PCB board, they used same SPROM, (same
design).
Can these FPGA share same SPROM when power on configuration?
Could any one can show me how to do that?

Thanks!
J.P.Liao
QtS


Article: 15080
Subject: I/O standards revisited
From: "Rune Baeverrud" <fpga@iname.com>
Date: Fri, 5 Mar 1999 09:59:14 +0100
Links: << >>  << T >>  << A >>
Working with the new Xilinx Virtex family has made me curious about all the
different I/O standards that it support. The Virtex supports the following
standards:

LVTTL
LVCMOS2
PCI
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 Class I and II
SSTL2 Class I and II
CTT
AGP

The electrical properties of these standards are described in the Virtex
datasheet and XAPP133 "Using the Virtex SelectIO".

What I would like to do now is gathering some information on the history and
typical use of these standards. Searching the Internet gave me very little
information on the newer standards, so I was hoping that you out there could
help me to locate this information. Newer standards not mentioned above are
also of interest.

The result of this survey will be published at http://freecore.com

Regards,
Rune Baeverrud


Article: 15081
Subject: Re: ALTERA pin assignment
From: "Francisco Josť Blasco Abril" <fblasco@tapec.uv.es>
Date: Fri, 05 Mar 1999 10:11:09 +0100
Links: << >>  << T >>  << A >>
Hi:

Welcome at club of crashing-minds.
It's no easy what you want to do. The assignment must be do from the
"Floorplan editor". Then you can assing pin groups to LABS. It's
convenient what you divide your logic core in sections, and you must
intend to distribute it in the LABS.
For example: if you have a 8 bit input data bus, you must assign this
inputs to LAB A (or B or C ...), but in one LAB. Then you don't collapse
the LABS interconnections.

Luck. Only experience can help you. 

One note: You must begin to assign a pin group, the you must compile the
design and you must probe that it's all right. Then you must assign
another pin group and so on.

Bye!!.
Article: 15082
Subject: Re: High Fanout Signals
From: Khaled benkrid <k.benkrid@qub.ac.uk>
Date: Fri, 05 Mar 1999 10:08:51 +0000
Links: << >>  << T >>  << A >>
Hi!

Thanks for the reply. Actually I am describing the circuit from a high level
environment that I developed.
 It is a lot easier for me to use a single LFSR. Using multiple LFSRs needs
extra development of the my tools to generate the proper layout ( I am
generating placement information myself from a high level programming
environment which generates EDIF netlist). That's why I wanted to use high
fanout signals. May be I'll do an extra effort! - use multiple LFSRs-.



Article: 15083
Subject: Re: Looking for advice on CPLD's
From: "Uday Godbole" <udayg@technofour.com>
Date: Fri, 5 Mar 1999 16:18:12 +0530
Links: << >>  << T >>  << A >>
You can try the Xilinx CPLD starter kit for $100.  Available from insight
electronics, includes almost everything you need.


Gerhard Mesenich wrote in message <7bkfp4$9ht$1@news05.btx.dtag.de>...
>Hi
>I intend to start to start with isp CPLD designs.
>
>
>with 16bit DSP's. Packages should ideally be PLCC 44/84 (easy handling on
>experimental boards). I am already familiar with small PAL's (20v8 etc.).
>
>I have looked already at several chips. These are:
>
>Xilinx - XC 95xx
>Altera - MAX 7000
>Lattice - ispl..
>
>
>Are there any suitable free integrated software packages?
>
>Which family/ software package is best suited to my need? What are the
>approx. prices and how is availability? How well does schematic capture
>work - is it useful?
>

In a couple of days you will get the hang of it.  The thing really works!

Uday



Article: 15084
Subject: Re: Can multiple FPGA share same SPROM for configuration?
From: "Paul T. Shultz" <paul@csciences.com>
Date: Fri, 05 Mar 1999 07:20:23 -0500
Links: << >>  << T >>  << A >>
"J.P.Liao" wrote:

> I have 16 Xilinx 4010 FPGA in a PCB board, they used same SPROM, (same
> design).
> Can these FPGA share same SPROM when power on configuration?
> Could any one can show me how to do that?
>
> Thanks!
> J.P.Liao
> QtS

You should be able to configure all 16 devices from a common sprom set.  I
can think of two approaches.  The first is a simultaneous serial load and
the second uses a daisy chained approach.

If all 16 FPGAs are the same design I think you could use a single,
globally connected sprom.  I would make 1 FPGA a serial master and the
other 15 serial slaves.  Connect all the programming clocks together.
Connect the sprom data out pin to all FPGA DIN pins.  Connect the proper
control signals from the master FPGA to the sprom and other slave FPGAs.
This includes LDC* (to sprom) and INIT* (to sprom and other FPGAs) (see
figure 52 in the Xilinx 1998 data book).  Once the configuration process
starts the master FPGA provides a common programming clock and all FPGA
receive the programming data from the single sprom. I haven't attempt this
approach and with 16 loads you may need to worry about signal fan out.

Another, lower risk approach uses the Master/Slave Serial Mode.  This is
detailed in the Xilinx data book (for the 4000 series see Figure 52, page
4-61 in the 1998 Data Book).  Basically the FPGA configuration data path
is serially daisy chained. The size of the sprom(s) will be 16 * 178096
bits for X4010E or 16 * 283376 bits for the XC4010.  If you can't find a
sprom big enough you can also daisy chain sproms. The Xilinx tool set has
a sprom formatter where the individual FPGA images are combined and
assigned to the sprom.  A single programming file is the end result.

I hope this helps.

Regards,

Paul T. Shultz
Chesapeake Sciences Corporation
<paul@csciences.com>


Article: 15085
Subject: Re: I/O standards revisited
From: tryggvem@my-dejanews.com
Date: Fri, 05 Mar 1999 12:56:01 GMT
Links: << >>  << T >>  << A >>
In article <7bo632$ku4$1@romeo.dax.net>,
  "Rune Baeverrud" <fpga@iname.com> wrote:
> Working with the new Xilinx Virtex family has made me curious about all the
> different I/O standards that it support. The Virtex supports the following
> standards:

Another feature that should be possible:
Why not use the Vref and the flexible SelectIO inputs for implementation
of voltage comparators for analog signal with in voltage range.

This should make it possible building simple A/D converters(using D/A and PWM
outputs) without needs of external IC's.

Any opinions? Or is this impossible?

Regards,

Tryggve Mathiesen

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15086
Subject: Re: High Fanout Signals
From: Ray Andraka <randraka@ids.net>
Date: Fri, 05 Mar 1999 09:35:16 -0500
Links: << >>  << T >>  << A >>
If you are already generating layout, why can't you just repeat the LFSR layout
with an offset?

Khaled benkrid wrote:

> Hi!
>
> Thanks for the reply. Actually I am describing the circuit from a high level
> environment that I developed.
>  It is a lot easier for me to use a single LFSR. Using multiple LFSRs needs
> extra development of the my tools to generate the proper layout ( I am
> generating placement information myself from a high level programming
> environment which generates EDIF netlist). That's why I wanted to use high
> fanout signals. May be I'll do an extra effort! - use multiple LFSRs-.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15087
Subject: Re: I/O standards revisited
From: mcgett@feynman.xsj.xilinx.com (Ed McGettigan)
Date: 5 Mar 1999 08:37:54 -0800
Links: << >>  << T >>  << A >>
In article <7bok8u$hjl$1@nnrp1.dejanews.com>,
 <tryggvem@my-dejanews.com> wrote:
>In article <7bo632$ku4$1@romeo.dax.net>,
>  "Rune Baeverrud" <fpga@iname.com> wrote:
>> Working with the new Xilinx Virtex family has made me curious about all the
>> different I/O standards that it support. The Virtex supports the following
>> standards:
>
>Another feature that should be possible:
>Why not use the Vref and the flexible SelectIO inputs for implementation
>of voltage comparators for analog signal with in voltage range.
>
>This should make it possible building simple A/D converters(using D/A and PWM
>outputs) without needs of external IC's.
>
>Any opinions? Or is this impossible?
>

Unfortunately this is not possible within the Virtex device.
The diff-amp/voltage comparator input buffers do not have
rail-to-rail capability and so they are not capable of 
discriminating across the full 0-3.3V range.

Ed
Article: 15088
Subject: Re: Fast-turn ASIC vendors
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Fri, 05 Mar 1999 17:40:58 GMT
Links: << >>  << T >>  << A >>
On Thu, 04 Mar 1999 19:26:51 GMT, Todd Kline <todd@wgate.com> wrote:

>Actually, I'd love to use the ARC core.  It is hands down my first choice
>for a soft core.  Unfortunately, my boss balks at the up-front license fee
>of soft cores, even the "relatively" low fee for the ARC.  We are a
>start-up, so cash flow management is extremely important.

Todd, your email address bounced. Please mail me on

stuart 'at' saros 'dot' co 'dot' uk

Thanks
Stuart
For Email remove "NOSPAM" from the address
Article: 15089
Subject: Re: Can multiple FPGA share same SPROM for configuration?
From: bibico <pobox303@usa.net>
Date: Fri, 05 Mar 1999 18:46:38 +0100
Links: << >>  << T >>  << A >>
Put one device in the serial master mode ( This device will give the
serial clock ) put the others in the serial slave mode and connect all
datalines in together ( do not daisy chain the data ).


J.P.Liao wrote:

> I have 16 Xilinx 4010 FPGA in a PCB board, they used same SPROM, (same
> design).
> Can these FPGA share same SPROM when power on configuration?
> Could any one can show me how to do that?
>
> Thanks!
> J.P.Liao
> QtS



Article: 15090
Subject: Re: Looking for advice on CPLD's
From: gerald coe <devantech@devantech.demon.co.uk>
Date: Fri, 5 Mar 1999 18:27:42 +0000
Links: << >>  << T >>  << A >>
In article <7bkfp4$9ht$1@news05.btx.dtag.de>, Gerhard Mesenich
<mesenich@t-online.de> writes
>Hi
>I intend to start to start with isp CPLD designs.
[snip]
>Thanks a lot for any help, opinion and recommendation.
>
The programmable logic jump station at www.optimagic.com is a good place
to start hunting.

-- 
Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031,
Gerald Coe      | .demon.co.uk    | 68302, 64180, 80C188EB cpu modules. 
http://www.devantech.demon.co.uk  | Full custom uP control systems designed.
Article: 15091
Subject: Re: Can multiple FPGA share same SPROM for configuration?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 05 Mar 1999 10:34:40 -0800
Links: << >>  << T >>  << A >>
J.P.Liao wrote:

> I have 16 Xilinx 4010 FPGA in a PCB board, they used same
> SPROM, (same
> design).
> Can these FPGA share same SPROM when power on
> configuration?
> Could any one can show me how to do that?
>  

   Very simple: One of your XC4010s gets its mode pins
connected as Master Serial, all the other ones as Sleve
Serial. Then you interconnect all CCLKpins and connect them
to the SPROM CLK, and you interconnect all DIN pins and 
connect them to the SPROM Data pin.
You also interconnect all INIT pins and use them as the
SPROM active Low RESET.

Considering the high fan-out, it may be wise to stay with
the slower CCLK rate of 1 MHz.

Good luck, this is easy.

Peter Alfke, Xilinx Applications

Article: 15092
Subject: Re: Problem with xilinx M1
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Fri, 05 Mar 1999 16:13:01 -0500
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> 
> I'm not sure you can have a chip with more than one top-level module!
> 
> Why would you want to do that????
> 
> -andy

I believe he said in earlier postings that he was instantiating these
modules in a seperate schematic diagram as black boxes. Then that is the
top level from the device point of view. The trick is to get the
synthesis tool to understand that the VHDL is no the top level... sort
of like "macro mode" in Exemplar Leonardo. I don't know how that is done
in FPGA Express, and apparently neither does Sergio. That is the nature
of the question now.

-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>

Article: 15093
Subject: Re: Foundation V1.5 Crash
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Fri, 05 Mar 1999 16:21:00 -0500
Links: << >>  << T >>  << A >>
Since I also scrapped the gui in favor of an automatic batch file, I am
beginning to wonder how many others have done the same thing. Since I
know Xilinx monitors this news group, I would be interested in
generating some user ffedback to them about the gui interface and it's
lack of flexibility for the power users.

I personally found the attempt at version management pretty bad and the
gui hard to use because of it (maybe they could provide a method to TURN
IT OFF!).

I also found it a pain to find the options I wanted to change buried in
the various option dialogs, and there are just too many buttons to press
to get from edif file to Intel Hex file. I like to start the batch file
running (which I built in error checking), walk away, and come back in
half-hour to see if it done. My time is too valuable to sit there and
babysit a GUI just to press buttons.

Jeff Hunsinger wrote:
<snip> 
> .....I quickly
> gave up on it and just run the whole thing from the command line with a
> make file.
> 

-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>

Article: 15094
Subject: Re: Getting started in programmable logic
From: Ray Andraka <randraka@ids.net>
Date: Fri, 05 Mar 1999 16:56:07 -0500
Links: << >>  << T >>  << A >>


Steve Dewey wrote:....

> A good example is the 10 bit counter you need. Typically you might have to wire
> that up using 3 4-bit counters, if restricted to TTL 74 series style functions.
> The alternative is just to use a LPM_COUNTER WITH (LPM_WIDTH=9). If your
> requirment changes, then just change the LPM_WIDTH value. If you choose to
> design in Altera Hardware Design Language (AHDL) you can define a parameter
> early in the design file, and declare your counter and any other datapath
> elements in terms of that parameter. This parameter can be passed down to
> whatever level of hierarcy nesting you like.
>
> I know of no other HDLs that provide this facility - allowing that VHDL &
> Verilog are synthesis languages rather than simple hardware description
> languages. Please correct me if I'm wrong.
>

VHDL will let you do this by using generics. You can explicitly construct hardware
just as you can in AHDL.  The synthesis engines don't have the nice functions like
LOG2 in them, so constructing something whose number of stages varies with the width
like an adder tree is easier in AHDL (although if you add the IEEE.math_real library
to the synthesizer that is fixed).  The biggest drawback to AHDL is that you can't
use it for another vendor's part.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15095
Subject: programming cplds and serial roms and fpgas
From: bob elkind <eteam@aracnet.com>
Date: Fri, 05 Mar 1999 14:34:24 -0800
Links: << >>  << T >>  << A >>
Is there a common, single solution set for hw and sw to program FPGAs and serial ROMs and CPLDs, from a PC parallel port to a
JTAG port?

Xilinx has the Parallel Cable (with software modules that are proprietary to Xilinx)...

Altera has the JAM language and Byte Blaster (and JAM is officially non-propietary,
   but is there JAM support for non-Altera devices?)...

Altera's ByteBlaster is very similar to Xilinx' Parallel Cable, except the pinouts are different.  Hence the SW to drive them is
different.  Is there a single, common solution for programming and/or testing A's and X's devices that are both JTAG supporters
?

Thanx in advance,

-- Bob Elkind, eteam@aracnet.com
Article: 15096
Subject: Current State of FPGA-based PCI Interfaces?
From: "Bob Bauman" <bbauman@lynxstudio.com>
Date: Fri, 5 Mar 1999 15:35:38 -0800
Links: << >>  << T >>  << A >>
Hi all,

About a year and a half ago I was considering implementing a PCI interface
in an FPGA. At that time I decided that the design was going to be very time
consuming and posed compatibility risks. Altera's and Xilinx's cores seemed
to require quite a bit of tweaking and they were expensive.

As I embark down this path again, I thought I might illicit the response of
this newsgroup to the current state of PCI cores and development tools
supplied by Altera, Xilinx, and others. Hopefully, this topic was not just
recently discussed in a thread that I missed. If so, I would appreciate
being directed to an archive.

From my initial survey it appears that Xilinx has put the most effort into
supplying PCI cores of various flavors that are supposedly easy to plunk
into a design. Is this observation correct ? Does anyone who has used either
or both of the Altera and Xilinx cores have any strong opinions?

Generally, are how much tweaking with placement and timing constraints is
required for the current crop of cores?

Thanks in advance.

Bob Bauman



Article: 15097
Subject: Re: I/O standards revisited
From: Brad Taylor <blt@cmln.com>
Date: 05 Mar 1999 18:50:47 PST
Links: << >>  << T >>  << A >>
You can get the low voltage standards right from JEDEC at:

http://www.jedec.org/download/freestd/jesd8-xx/

Rune Baeverrud wrote:
> 
> Working with the new Xilinx Virtex family has made me curious about all the
> different I/O standards that it support. The Virtex supports the following
> standards:
> 
> LVTTL
> LVCMOS2
> PCI
> GTL
> GTL+
> HSTL Class I
> HSTL Class III
> HSTL Class IV
> SSTL3 Class I and II
> SSTL2 Class I and II
> CTT
> AGP
> 
> The electrical properties of these standards are described in the Virtex
> datasheet and XAPP133 "Using the Virtex SelectIO".
> 
> What I would like to do now is gathering some information on the history and
> typical use of these standards. Searching the Internet gave me very little
> information on the newer standards, so I was hoping that you out there could
> help me to locate this information. Newer standards not mentioned above are
> also of interest.
> 
> The result of this survey will be published at http://freecore.com
> 
> Regards,
> Rune Baeverrud

-- 

----------------------------------------------------------------
Web Page:       file:////chamfs/share/applications/web/top.html
----------------------------------------------------------------
Brad Taylor     Chameleon Systems
Phone:          1-408-730-3300 ext 108
Fax:            1-408-730-3303
Email:          <Brad Taylor> blt@cmln.com
WWW:            www.cmln.com
Location:       1195 W. Fremont Ave
                Sunnyvale, CA 94087-3825
----------------------------------------------------------------
Article: 15098
Subject: Re: Problems inferring RAM memory
From: ems@riverside-machines.com.NOSPAM
Date: Sat, 06 Mar 1999 13:08:05 GMT
Links: << >>  << T >>  << A >>
On Tue, 02 Mar 1999 18:13:37 +0000, Eduardo Augusto Bezerra
<E.A.Bezerra@sussex.ac.uk> wrote:

>
>Hello
>
>I want to use VHDL in order to have a technology independent
>implementation, but the problem is that VHDL is not synthesis
>tool independent. Is it correct? Is it possible to have only
>one VHDL description which can be used for several synthesis
>tools to infer memory to different FPGAs?

The problem here is that simulation and synthesis tools work
differently. A synthesiser doesn't attempt to "run" (ie. simulate)
your code - it looks for templates for things that it knows about.
With the common tools, both Spectrum and Synplify understand RAM
templates, but Express doesn't. Express's code will probably work, but
it will be inefficient, as you've found out.

I wouldn't personally recommend coding for RAM, at least until
everyone agrees on a common template. Todd's suggestion would be
better.

Evan

Article: 15099
Subject: newbie question about PALASM 1.5
From: wpadrao@dcc.ufmg.br (Wilton de Castro Padrao)
Date: 6 Mar 1999 13:54:12 GMT
Links: << >>  << T >>  << A >>
Hi,

How can I specify the PAL package in PALASM 1.5?

I'm trying to compile for PALCE22V10, PLCC package.

Best Regards,


Wilton Padrao



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