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Messages from 175

Article: 175
Subject: FPGA `95 Symposium Second Call for Papers
From: jayar@eecg.toronto.edu (Jonathan Rose)
Date: 9 Sep 94 14:39:20 GMT
Links: << >>  << T >>  << A >>
		    FPGA '95: Second Call for Papers
		1995 ACM/SIGDA International Symposium on
		    Field-Programmable Gate Arrays

		    Chaminade at Santa Cruz, California
			February 12-14, 1995

This symposium has evolved from two previous workshops, FPGA '92 and 
FPGA '94. As Field-Programmable Gate Arrays become more essential to the 
design of digital systems there is increased desire to improve their 
performance, density and automated design. This symposium, sponsored by 
ACM/SIGDA, seeks contributions, but is not limited to, the following areas:

+ FPGA Architecture: logic & routing, memory, I/O, new commercial architectures.

+ Interactions: between CAD, architecture, applications, and programming 
  technology.

+ Applications: novel uses of FPGAs

+ Process Technology-Issues Related To FPDs

+ CAD for FPGAs: Logic optimization, technology mapping, placement, routing

+ Field-Programmable Systems: emulation and computation, partitioning across 
  chips

+ Field-Programmable Interconnect Chips/Devs

+ Field-Programmable Analog Arrays

Authors should submit 20 copies of their work (maximum 10 pages, minimum 
point size 10) by October 3, 1994. Notification of acceptance will be sent 
by November 20, 1994. 

A proceedings of accepted papers will be published (which is different from 
the publication policy of the previous related workshop). Final papers will 
be limited in length to six pages. Submissions should be sent to:

Jonathan Rose
FPGA '95
Department of Electrical and Computer Engineering.
10 King's College Road,
Toronto, Ontario 
Canada M5S 1A4

email: jayar@eecg.toronto.edu, 
phone: (416) 978-6992, 
fax:   (416) 971-2286

General Chair: Pak Chan, UC Santa Cruz
Program Chair: Jonathan Rose, University of Toronto.

Program Committee:

Duncan Buell, SRC
Pak Chan, UCSC
Jason Cong, UCLA
Ewald Detjens, Exemplar
Carl Ebeling, U. Washington
Frederic Furtek, Atmel
Dwight Hill, Synopsys
Sinan Kaptanoglu, Actel
John McCollum, Actel
Jonathan Rose, U. Toronto
Richard Rudell, Synopsys
Rob Rutenbar, CMU
Takayasu Sakurai, Toshiba
Martine Schlag, UCSC
Tim Southgate, Altera
Steve Trimberger, Xilinx


Article: 176
Subject: Re: Xilinx and 8.4 -- not!
From: jff@mrc-gwy.uidaho.edu (Jim Frenzel)
Date: 9 Sep 1994 14:45:24 GMT
Links: << >>  << T >>  << A >>
Brett Stutz (bretts@fred.xilinx.com) wrote:

> In article <347qlh$mgn@owl.csrv.uidaho.edu>, jff@mrc-gwy.uidaho.edu (Jim
> Frenzel) writes:
> |> Those of you using Xilinx XACT 5.0 with the Mentor interface
> |> might want to think twice about upgrading to 8.4 (A-1.F).
> |> 
> |> It appears that Mentor changed the shared libraries distributed
> |> with this version and now the Xilinx tool, gen_sch8, which produces
> |> backannotated schematics does not work.  Xilinx has verified this
> |> but it is not clear when a workaround will be available.
> |> 
> |> If 8.4 is important to you, you might want to give Xilinx
> |> a nudge ...  :-)

> And as a former Mentor employee, I suggest that you give Mentor a nudge
> as well.

I would be glad to, but I'm not sure what they could do to fix
the problem, short of going back to the old libraries.

Just to finish this thread (which doesn't seem to have generated
much traffic --- does that mean Xilinx users aren't using Mentor or
vice versa? :-) ), the word I got back from Xilinx is that, for now,
they are not going to support MGC 8.4.  In later releases of XACT
they will try and eliminate/reduce their dependence on the Mentor
libraries but for now I'm on my own ...

--

  Jim Frenzel, Asst. Prof   Electrical Engineering, BEL 213
  208-885-7532              University of Idaho         
  jfrenzel@uidaho.edu       Moscow, ID 83844-1023 USA


Article: 177
Subject: Re: I Cube FPIDs
From: kentd@netcom.com (Kent Dahlgren)
Date: Fri, 9 Sep 1994 20:37:56 GMT
Links: << >>  << T >>  << A >>
Andrew Shelley (A.Shelley@Sheffield.ac.uk) wrote:
: Does anyone have the postal address of I-Cube. If you have can you e-mail it to me.
: Thanks.
: Andy


Andrew you can contact us through any one of the following:

_______________________________________________________________________

I-Cube Inc.				Phone: (408) 986-1077
2328-C Walsh Avenue			FAX:   (408) 986-1629
Santa Clara, CA 95051			Email: marketing@icube.com
_______________________________________________________________________


Article: 178
Subject: Lattice ISP software: really bad or just different?
From: Eric@wolf359.exile.org (Eric Edwards)
Date: Sat, 10 Sep 1994 07:37:08 GMT
Links: << >>  << T >>  << A >>
I saw much moaning a couple of weeks ago about the conventions used in
Lattice ISP software.  Unfortunately I didn't save them. 

Can someone tell me what the real problem is?  Is the Lattice software
really cumbersome or is it annoying becuase works differently and uses
different conventions than more standard PLD software?

Lattice's "Starter Kit" looks like a very effective way to get started
with PLD's.  If the software is really bad I may look elsewhere but if it
is just "different" then there really isn't a problem.  I have no old
habits to unlearn.

----
Eric Edwards: Bang= cg57.esnet.com!wolf359!eric Domain= eric@exile.org
Remember the home hobbyist computer: Born 1975, died April 29, 1994



Article: 179
Subject: CPU Research POSTDOC Position
From: eugen@research.nj.nec.com@research.nj.nec.com (Eugen Schenfeld)
Date: 12 Sep 1994 12:57:04 -0400
Links: << >>  << T >>  << A >>

SCIENTIST POSITIONS AVAILABLE
=============================

NEC Research Institute of Princeton, NJ has one immediate opening for a term 
(tmp) Scientist position in the areas of: 

    VLSI CHIP DESIGN of a CPU with EMBEDDED COMMUNICATION.

The initial term of these positions is for one year. Subject to 
performance and availability of funds, it may be possible to extend this 
position for a longer period. 

Candidates for this  position should be familiar with and have PROVEN 
EXPERIENCE in one or more of the following topics: 

-Hardware prototyping (e.g., Xilinx and Aptix), 
-High level VLSI CAD/CAE design tools (e.g., Cadence/Verilog; Synopsys), 
-CPU architectures for parallel processing. 

The candidates should have a recent research activity in the above topics
and also have lab. working experience with instrumentation and measurement 
equipment. A Ph.D. thesis in the involving the design and implementation
of a "CPU Chip" (or being part of such a group) is a big advantage.
A Ph.D. in CS, EE, or CE is required for this position (candidates that
are close to finish their thesis will also be considered).


Successful candidates will participate in an ongoing research project. 
It is anticipated that the candidates would integrate their contributions
and be interested in the goal and scope of the current activity, leading
to new Massively Parallel Processing (MPP) paradigms and systems.

Interested applicants should send their resumes by mail, fax or email to:

	Dr. Eugen Schenfeld
	NEC Research Institute
	4 Independence Way
	Princeton, NJ 08540
        email: eugen@research.nj.nec.com
        phone: (609)951-2742
	fax:   (609)951-2482

The NEC Research Institute, founded in 1988, conducts long-term basic
research in the sciences underlining future technologies of computers
and communications (C&C). The goal of the Institute is to make
fundamental contributions to the computing and physical sciences basic
to the processing and interpretation of information. The Institute's
parent company is NEC Corporation, a global leader in computers,
communications, electronics and information services. On May 2, 1990,
the NEC Research Institute dedicated its $30 million new facilities on 
a twenty-one acre site in the Princeton area. This region was selected 
because of its tradition of basic research and invention. 
The Institute supports the belief that research results should be
available in the open literature and therefore emulates the liberal
publication policies of universities. Scientists at the NEC Research
Institute seek to expand the base of scientific knowledge and enhance
mutual understanding among the people of all nations.

NEC Research Institute is an equal opportunity employer.
Applicants must show documentation of eligibility for employment in the USA. 


============================================================================




Article: 180
Subject: Re: Xilinx and 8.4 -- not!
From: biggs@mothra.msd.lmsc.lockheed.com (Tom Biggs)
Date: Tue, 13 Sep 1994 23:36:56 GMT
Links: << >>  << T >>  << A >>
In article 552@owl.csrv.uidaho.edu, jff@mrc-gwy.uidaho.edu (Jim Frenzel) writes:
>Brett Stutz (bretts@fred.xilinx.com) wrote:
>
>> |> It appears that Mentor changed the shared libraries distributed
>> |> with this version and now the Xilinx tool, gen_sch8, which produces
>> |> backannotated schematics does not work.  Xilinx has verified this
>> |> but it is not clear when a workaround will be available.
>> |> 
>Just to finish this thread (which doesn't seem to have generated
>much traffic --- does that mean Xilinx users aren't using Mentor or
>vice versa? :-) ), the word I got back from Xilinx is that, for now,
>they are not going to support MGC 8.4.  In later releases of XACT
>they will try and eliminate/reduce their dependence on the Mentor
>libraries but for now I'm on my own ...

Perhaps this hasn't generated much traffic because many users don't need to use
gen_sch8 when doing back annotation. If I understand it correctly, gen_sch8 is
only used when a Mentor schematic is generated from the Xact netlist. If a Mentor
schematic was used to create the Xact netlist, then gen_sch8 need never be called
when doing a back annotation.

Also, many of us haven't gone to 8.4 yet, and haven't seen this problem.

By the way, there is nothing faster than running Xilinx tools on an HP750!
I would never attempt to do hand-routing of a XC4013 part on anything slower.

    -tom
        biggs@mothra.msd.lmsc.lockheed.com

            These opinions are my own...[insert various other legal disclaimers here].


Article: 181
Subject: Need General Ptr's on FPGA's
From: fic@shell.portal.com (Future Intergrated Chips)
Date: 14 Sep 1994 02:27:02 GMT
Links: << >>  << T >>  << A >>
Can anybody advise me based on your experience about the appropriate
FPGA to use for my application?

REQUIREMENT:

Design is in VHDL (mostly combinatorial).  
Approximate Gate count = 10K
Max operating speed = 50MHz.
Single Clock synchronous system.

Plan to use SYNOPSYS for synthesis.  

Thanks in advance.

Johnson.     



Article: 182
Subject: Re: Xilinx and 8.4 -- not!
From: greenlaw@war.ece.uiuc.edu (Jonathan Greenlaw)
Date: 14 Sep 1994 15:16:29 GMT
Links: << >>  << T >>  << A >>
8.4?  I still have problems with 8.2_5.  Most of the problems are more annoying
than anything else.  They all seem to center around the way pads are handled
in Design Architect.  The problem is in the way Xilinx translates the edif to
XNF.  It seems to drop several properties in the submodules (pin assignments
,etc).  We have also noticed problems with embedding ground busses in submodules
Like I said, there are workarounds, but they are ugly.  I wish Xilinx would
fix the netlisters first.  BTW. I have prodded Xilinx about this and their
response was that it would not probably be fixed for quite some time.

On the plus side, XACT 5.0 is the first release that we were able to do timing
simulation without having to sacrifice any poultry.  RPMs are great.

The problem (and it is not just Xilinx) is that the front end vendors (Mentor
Viewlogic, etc) no longer march in lock step with the FPGA vendors.  I do not
envy anyoune this task.

JG

--
Jonathan Greenlaw - F.O.H. (Friend of Holmes)
ECE Academic Systems Support - University of Illinois
1406 W. Green Urbana, IL 61801 (217) 244-8032


Article: 183
Subject: Re: Xilinx and 8.4 -- not!
From: joes@VFL.Paramax.COM (Joe Schulingkamp)
Date: Wed, 14 Sep 1994 17:46:35 GMT
Links: << >>  << T >>  << A >>
In article <Cw3DLK.z6@butch.lmsc.lockheed.com> biggs@mothra.msd.lmsc.lockheed.com writes:
>In article 552@owl.csrv.uidaho.edu, jff@mrc-gwy.uidaho.edu (Jim Frenzel) writes:
>>Brett Stutz (bretts@fred.xilinx.com) wrote:
>>
>>> |> It appears that Mentor changed the shared libraries distributed
>>> |> with this version and now the Xilinx tool, gen_sch8, which produces
>>> |> backannotated schematics does not work.  Xilinx has verified this
>>> |> but it is not clear when a workaround will be available.
>>> |> 
>>Just to finish this thread (which doesn't seem to have generated
>>much traffic --- does that mean Xilinx users aren't using Mentor or
>>vice versa? :-) ), the word I got back from Xilinx is that, for now,
>>they are not going to support MGC 8.4.  In later releases of XACT
>>they will try and eliminate/reduce their dependence on the Mentor
>>libraries but for now I'm on my own ...


Gee, I've heard that song before . . .


>
>Perhaps this hasn't generated much traffic because many users don't need to use
>gen_sch8 when doing back annotation. If I understand it correctly, gen_sch8 is
>only used when a Mentor schematic is generated from the Xact netlist. If a Mentor
>schematic was used to create the Xact netlist, then gen_sch8 need never be called
>when doing a back annotation.
>

If you want to simulate a design with Mentor, and you've used XBLOX components,
you need to use gen_sch8, I believe.


>Also, many of us haven't gone to 8.4 yet, and haven't seen this problem.

This is true  . . . I screamed in anticipation of trouble based on my problems
with 7.x and pre-XACT 5.0.


I went to a Xilinx seminar a little while ago, the main thrust of which was
marketing and sales (surprised).  What I got out of the talk was that 
although Xilinx is re-investing $$ in software and support, it's still
not a great percentage of income.  OK fine - then I guess reducing the
price of the development system wouldn't hurt that much, would it?

Mentor's trouble is that when the make a new release, they don't just fix
bugs, they add functionality, which creates a new set of problems.
-- 
Joe Schulingkamp,
joes@vfl.paramax.com
Unisys
Valley Forge Engineering Center


Article: 184
Subject: XACT 5.0 and XSI
From: schott@super.org (Brian Schott)
Date: Thu, 15 Sep 1994 15:17:51 GMT
Links: << >>  << T >>  << A >>
I just installed XACT 5.0 (FPGA core and XBLOX) from scratch with XSI
3.01b (Xilinx-Synopsys-Interface) in the SAME directory on a sparc.
It appears that the installation *must* be done in the following
order:

        1) install XBLOX from XACT-5.0 cd.
        2) install XSI from tape.
        3) install FPGA core tools from cd.
        4) install XSI update 3.01b floppy update.

The documentation says to install XSI first, but the XSI install
script tells you to install XBLOX first.

I was wondering if anyone is using this combination of XSI and XACT
5.0 with Synopsys 3.1b, and if there are any other pit-falls to watch
out for.  Or, if others have had more luck with XSI and XACT in
DIFFERENT directories.

Regards,
Brian

\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\//////////////////////////////////////
// Brian Schott                     \/ email: schott@super.org           \\
\\ Supercomputing Research Center   \/ phone: (301) 805-7322             //
// 17100 Science Drive              /\ quote: WAIT UNTIL clock'event;    \\
\\ Bowie, Maryland  20715           /\        clock <= snooze;           //
/////////////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\




Article: 185
Subject: Looking for Altera's FTP site
From: altatech@xmission.com (Alta Technology)
Date: 15 Sep 1994 12:25:54 -0600
Links: << >>  << T >>  << A >>
Does Altera have an FTP site and what is their address?

Thanks,

Frank


Article: 186
Subject: Altera/Intel nfXboard
From: devb@char.vnet.net (David Van den Bout)
Date: 15 Sep 1994 15:27:54 -0400
Links: << >>  << T >>  << A >>
For those who have been requesting information, the PostScript file
for the nfXboard manual is now in the pub/xess directory at ftp.vnet.net.
This will describe more fully the capabilities of the board.  It also 
includes a schematic.  A picture of the board can be found in mancvr2.prn.gz.
In addition, I've broken all the PLDasm design files out of the tar file
and placed them in a "designs" subdirectory so people can pick and choose
what they want.  New information on ordering and new distributors is in
the file OrdForm.txt.

As to the availability of PLDShell after Altera takes control of the
FLEXLogic product line on October 1, XESS Corp. will distribute PLDShell
from ftp.vnet.net at least until Altera initiates its own ftp site service.
This will prevent a break in the availability of the software as Altera
ramps up on the product.

-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 187
Subject: Re: Lattice ISP software: really bad or just different?
From: schneider@hwcae.Honeywell.COM (Tim Schneider)
Date: 15 Sep 94 18:06:18
Links: << >>  << T >>  << A >>

Here are the details from one of the engineers at our facility who
attempted to use the Lattice design kit... This is what I referred to
in my original post.


From: "Paul McGaugh" <mcgaugh@eng.iac.honeywell.com>
To: schneider
Date: Thu, 15 Sep 1994 18:39:20 -0600
Subject: Re: Forwarded mail [Lattice ISP software:  really bad or just different?]


> Can someone tell me what the real problem is?  Is the Lattice software
> really cumbersome or is it annoying becuase works differently and uses
> different conventions than more standard PLD software?
>
> Lattice's "Starter Kit" looks like a very effective way to get started
> with PLD's.  If the software is really bad I may look elsewhere but if it
> is just "different" then there really isn't a problem.  I have no old
> habits to unlearn.


The Lattice software IS really bad compared with most other packages. (All
other packages as far as I know.)  Here's the deal.

---background---
Each device has its own architecture of "macrocells", internal switch matrices,
output switch matrices, clock routing resources, global reset resources, buried
type macrocells etc. No "macrocell" is the same, I might add, between any two
vendors.  This is one of their key selling points (Ours is better than theirs
etc.)  I don't know any designer that wishes to become intimately familiar with
every PLD he ever uses.  In fact, most designers would like to learn as little
as possible about the "internals" of each PLD as long as their design can _FIT_
into the device and work.  (It would be a full time job just keeping up with
the differences.)

---now---
Most software packages allow the designer to write a set of equations (some
sort of HDL type language) in one file and then target some device into which
that they think the equations should _FIT_. The software then takes the
equations and partitions them into the various "macrocells", routing resources,
global resources etc.  The designer does't have to know (and likely doesn't
care) how each signal is routed between each "macrocell".  Here's where the
Lattice software becomes extremely tedious.  It expects the designer to write
seperate equation sets for each of the macrocells (like on the order of 32 or
64 or 128 macrocells).  Essentially, the designer has to partition his design
into tiny bits that will fit into the macrocell.  If the design changes at all,
the designer will have to do the partitioning all over again... this is no
small task, even for the small CPLDS.  So, unless your budget is paramount and
time is unlimited the Lattice software leaves much to be desired.

(The point of most software packages is to partition the design.  With Lattice
 software, YOU are the partitioner, that's the problem, wish it were as
 easy as utilizing the AMD mach devices in our PLDSII Minc/Mentor environment.)

  Paul

*****Paul McGaugh   phn:789-5256  m/s:AZ15 2N1; mcgaugh@eng.iac.honeywell.com*****

--
  \                      tim schneider
 o/\_            schneider@eng.iac.honeywell.com
<\__,\              602.863.5656  Phoenix, AZ
 ">   |
  `   |         Sometimes you're the windshield...
       \            Somtimes you're the bug.  
        \










Article: 188
Subject: Re: GigaOps video-compute-engine
From: chaseb@netcom.com (Bryan Chase)
Date: Fri, 16 Sep 1994 05:50:18 GMT
Links: << >>  << T >>  << A >>
Eric Pearson (ecp@focus-systems.on.ca) wrote:

: I saw mention of GigaOps just-introduced video-compute-engine
: development platform in an EE Times article.

: Does anyone have knowledge about this product that they are willing to
: share. Questions that come to mind are:

: 	- Which FPGA are they based upon? SRAM/VRAM?
: 	- How does the system scale upwards for larger problem
: 	- What tools/libraries are used
: 	- In what form is image data put in and taken out?
: 	- Is this a proprietary hardware system?

GigaOps presented their technology at a recent meeting of the Parallel
Processing Connection and I can tell you a little about what I heard
about there.  They do have data sheets which they will give you, I
have some around here somewhere... 

My disclaimer:  I do not officially speak nor work for GigaOps. I
believe a useable email address for them is bovarga@gigaops.com.

My Quick answers to the above questions:

1) They use Xilinx FPGAs.

2) I don't know how the system scales, but they allow for many 'daughter'
   boards off of a main board that plugs into a PC.

3) They use the Xilinx FPGA compiler S/W and the Analog Devices 2101 compiler.

4) I don't know anything about their image data format.

5) The hardware system is definitely their own design, I think they'll work
   with you as far as how their system works.

Their products as far as I know consist of a board with an Analog Devices
2101 processor (a DSP) and a Xilinx 4010 (an SRAM based FPGA) and 4 Megs
of memory. I think they put two of each (2 x 2101 plus 2 x 4010) plus the
memory on a card the size of a credit card, about 1/4 inch thick. The DSP
takes care of floating point calculations, while the Xilinx takes the
integer calculations and DMA type functions in order to route data. They
are also working on a C-language to Xilinx compiler, which they have
working to a certain degree in the lab, but it's not ready for shipment.
This 'daughter' boards plug into a larger board that plugs into a PC.
You can download configuration files for the Xilinx parts and code for
the 2101 from the PC and run whatever algorithms you want.

You have to compile for the Xilinx and the 2101 separately, so you have to
have a good idea of how to partition your function up.  Their product is
meant for video applications, but I'm not sure what anyone is
actually using it for.

-Bryan Chase


Article: 189
Subject: Re: Need General Ptr's on FPGA's
From: chaseb@netcom.com (Bryan Chase)
Date: Fri, 16 Sep 1994 06:18:25 GMT
Links: << >>  << T >>  << A >>
Future Intergrated Chips (fic@shell.portal.com) wrote:
: Can anybody advise me based on your experience about the appropriate
: FPGA to use for my application?

: REQUIREMENT:

: Design is in VHDL (mostly combinatorial).  
: Approximate Gate count = 10K
: Max operating speed = 50MHz.
: Single Clock synchronous system.

: Plan to use SYNOPSYS for synthesis.  

I'm just about to complete two designs that come close to your description.
One (actually two chips) is a Xilinx XC4006 design (their estimate = 6000
gates per chip). The other is an Altera FLEX81188 design (their estimate
= 12000 gates per chip).  Xilinx makes FPGAs that hold up to 13000 gates,
but I think you need a SparcStation class machine to compile it.  The
PC version chokes on large designs.  Altera is just about to or has already
released their 15000 gate FPGA.  Both companies will be producing bigger
and bigger ones as time goes on.  I think SYNOPSYS will work with both.
I know Altera has a VHDL input compiler in their most recent S/W release
(version 5.0).  I think Xilinx still depends on third parties.

I also have experience with Altera's EPLD line, which I would recommend
over an FPGA due to your Single Clock Synchronous System requirement.  The
only problem there is that you'll only get about 5000 gates in the
largest EPLD.  Must it be a one chip solution?  Heck, I'd probably trough
about 18000 gates at your 10K requirement anyway, since FPGAs will route 
easily to only 70%.  You'll then want to have a little overhead for bug fixes,
new requirements and such.

Your decision probably depends mostly on how much money you want to spend
on development tools, how many tools you already have and how willing you
are to design in a different programming environment.  For example, Xilinx
works best (I think) with View-Logic as the front end, but all front-ends
have their idosyncracies.  Altera has a complete S/W solution which I've
found to be very good.

There are other logic companies around too, such as Quicklogic (cheap S/W), 
Lattice, AT&T,  Atmel (rad-hard), and probably 10 others, were I to think
a little harder.  Most will satisfy your requirements.

-bryan chase
chaseb@netcom.com


Article: 190
Subject: Re: Looking for Altera's FTP site
From: kerry@altera.com Kerry Veenstra <72712.1243@CompuServe.COM>
Date: 16 Sep 1994 06:46:44 GMT
Links: << >>  << T >>  << A >>
Altera is now working toward providing its ftp site.  Until it is in
place, you can take advantage of the BBS, e-mail, and the XESS Corp.
ftp site mentioned in an earlier message.  For more information, send
e-mail to frankm@altera.com
 
Kerry Veenstra
kerry@altera.com


Article: 191
Subject: Address of VIRTUAL COMPUTERS Inc ???
From: kugel@mp-sun8.informatik.uni-mannheim.de (Andreas Kugel)
Date: 16 Sep 1994 07:15:38 GMT
Links: << >>  << T >>  << A >>
I found some references to a large FPGA/FDIP based machine (maybe prototype)
from a company named similar to VIRTUAL COMPUTERS Inc.

I would like to get in contact with them, cause we`re dealing also with FPGA
based computer.

Is their addresse somewhere out in the net?

Thanks
Andreas





Article: 192
Subject: Re: Address of VIRTUAL COMPUTERS Inc ???
From: jdp@elis.rug.ac.be (Jo Depreitere)
Date: 16 Sep 1994 08:40:53 GMT
Links: << >>  << T >>  << A >>
Andreas Kugel (kugel@mp-sun8.informatik.uni-mannheim.de) wrote:
: I found some references to a large FPGA/FDIP based machine (maybe prototype)
: from a company named similar to VIRTUAL COMPUTERS Inc.

: I would like to get in contact with them, cause we`re dealing also with FPGA
: based computer.

: Is their addresse somewhere out in the net?

: Thanks
: Andreas


For more information contact:

             Virtual Computer Corporation
       6925 Canby Ave #103    Reseda, CA 91335
              tel: (818) 342-8294
              fax: (818) 342-0240
             e-mail: info@vcc.com

--
Kind regards,

Jo Depreitere
Researcher UG-ELIS

====================================================================
e-mail : jdp@elis.rug.ac.be
URL    : http://www.elis.rug.ac.be
Phone  : ++32+9/264 34 09
Fax    : ++32+9/264 35 94

Address: University of Ghent
         Electronics and Information Systems Dpt.
         Sint-Pietersnieuwstraat 41
         B-9000 Ghent
         Belgium
====================================================================


Article: 193
Subject: Re: Lattice ISP software: really bad or just different?
From: Cho Moon -- Lattice Semiconductor <lattice@rahul.net>
Date: Fri, 16 Sep 1994 21:02:45 GMT
Links: << >>  << T >>  << A >>
In article <SCHNEIDER.94Sep15180618@ms13.hwcae.az.Honeywell.COM>,
Tim Schneider <schneider@eng.iac.honeywell.com> wrote:
>
>Here are the details from one of the engineers at our facility who
>attempted to use the Lattice design kit... This is what I referred to
>in my original post.
>
>The Lattice software IS really bad compared with most other packages. (All
>other packages as far as I know.)  Here's the deal.
...
>(The point of most software packages is to partition the design.  With Lattice
> software, YOU are the partitioner, that's the problem, wish it were as
> easy as utilizing the AMD mach devices in our PLDSII Minc/Mentor environment.)
>
>  Paul
>
>*****Paul McGaugh   phn:789-5256  m/s:AZ15 2N1; mcgaugh@eng.iac.honeywell.com*****

I just would like to make two points:

1.  There are two Lattice starter kits in the market: pDS and pDS+/ABEL.
The pDS starter kit does not support automatic partitioning (believe me, 
there are still designers out there who want to do everything manually).  
Our pDS+/ABEL kit does suport automatic partitioning, and we have been
receiving very positive feedback from customers on this kit.  If you are using 
DATA I/O already, pDS+/ABEL should be very easy to use.  For more information 
on pDS+/ABEL, you may call 1-800-LATTICE.

2.  The name of our software is pDS not ISP.  ISP stands for "in-sytem 
programmability", a feature which lets you implement multiple hardware
configurations with the same board design.  I would be interested in hearing 
about the use of ISP capabilities in reconfigurable computers.

All the best,

Cho Moon

| Cho W. Moon                                                                |
| Lattice Semiconductor,  1820 McCarthy Blvd., Milpitas, CA 95035-7425       |
| (408) 428-6400x250 (voice) (408) 944-8444 (fax) cmoon@lattice.com (e-mail) |

-- 
Cho Moon -- Lattice Semiconductor <lattice@rahul.net>


Article: 194
Subject: Partly reconfigurable FPGAs
From: telkamp@eis.cs.tu-bs.de (Gerrit Telkamp)
Date: 17 Sep 1994 16:49:40 GMT
Links: << >>  << T >>  << A >>
Two or three weeks ago someone looked for partly reconfigurable FPGAs
(unfortunately I can't remember that posting exactly)

I found FPGAs in the new ATMEL programmable logic data book, which can be
partly reconfigurated (AT 6000 series). Capacity : 2.000 - 10.000 gates.

Gerrit
-----------------------
telkamp@eis.cs.tu-bs.de


Article: 195
Subject: Re: Lattice ISP software: really bad or just different?
From: skrodzki@t500m0.telematik.informatik.uni-karlsruhe.de (Skrodzki Stefan)
Date: 18 Sep 1994 16:21:39 GMT
Links: << >>  << T >>  << A >>
> There are two Lattice starter kits in the market: pDS and pDS+/ABEL.

I wouldn't call a starter kit "starter kit" when it costs more than 1000DM her
in Germany. So for me there is only one starter kit: the pds-soft.

For me a starter kit should show the whole possibilities of a development system maybe with restrictions in the choice of devices. But my experiences with
the pds starter kit makes it really difficult for me to buy the pds+ soft...

> (believe me,
> there are still designers out there who want to do everything manually).

There are still designers out there who want to have first _results_ and
then perhaps improve them manually.

The bad thing is that the isp chips are IMHO a very good choice in price and 
functionality but _not_ with that gruel software.

So, come on You people at Lattice. Take a look at other low-cost design tools
(look at ftp.intel.com :-) an change the pds from a funny double-clicking-
memmory-munging windows programm to a powerful development tool. Many people
would thank you for this with buying the ips chips!

I think one of the reasons why intel flexlogic becomes more and more respect
the recent time is their development tool!

Bye 
 Steve


Article: 196
Subject: Postings sent as mail ???--------------
From: leeja@netcom.com (Leeja)
Date: Mon, 19 Sep 1994 02:54:55 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm just wondering if its at all possible to have all the postings of 
comp.arch.fpga to be sent as email to someone.

I'm asking because someone I know wants access to the threads of this
newsgroup but does not have internet/usenet access. His email account
is set up in a company that has a netcom uucp link. So is it possible to
ask the netcom admin to just mail the postings to a dummy user at his 
company? Also, how would one go about posting to the group if this method
were possible?


Thanks in advance.

leeja@netcom.com



Article: 197
Subject: Re: Lattice ISP software: really good
From: trev@ss11.wg.icl.co.uk (Trevor Hall)
Date: Mon, 19 Sep 1994 06:01:23 GMT
Links: << >>  << T >>  << A >>
In article <SCHNEIDER.94Sep15180618@ms13.hwcae.az.Honeywell.COM>,
Tim Schneider <schneider@eng.iac.honeywell.com> wrote:
>
>Here are the details from one of the engineers at our facility who
>attempted to use the Lattice design kit... This is what I referred to
>in my original post.
>
>The Lattice software IS really bad compared with most other packages. (All
>other packages as far as I know.)  Here's the deal.
...
>(The point of most software packages is to partition the design.  With Lattice
> software, YOU are the partitioner, that's the problem, wish it were as

Not true, auto partitioning is included with PDS+


> easy as utilizing the AMD mach devices in our PLDSII Minc/Mentor environment.)

I am currently using ispLSI3256 devices (approx 80% pin and GLB utilazation).
My experience so far has shown the Lattice parts to be far superior to AMD mach, where
fitting and then re-fitting with the pins fixed is concerned. I have used both MINC and
PALASM to fit AMD parts and quite honestly it was an unpleasant experience.

I am using MINC as a front end, with a MINC to ABEL pla bridge to the Lattice fitter.
This bridge was co-developed by ourseleves and Lattice UK (who did most of the work I may add). As this bridge is still under development I doubt that it will be freely
available yet.

As for the grumblings I have seen here about the cost of PDS+, well it cost us the 
grand sum of 600 uk pounds. That is a lot less than the approx. 2K pounds MINC will
charge for a their own Lattice fitter (if and when they get round to doing it).

As an aside, Lattice have also written a bridge into the Teradyne LASAR simulator for
us. This allows us to perform worst case PCB level simulation.

If you wish to contact Lattice about the MINC2ABL bridge I suggest you contact 
James Foster, Lattice UK --- engoff@attmail.com



Trevor Hall
Goldrush Project
ICL




Article: 198
Subject: Re: Partly reconfigurable FPGAs
From: wao@antares (W. Oswald)
Date: Mon, 19 Sep 1994 15:44:05 GMT
Links: << >>  << T >>  << A >>
Gerrit Telkamp (telkamp@eis.cs.tu-bs.de) wrote:
: Two or three weeks ago someone looked for partly reconfigurable FPGAs
: (unfortunately I can't remember that posting exactly)

: I found FPGAs in the new ATMEL programmable logic data book, which can be
: partly reconfigurated (AT 6000 series). Capacity : 2.000 - 10.000 gates.

: Gerrit
: -----------------------
: telkamp@eis.cs.tu-bs.de

All of the AT&T ORCA(tm) series fpga's can be partially or completely
reconfigured on the fly. Capacity : 3,000 - 26,000 gates

--
My views are my own!
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
_/_/ Bill                                       _/_/
_/_/    __      _  _  __                  _     _/_/
_/_/   /  )    // // / ')                //   / _/_/
_/_/  /--<  o // // /  / _   , , , __.  // __/  _/_/
_/_/ /___/_<_</_</ (__/ /_)_(_(_/_(_/|_</_(_/_  _/_/
_/_/                                            _/_/
_/_/ w.a.oswald@att.com                         _/_/
_/_/ billatt@aol.com                            _/_/
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/


Article: 199
Subject: PLD for async state machine?
From: tompkins@appliedmicro.ns.ca (Jim Tompkins)
Date: 19 Sep 1994 16:08:44 -0300
Links: << >>  << T >>  << A >>
Hi,

   I'm trying to implement an asynchronous state machine in
a PLD.  Anyone know of a good device for doing so?  I need
a small number of flip-flops with true asynchronous sets
and resets.

   Any suggestions greatly appreciated.

Cheers,
--
Jim Tompkins                Internet : tompkins@appliedmicro.ns.ca   
Applied Microelectronics Institute      Voice    : (902) 421-1250   
1046 Barrington Street                  Fax      : (902) 429-9983  
Halifax, NS  CANADA B3H 2R1                                       




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