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Messages from 1000

Article: 1000
Subject: Re: Neocad merges with Xilinx
From: derekp@ix.netcom.com (Derek Palmer)
Date: 11 Apr 1995 19:00:07 GMT
Links: << >>  << T >>  << A >>
In <3lrhue$sf6@newsbf02.news.aol.com> thomrscott@aol.com (ThomRScott) 
writes: 

>
>Okay folks I guess someone should address this. I am now a 
Manufacturer's
>Rep representing AT&T Microelectronics in Oregon. I used to be an FAE
>representing one of Neocad's resellers, and I know and respect highly 
many
>of the people at Neocad. Before that I was a digital designer for 12
>years.
>
>This is not an April Fool's Joke. Xilinx HAS indeed purchased Neocad.
>While I cannot speak for the other FPGA vendors who had been aligned 
with
>Neocad; and while my statements are not necessarily AT&T party line, 
allow
>me to take my official hat off and state some personal opinions:
>
>IMHO: Xilinx has finally admitted what I've been claiming for some 
time,
>that Neocad had developed by far the best FPGA place and route tools in
>the industry. After taking a hard line for years that they wouldn't 
work
>with Neocad (the bright folks at Neocad reverse engineered the support 
for
>Xilinx with no help from Xilinx, and have been cleaning Xact's clock
>almost from day one) Xilinx couldn't afford to be handicapped any 
longer.
>Xilinx has finally acknowledged that their architectures -- more than
>anyone else's -- desparately need the superb placement and routing of
>Neocad. I think this is not even a controversial statement. Have you 
heard
>how "good" the 4025 is?
>
>AT&T some time ago recognized how good Neocad's stuff was and entered 
into
>a series of agreements with Neocad that ultimately secured full source
>code ownership rights. AT&T has been developing this code with Neocad 
for
>some time now, and will be releasing updates on a regular schedule, 
with
>some very exciting enhancements to come. In terms of interfering with
>AT&T's support, Xilinx bought the barn after we'd already taken the 
horses
>home.
>
>Its too bad that the market will lose the vendor-independent tool that
>Neocad has been. Many of our customers first discovered how good ORCA 
was
>when using Neocad to run benchmarks. Neocad's vendor independence 
enabled
>them to compare their designs on other FPGA architectures with AT&T 
ORCA
>and as result discovered the strengths of the AT&T ORCA. I'm not aware 
of
>a benchmark that ORCA has lost. When you're in that position, 
comparisons
>are good!
>
>In summary, this is certainly a major change in our market, but AT&T 
users
>should have no fear that they will lose this great technology. AT&T has
>the foundries, the architectures, the tools, the people, and the market
>momentum to continue to be very succesful in the high-speed, medium to
>high-density, super routable, low-power FPGA market for some time to 
come.
>
>I hope this answers some questions. For more information contact your
>local rep.
>(Okay, maybe my hat did slip back on a little at the end there.  ;-)  )
>

I have been waiting for to happen for over a year.  It was very obvious 
early on that Neocad was routing better than Xilinx's own router.  I 
wondered how long Xilinx would let this go on.  
Competitively, I think it makes sense.  Get a better piece of software 
and take it away from your competitors at the same time. Nice move.  
With the PLD/FPGA devices passing the 10K gate range, software becomes 
critically important.  I've seen good programable architectures enter 
the market with less than adequate software and watched them flounder.  
I read an article that said AT&T had dissolved its software group after 
the Neocad agreement.  If this is true I can only guess at how AT&T will 
proceed.  Rebuild a S/W group and give them a piece of code they didn't 
write and ask them to maintain it. Good Luck!  What about new 
architectures in the future?  I think Motorola is in the same boat.
The unfortunate are those who are hoping for vendor independent tools.  
If I was a silicon vendor I would not want to bet my future success on 
someone elses software.  I would support anyone who wanted to provide 
software for my devices, but I would never discontinue my support 
internatlly?  
The architectures that are evolving in this market are changing to fast 
for a third party vendors to keep up.  Plus many of these tools (i.e 
synthesis) were optimized for ASICs. They don't always work well when 
targeting programmable logic. 
If you look at the two largest vendors in the programmable logic market 
( Altera and Xilinx), you'll notice they make their own software as well 
as support all the major third party vendors. I don't see this changing. 
It seems to work.
As always, my opinions are my own.
Derek


Article: 1001
Subject: Device XC7336 not in XACT device list
From: soldered@prometheus.hol.gr (Argirhs Diamanths)
Date: 11 Apr 1995 22:22:37 +0200
Links: << >>  << T >>  << A >>
Hello everybody,
I have purchased the XACT EPLD core tools (Version 4.0.1 if i am correct),
and i have found that the XC7336 device does not appear in the  list of
the eplds. It seems this Version of EPLD core tools does not have the
library of this device (although the databooks include it). Has anybody else
encountered the same problem? Does Xilinx have any update packages to
support this device? If yes can i ftp them from somewhere in the net (the
XC7336 libraries). I have the chip, the programmer, and i am missing the
compiler!

Thanks in advance
Alexopoulos Ilias


Article: 1002
Subject: I-Cube - contact information ?
From: Gavin Brebner <gavinb@shannon.tellabs.com>
Date: Wed, 12 Apr 1995 13:07:31 GMT
Links: << >>  << T >>  << A >>

Does anyone have contact information they can pass on
to me for I-Cube; email / fax / telephone or even snail
mail address all acceptable.


	Thanks,

	Gavin


Article: 1003
Subject: Re: AT&T Statement ref Neocad
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 12 Apr 1995 17:27:38 GMT
Links: << >>  << T >>  << A >>
In article 2v9@oasis.icl.co.uk, trev@ss11.wg.icl.co.uk (Trevor Hall) writes:
>1) MINC do not currently supply FPGA place and route tools, they do provide front-end
>synthesis for the likes of XILINX, ACTEL etc..

It seems that everyone is providing front end FPGA support but shying away from 
place and route.  Even Cadence, who is quite pround of the place & route algoritms.

>2) Word has it that AMD is stopping development of its own fitters, placing all future
>development in the hands of MINC. How this will effect PALASM users I don't know.

The opposite trends in CPLDs and FPGAs are interesting.  Conclusion - 

FPGA market is splintered and devices quite different. Makes support 
of a universal tool very tough.  

CPLDs are quite similar, second sources etc.  Users ask for great universal 
tools and get them, eventually obsoleting vendor specific tools.  Plus, 
silicon vendors have a hard time making money on tools, so why mess with it.


---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1004
Subject: Re: Neocad merges with Xilinx
From: kgold@watson.ibm.com (Ken Goldman)
Date: 12 Apr 1995 18:10:30 GMT
Links: << >>  << T >>  << A >>
derekp@ix.netcom.com (Derek Palmer) writes:
> [snip]
> If I was a silicon vendor I would not want to bet my future success on 
> someone elses software.  I would support anyone who wanted to provide 
> software for my devices, but I would never discontinue my support 
> internatlly?  
> The architectures that are evolving in this market are changing to fast 
> for a third party vendors to keep up.  Plus many of these tools (i.e 
> synthesis) were optimized for ASICs. They don't always work well when 
> targeting programmable logic. 
> If you look at the two largest vendors in the programmable logic market 
> ( Altera and Xilinx), you'll notice they make their own software as well 
> as support all the major third party vendors. I don't see this changing. 
> It seems to work.

I found it interesting that just as Xilinx took this approach, AMD
(certainly one of the largest PLD vendors) decided to abandon their
internal support for the MACH family and turn it over to MINC.

Can they both be right?


Article: 1005
Subject: Intel Flex Download Cable
From: morph@io.org (Ryan Raz)
Date: 12 Apr 1995 17:09:56 -0400
Links: << >>  << T >>  << A >>
Intel supplies software on their BBS for on-board programming
of their FX780 FLEX logic parts (now the Altera EPX780).
This software requires a down load cable which connects from
the PC parallel port to a 20 pin header on the target board.
I have the spec's for the 20 pin header.  I am looking for
spec's or schematics for the cable.

----------------------------------------------------------------- 
 Ryan S. Raz     
 Morphometrix, 120 Adelaide St. E., Unit 2, 
 Toronto, Ontario, Canada M5C 1K9
 Tel: (416)361-6239   Fax: (416)361-3162   Email: morph@io.org
-----------------------------------------------------------------


Article: 1006
Subject: Need "fusemap" information from vendor, likely?
From: pdgray@undergrad.math.uwaterloo.ca (Peter D. Gray)
Date: Wed, 12 Apr 1995 23:20:11 GMT
Links: << >>  << T >>  << A >>
I want to write my own programs to "route and place" for FPGAs. This is
for my own little project, not as another HDL compiler.  In
particular, I've been looking at the ALTERA Flex 8000 chips, but at
this stage I can still choose anything (must be SRAM based).

The question is this: Can I, as a nobody, get the required information
from the manufacturer so that I can generate the JDEC files/fusemaps
(whatever you want to call them) so that I can program these chips
without using their software? I would be willing to sign an NDA
(non-disclosure agreement) but not pay money.

For that matter, is it just a question of requesting the correct
application note from the company? Something like, "Application note
#9485, Memory map: Cell location to function mapping".

Thanks,
PG


Article: 1007
Subject: Re: Neocad merges with Xilinx
From: mstan@hades.ecs.umass.edu (Mircea R Stan)
Date: 13 Apr 1995 00:04:18 GMT
Links: << >>  << T >>  << A >>
In article <3mh52m$10p3@watnews1.watson.ibm.com> kgold@watson.ibm.com (Ken Goldman) writes:
>derekp@ix.netcom.com (Derek Palmer) writes:
>> [snip]
>> If I was a silicon vendor I would not want to bet my future success on 
>> someone elses software.  I would support anyone who wanted to provide 
>> software for my devices, but I would never discontinue my support 
>> internatlly?  
>> The architectures that are evolving in this market are changing to fast 
>> for a third party vendors to keep up.  Plus many of these tools (i.e 
>> synthesis) were optimized for ASICs. They don't always work well when 
>> targeting programmable logic. 
>> If you look at the two largest vendors in the programmable logic market 
>> ( Altera and Xilinx), you'll notice they make their own software as well 
>> as support all the major third party vendors. I don't see this changing. 
>> It seems to work.
>
>I found it interesting that just as Xilinx took this approach, AMD
>(certainly one of the largest PLD vendors) decided to abandon their
>internal support for the MACH family and turn it over to MINC.
>
>Can they both be right?

Yes, if AMD buys MINC next year :)


-- 
Mircea R. Stan		|	"Without immortality the whole world would 
UMass, ECE Dept.	|	be nonsense, all of creation an absurdity."
Amherst, MA 01003	|					Karl F. Gauss


Article: 1008
Subject: Re: Need "fusemap" information from vendor, likely?
From: mstan@hades.ecs.umass.edu (Mircea R Stan)
Date: 13 Apr 1995 02:11:23 GMT
Links: << >>  << T >>  << A >>
In article <D6y3Hn.GtJ@undergrad.math.uwaterloo.ca> pdgray@undergrad.math.uwaterloo.ca (Peter D. Gray) writes:
>I want to write my own programs to "route and place" for FPGAs. This is
>for my own little project, not as another HDL compiler.  In
>particular, I've been looking at the ALTERA Flex 8000 chips, but at
>this stage I can still choose anything (must be SRAM based).
>
>The question is this: Can I, as a nobody, get the required information
>from the manufacturer so that I can generate the JDEC files/fusemaps
>(whatever you want to call them) so that I can program these chips
>without using their software? I would be willing to sign an NDA
>(non-disclosure agreement) but not pay money.
>
>For that matter, is it just a question of requesting the correct
>application note from the company? Something like, "Application note
>#9485, Memory map: Cell location to function mapping".
>
>Thanks,
>PG
I don't think you have any chances of getting that information.
The reason is simple: security. Noone wants to have their designs
easily reverse engineered by someone looking at the bitstream.

Good Luck!
-- 
Mircea R. Stan		|	"Without immortality the whole world would 
UMass, ECE Dept.	|	be nonsense, all of creation an absurdity."
Amherst, MA 01003	|					Karl F. Gauss


Article: 1009
Subject: Re: Intel Flex Download Cable
From: devb@jazzmin.vnet.net (David Van den Bout)
Date: 12 Apr 1995 22:29:05 -0500
Links: << >>  << T >>  << A >>
In article <Pi3ZlOCGpFR5079yn@io.org>, Ryan Raz <morph@io.org> wrote:
>Intel supplies software on their BBS for on-board programming
>of their FX780 FLEX logic parts (now the Altera EPX780).
>This software requires a down load cable which connects from
>the PC parallel port to a 20 pin header on the target board.
>I have the spec's for the 20 pin header.  I am looking for
>spec's or schematics for the cable.
>

Ryan:

The cable is easy to build:

1. Connect a male DB-25 to a 26-pin socket.  Pin 26 of the socket
   remains unconnected.  The DB-25 goes to the parallel printer port
   while the 26-pin socket connects to a 13x2 header on the EPX780 board.
2. Connect pin 2 of the header through two 7414 inverters to the TCK
   pin of the EPX780.  The 7414 cleans up the clock signal.
3. Connect pin 3 to the TMS input pin of the EPX780.
4. Connect pin 8 to the TDI input pin of the EPX780.
5. Connect pin 11 to the TDO output pin of the EPX780.
6. Connect pins 9 and 12 of the header together so the downloading
   software can detect the presence of the cable.
7. Ground header pins 18 through 25.

That should do it.  If the PENGN software has trouble verifying the
download (using the -v option), then you may have to buffer the
TMS, TDI, and TDO outputs on the FPGA board or shorten the cable.



-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 1010
Subject: Re: Need "fusemap" information from vendor, likely?
From: bbutler@netcom.com (Bryan Butler)
Date: Thu, 13 Apr 1995 05:24:54 GMT
Links: << >>  << T >>  << A >>
Mircea R Stan (mstan@hades.ecs.umass.edu) wrote:
> In article <D6y3Hn.GtJ@undergrad.math.uwaterloo.ca> pdgray@undergrad.math.uwaterloo.ca (Peter D. Gray) writes:
> >I want to write my own programs to "route and place" for FPGAs. This is
> >for my own little project, not as another HDL compiler.  In
> >particular, I've been looking at the ALTERA Flex 8000 chips, but at
> >this stage I can still choose anything (must be SRAM based).
> >
> >The question is this: Can I, as a nobody, get the required information
> >from the manufacturer so that I can generate the JDEC files/fusemaps
> >(whatever you want to call them) so that I can program these chips
> >without using their software? I would be willing to sign an NDA
> >(non-disclosure agreement) but not pay money.
> >
> >For that matter, is it just a question of requesting the correct
> >application note from the company? Something like, "Application note
> >#9485, Memory map: Cell location to function mapping".
> >
> >Thanks,
> >PG
> I don't think you have any chances of getting that information.
> The reason is simple: security. Noone wants to have their designs
> easily reverse engineered by someone looking at the bitstream.

I agree this information is not easy to obtain. However, the reason is that
the manufacturers want you to buy their software. 

Most devices have security fuses to prevent reverse-engineering.

--
-------
Bryan Butler
bbutler@netcom.com


Article: 1011
Subject: Re: I-Cube - contact information ?
From: jdp@elis.rug.ac.be (Jo Depreitere)
Date: 13 Apr 1995 07:32:54 GMT
Links: << >>  << T >>  << A >>
Gavin Brebner (gavinb@shannon.tellabs.com) wrote:

: Does anyone have contact information they can pass on
: to me for I-Cube; email / fax / telephone or even snail
: mail address all acceptable.


: 	Thanks,

: 	Gavin



I-Cube Inc.				Phone: (408) 986-1077
2328-C Walsh Avenue			FAX:   (408) 986-1629
Santa Clara, CA 95051			Email: marketing@icube.com


--
Kind regards,

Jo Depreitere

====================================================================

-   Many dead animals of the past changed to fossils, others
    preferred to be oil.

====================================================================
e-mail : jdp@elis.rug.ac.be
URL    : http://www.elis.rug.ac.be
Phone  : ++32+9/264 34 09
Fax    : ++32+9/264 35 94

Address: University of Ghent
         Electronics and Information Systems Dept.
         Sint-Pietersnieuwstraat 41
         B-9000 Ghent
         Belgium
====================================================================


Article: 1012
Subject: Any way to go from routed LCA to logic description?
From: hamilton@appliedmicro.ns.ca (Neil Hamilton)
Date: 13 Apr 1995 14:29:14 -0300
Links: << >>  << T >>  << A >>
I am updating an old 2000 series Xilinx design and have design
sketches only. The design was hand stitched into the device.

I have only the routed LCA files and the sketches to work from.

Is there anyway to generate a crude logic diagram from what I have??

Any help would be much appriciated!!


-- 

---------------------------------------------------------------------
Neil Hamilton, PEng (EE)	phone (902)421-1250 fax (902)429-9983
Applied Microelectronics, Halifax, NS      hamilton@appliedmicro.ns.ca



Article: 1013
Subject: Re: Need "fusemap" information from vendor, likely?
From: schmitz@mach1.amd.com (Nick Schmitz)
Date: Thu, 13 Apr 1995 10:57:58 -0800
Links: << >>  << T >>  << A >>
In article <D6y3Hn.GtJ@undergrad.math.uwaterloo.ca>, 
pdgray@undergrad.math.uwaterloo.ca (Peter D. Gray) writes:
...
> Subject: Need "fusemap" information from vendor, likely? 
...
> 
> I want to write my own programs to "route and place" for FPGAs. This is 
> for my own little project, not as another HDL compiler.  In 
> particular, I've been looking at the ALTERA Flex 8000 chips, but at 
> this stage I can still choose anything (must be SRAM based). 
> 
> The question is this: Can I, as a nobody, get the required information 
> from the manufacturer so that I can generate the JDEC files/fusemaps (
> whatever you want to call them) so that I can program these chips 
> without using their software? I would be willing to sign an NDA 
> (non-disclosure agreement) but not pay money. 
> 
> For that matter, is it just a question of requesting the correct 
> application note from the company? Something like, "Application 
> note #9485, Memory map: Cell location to function mapping". 
> 
> Thanks, 
> PG 

A valid question, but..

Each CPLD/FPGA vendor has different rules, but the short answer is probably 
not. The task of reading the vendor's internal device specification, adapting 
existing place & route algorithms, implementing new ones, and TESTING the 
program is a daunting task. As an educational project or thesis topic, it 
could consume several manyears of effort.


We at AMD do have specifications for the Jedec file used in programming our 
devices & have made them available to other companies for either CAD 
software, device timing model or programmer development reasons (under NDA). 
But we usually narrow that list to those companies who have a track record of 
helping us & we can justify the internal support resources for their 
questions.


I clearly do NOT speek for Altera, but they have kept their device 
programming data propietary in a binary file. They have also not adopted the 
ascii-based Jedec file format used by most of the PLD industry. With the 
normal RAM based FPGA's reverse engineering a bit-stream is not that hard (it 
is time consuming), given you have the vendor's s/w, a device & some patience.


AMD does NOT currently make RAM based FPGA's. Our technology is 
reprogrammable using 5-v serial bit streams (JTAG access), but retains its 
configuration with power removed.

 
Nick Schmitz
Advanced Micro Devices
PLD Product Planning Manager.






Article: 1014
Subject: FCCM'95 Program
From: jma@descartes.super.org (Jeffrey M. Arnold)
Date: Thu, 13 Apr 1995 22:28:03 GMT
Links: << >>  << T >>  << A >>
Once again, here's the program from FCCM'95 next week.  For more late
breaking changes check:

	http://www.super.org:8000/FPGA/fccm95.html

-jeff



			   FCCM'95 Program

	IEEE Symposium on FPGAs for Custom Computing Machines

		       Marriott at Napa Valley
			       Napa, CA
			  April 19-21, 1995


			      Co-Chairs

Kenneth L. Pocek		Peter M. Athanas
Intel				Virginia Polytechnic Institute
Mail Stop RN6-18		Bradley Dept. of Electrical Eng.
2200 Mission College Blvd	340 Whittemore Hall
Santa Clara, CA 95052		Blacksburg, VA 24061-0111
(408)765-6705 voice		(703)231-7010 voice
(408)765-5165 fax		(703)231-3362 fax
kpocek@sc.intel.com		athanas@vt.edu



			 Organizing Committee

Jeffrey Arnold, IDA SRC			Fred Furtek, Atmel Corp.
Duncan Buell, IDA SRC			Brad Hutchings, Brigham Young Univ.
Pak Chan, UC Santa Cruz			Tom Kean, Xilinx (UK)
Apostolos Dollas, Tech. Univ. Crete	Wayne Luk, Imperial College (UK)




		        Tuesday April 18, 1995

Registration and reception beginning at 6pm.


		       Wednesday April 19, 1995


		Session 1: Custom Computing Platforms

A FCCM for Dataflow (Spreadsheet) Programs
A. Lew, R. Halverson
University of Hawaii at Manoa


MORPPH: A MOdular and Reprogrammable Real-time Processing
Hardware
T. Drayer, W. King, J. Tront, R. Conners
Virginia Tech


Architecture of a FPGA-based Coprocessor: The PAR-1
Javier Moran, Eduardo Juarez Martinez, Sadot Alexandres Fernandez, 
Juan Meneses Chaus
Technical University of Madrid



		Session 2: Custom Computing Platforms

Teramac - Configurable Custom Computing
R. Amerson, R. Carter, B. Culbertson, P. Kuekes, G. Snider
HP Labs


Common Processor Element Packaging
B. Box, J. Nieznanski
Lockheed Sanders


Enable++: A Second Generation FPGA Processor
H. Hogl, A. Kugel, J. Ludvig, R. Manner, K. Noffz, R. Zoz
University Mannheim (Germany)



				Lunch

		     Session 3: Signal Transport


Design and Implementation of a Multicomputer Interconnection Using
FPGAs
Chun-Chao Yeh, Chu-Hsing Wu, Jie-Yong Juang
National Taiwan University


Routability Improvement Using Dynamic Interconnect Architecture
J. Li, C.K. Cheng
UC San Diego


Reconfigurable Real-time Signal Transport System Using Custom FPGAs
K. Hayashi, T. Miyazaki, K. Shirakawa, K. Yamada, N. Ohta
NTT Optical Network Systems Laboratory



		 Session 4: Run-time Reconfiguration


Design Methodologies for Partially Reconfigured Systems
J. Hadley, B. Hutchings
Brigham Young University


Issues in Wireless Video Coding using Run-time Reconfiguration FPGAs
C. Jones, J. Oswald, B. Schoner, J. Villasenor
UCLA


Run Time Reconfiguration of FPGA for Scanning Genomic Databases
E. Lemoine, D. Merceron
University Montpellier II (France)


A Dynamic Instruction Set Computer
M. Wirthlin, B. Hutchings
Brigham Young University



		       Thursday April 20, 1995

		      Session 5: Applications 1


Emulating Static Faults Using a Xilinx Based Emulator
R. Wieler, Z. Zhang, R. McLeod
University of Manitoba


Acceleration of Template-Based Ray Casting for Volume Visulization
Using FPGAs
M. Dao, T. Cook, D. Silver
Rutgers University


Flexible Image Acquisition using Reconfigurable Hardware
Mark Shand
Digital Equipment Corp.



		      Session 6: Compiler Issues



The Transmogrifier C Hardware Description Language and Compiler for
FPGAs
David Galloway
University of Toronto


Architectural Descriptions for FPGA Circuits
Satnam Singh
University of Glasgow


Quantitative Analysis of Floating Point Arithmetic on FPGA-based
Custom Computing Machines
N. Shirazi, A. Walters, P. Athanas
Virginia Tech



				Lunch

		      Session 7: Compiler Issues


A Declarative Approach to Incremental Custom Computing
W. Luk
Imperial College of Science, Technology, and Medicine


A C++ compiler for FPGA custom execution units synthesis
C. Iseli, E. Sanchez
Laboratoire de Systemes Logiques


Implementing a Genetic Algorithm on a Parallel Custom Computing
Machine
N. Sitkoff, M. Wazlowski, A. Smith, H. Silverman
Brown University



		      Session 8: Applications 2


Rapid Prototyping of a RISC Architectur for Implemention in FPGAs
Russell Meier
Iowa State University


Implementation of a Parallel VLSI Linear Convolution Architecture
Using the EVC1s
H. Chow, S. Casselman, H. Alnuweiri
University of British Columbia


Convolution on Splash 2
N. Ratha, A. Jain, D. Rover
Michigan State University


Implementing Hidden Markov Modelling and Fuzzy Controllers in FPGAs
Herman Schmit, D. Thomas
Carnegie Mellon University



			Friday April 21, 1995

		    Special session on commercial
	   Custom Computing Machines, Software, and Devices

Scheduled participants include:

Annapolis Micro Systems
Atmel
Escalade
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Article: 1015
Subject: MINC's PLDesigner-XL Series
From: Alex Luccisano <alucci@io.org>
Date: 13 Apr 1995 23:49:38 GMT
Links: << >>  << T >>  << A >>
I would very much appreciate any feedback on the MINC 
series of PLD Design Tools.  I'm looking at the entry-level 
version for now, called Prelude, but would also like 
comments about the higher end versions such as Prodigy and 
Professional. 
 
>From my investigations so far, MINC seems to have a good 
set of upgradeable software tools, but I need some real-world 
feedback before making the leap.  I am targeting PAL/GAL's and 
CPLD's (later on) from Lattice or AMD or Altera (haven't  
decided yet.) 
 
Thanks in advance. 
 
Alex Luccisano 
email: alucci@io.org 




Article: 1016
Subject: $40 Million For NeoCAD & A New FPGA Synthesis Tool
From: jcooley@world.std.com (John Cooley)
Date: Fri, 14 Apr 1995 13:05:03 GMT
Links: << >>  << T >>  << A >>
Concerning the NeoCAD purchase that so many in the FPGA design world are
up in arms about because it just took a damn good general purpose FPGA
Place & Route tool and made it Xilinx proprietary -- I heard that NeoCAD
was sold for $35 to $40 million because of competitive bidding with
companies like Mentor Graphics and the likes.  To me, this indicates 
that although this provided a nice kick in the groin to two of Xilinx's
competitors (AT&T Orca and Motorola FPGA) who relied on NeoCAD for
Place & Route support & software, Xilinx will be quite serious about
using & promoting NeoCAD's tools.  That is, this was far too much $$$
to spend on just being cut-throat to a competitor.

----------------------------

Next week, a small FPGA start-up formed by an ex-Mentor synthesis R & D
guru, Ken McElvain, will be announcing a rather unusual FPGA synthesis
tool for both the PC and UNIX marketplace.  What makes this tool so
different is closely reflected in the name on the company: Synplicity.

Ken's tool takes in Verilog or VHDL source code and synthesizes it
with NO SWITCHES -- that is, the GUI consists of:

        Source File:_____________________

        Result File:_____________________

         -----------       ------------
         |   RUN   |       |  CANCEL  |
         -----------       ------------

There is no mechanism for putting in timing constraints; it just designs
Actel, Altera, Cypress, Quicklogic and Xilinx FPGA's with the default
setting of "make as fast as you can."  In addition, the time it takes
to build these designs is supposedly 10x - 100x *faster* than its FPGA
synthesis competitors (according to Synplicity supplied benchmarks.)

Although I always doubt vendor supplied benchmarks and reviewing software
I haven't designed with myself, I can comment on the idea of a super-simple
FPGA synthesis tool -- I think there are ASIC designers who would love
something like this for protyping using FPGA's if it could provide even
halfway useable results.  (It could be argued that *any* FPGA synthesis
tool could be run in this matter just by using the default settings; but
I don't think these competitor's tools were built with this as their
long term strategy.)

I'm going to be especially curious how Synplicity's new tool, Synplify,
handles the 1001 ways to write your source Verilog or VHDL problem and
getting good synthesis results.

Synplify will be available Q2 1995 and the U.S. price is $8,000 on the
PC and $16,000 on a UNIX workstation.  E-mail: info@synplicity.com

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3271 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1017
Subject: Re: PPR problem
From: allen@hex.viewlogic.com (Dave Allen)
Date: 14 Apr 1995 08:27:45 -0700
Links: << >>  << T >>  << A >>
TAM  ERNEST CHI YUI (tame@eecg.toronto.edu) wrote:
> When I want to ppr my design in XC4010, it says that the .xtf file is
> missing.  I used ppr before but that time, my design was made of 
> standard logic.  This time, all the building blocks are described in
> VHDL.  I am working in the Powerview environment.  I use vhdl analyzer 
> to analyze the source code and then use vhdl2sym to create the 
> symbol for each block.  Afterwards, I use Viewdraw to put together
> all the blocks and simulate.
> 
> Is there any step I have to do before I run the PPR program?
> How can I generate the .xtf file for PPR?

Are you using the Xilinx "xmake" program to run all of the Xilinx tools
automatically?  There are a number of tools in the Xilinx design flow,
such as wir2xnf, xnfmerge, and xnfprep.  The tools must be run in the
correct order, which is what xmake does for you.  The "xtf" file is one
of the intermediate files in this chain of tools.

- Dave Allen: allen@viewlogic.com


Article: 1018
Subject: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
From: jhallen@world.std.com (Joseph H Allen)
Date: Fri, 14 Apr 1995 20:48:39 GMT
Links: << >>  << T >>  << A >>
In article <D710CG.HMB@world.std.com>,
John Cooley <jcooley@world.std.com> wrote:

>Next week, a small FPGA start-up formed by an ex-Mentor synthesis R & D
>guru, Ken McElvain, will be announcing a rather unusual FPGA synthesis
>tool for both the PC and UNIX marketplace.  What makes this tool so
>different is closely reflected in the name on the company: Synplicity.

>Ken's tool takes in Verilog or VHDL source code and synthesizes it
>with NO SWITCHES -- that is, the GUI consists of:

When is someone going to write a freeware synthesis tool (or a even a $100
synthesis tool)?  This couldn't be that hard to do: simulated annealing for
placement is almost trivial, a maze-router for placement is straightforward,
as is a C to logic compiler.  A low quality synthesis tool shouldn't be that
hard to come out with.

Once there is a freeware synthesis tool, we could start a free hardware
foundation.  I could see a few high-level free hardware designs making a big
impact on FPGA sales.  Imagine if there was a free serial CPU design that
could fit in medium sized FPGA?  This is too much to write for one project,
but if a free version was out there I could see people integrating it in
their controller designs- a CPU with a tiny bit of custom logic would be
ideal.  FPGAs could be competative with micro controllers.  Likewise for
things like DRAM controllers, video controllers and stepper motor drivers.

Perhaps fear of this is the reason why Xilinx won't release their bitstream
format.  Some determined hacker should reverse engineer and publish it.
-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}


Article: 1019
Subject: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
From: Chris@ruatha.demon.co.uk (Chris G Abbott)
Date: Sat, 15 Apr 1995 10:26:16 +0000
Links: << >>  << T >>  << A >>
There is a piece on this buyout in the U.K Electronics Weekly Paper, in it
they state that the software will enevitably become device specific, but there
was a mention of some previous agreements that must be upheld.

-- 
God Bless

Chris Abbott
============================================================================


Article: 1020
Subject: Re: Need "fusemap" information from vendor, likely?
From: kahrs@gandalf.rutgers.edu (Mark Kahrs)
Date: 17 Apr 1995 00:09:48 -0400
Links: << >>  << T >>  << A >>
Speaking from personal experience, I can say that most vendors are
extremely relcutant to part with fuse maps, AMD included.  NDAs are
the norm, not the exception.  Cypress deserves kutos for keeping the
faith for those of us who wish to "roll our own".  Bear in mind
that no manufacturer wants to get involved with finger pointing
about device fuses...  But still...

Mark Kahrs
Rutgers U.

p.s. What's the use in writing CAD software if you can't make it real,
and how can you make it real if you can't use it on real devices?
(When fuse maps are outlawed, only outlaws will have fuse maps -
where have I heard that before?)




Article: 1021
Subject: BLIF to XNF translator
From: eea80593@maddux.EE.NCTU.edu.tw (Chuang Hsien-Ho)
Date: 17 Apr 1995 08:17:03 GMT
Links: << >>  << T >>  << A >>
Hi:

I want translate SIS's output(blif/slif/eqn...) to XNF format.
Does anyone has the translator? Or any other sugesstion to me?
Thanks a lot!

--
===============================
Hsien-Ho Chuang  
eea80593@yankees.ee.nctu.edu.tw
===============================


Article: 1022
Subject: Re: MINC's PLDesigner-XL Series
From: trev@ss11.wg.icl.co.uk (Trevor Hall)
Date: Tue, 18 Apr 1995 07:31:35 GMT
Links: << >>  << T >>  << A >>
 Alex Luccisano <alucci@io.org> writes :-

>I would very much appreciate any feedback on the MINC 
>series of PLD Design Tools.  I'm looking at the entry-level 
>version for now, called Prelude, but would also like 
>comments about the higher end versions such as Prodigy and 
>Professional. 
>
>From my investigations so far, MINC seems to have a good 
>set of upgradeable software tools, but I need some real-world 
>feedback before making the leap.  I am targeting PAL/GAL's and 
>CPLD's (later on) from Lattice or AMD or Altera (haven't  
>decided yet.) 
 
I have been using PLDesigner (the top of the range model) for about 3 years now .

Pro's :-
A very nice hardware description language, boolean/state machine/IF-THEN-ELSE and CASE
constructs/procedures & functions.
The fitters are good. 
AMD MACH support is very good.
PAL/GAL support ditto.

Cons :-
I have found a few bugs (minor) which MINC do not seem interested in fixing (their
resources are being used to develop new fitters, I am told).

Notes :-
For Altera (other than MAX5016 and 5032) & Lattice CPLDs you will need the vendors
fitters.
If you wish to target XILINX FPGA architectures I suggest you also use schematic 
capture (using PLDesigner for state machines etc.) as PLDesigner does not support all
the architectural features and busses are a pain to describe in the HDL.
Although the auto-partitioning tool works I have never used it in anger, as is the case
with the auto device selection (speed/power/cost constraints etc.).

In summary, I like it.
My own opinions etc. etc..

T.H.











Article: 1023
Subject: Viewlogic 4.1 & Windows '95
From: Mark@rmcecl.demon.co.uk (Mark Webster)
Date: Tue, 18 Apr 1995 07:54:31 +0000
Links: << >>  << T >>  << A >>
Hi,

Has anyone tried to use the DOS based Viewlogic suite of programs under 
Windows '95 ?

I have the XACT 5.1 basic kit for Xilinx FPGA's. At the moment I use 
the tools under DOS 6.22 & QEMM & I would like to install Windows '95.

TIA
-- 
Mark Webster



Article: 1024
Subject: Free Hardware
From: daveb@perth.DIALix.oz.au (David Brooks)
Date: 18 Apr 1995 17:11:47 +0800
Links: << >>  << T >>  << A >>
A few days ago, someone (my apologies, I didn't save a copy, and have 
mislaid their name) posted here, a proposal for "free hardware", along 
the lines of the Free Software Foundation.

As I recall, the proposal was twofold:

1. A set of free FPGA design software, produced and distributed similarly 
to Linux.

2. A "free CPU architecture", which could be implemented in FPGA's, and 
made generally available to be enhanced, etc. Presumably one would hope 
to port Linux to this, obtaining a "free system".

If I have quoted correctly, I would like to follow up thus:

1. Free CAD software would be (IMHO) welcomed widely. As I see it, there 
would be two obstacles, viz.

  a. The sheer size of the task - OK the Linux project shows it's possible.

  b. Getting the intimate design data (fuse locations) out of the FPGA 
     vendors. They seem very tight with it.

2. This would be a delightful challenge, but how practical is it? Unlike 
software, hardware cannot be copied at essentially no cost. With a free 
design, we still must either buy FPGA's, or persuade some kind soul to 
have some wafers run off. Presumably the "free" CPU would need to be 
either cheaper or faster than current commercial offerings. Some of the 
RISC chips are getting quite inexpensive.

On a more positive note, about 20 years ago, I built a homebrew CPU using 
some 120 TTL/MSI chips. 64kB space, operands 8-64 bits wide. The design 
could quite readily be modernised and migrated to a FPGA. If anyone is 
interested, I could do this, and am quite happy to publish the FPGA 
design files, as a "free CPU". However, it will never be as hot as a 
Pentium :)


-- 
David R. Brooks <daveb@perth.DIALix.oz.au>    Tel/fax. +61 9 434 4280
"Government is not reason. It is not eloquence. It is a force. 
Like fire, a dangerous servant and a fearful master." - G. Washington 





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