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Messages from 93275

Article: 93275
Subject: Re: Avnet hav2 s3e starter kit?
From: "Alex Gibson" <news@alxx.org>
Date: Mon, 19 Dec 2005 00:39:08 +1100
Links: << >>  << T >>  << A >>

"Antti Lukats" <antti@openchip.org> wrote in message
news:dnv9db$a90$03$1@news.t-online.com...
> "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag
> news:eEFof.83$lb5.41@news-west.eli.net...
>> "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)"
>> <steve.knapp@xilinx.com> wrote in message
>> news:1134761443.681907.191430@g44g2000cwa.googlegroups.com...
>>> The Spartan-3E Starter Kit board will be available in roughly two
>>> weeks.  You can sign up to receive E-mail notification when order entry
>>> is opened.
>> <snip>
>>
>> So no Christmas this year!
>> And here I was hoping "available in December" was a tease for the present
>> pile rather than a New Year's eve party favor.
>>
>> Thanks for the updates, Steve.
>>
>
> uups! I did think (silly me) that what Steve was referring to was that
> avnet will ship
> their s3e500 board in 2 weeks, as Xilinx promised the their S3e starterkit
> in December!
>
> well roughly 2 weeks means defenetly after christmas and possible not in
> 2005 at all.
>
> meaning that the only boards shipped from public online orders this year
> could be
> 1) s3e-100 eval from avnet
> 2) s3e-500 usb board from cesys
> 3) or is there any other s3e board already been shipped to customers
> (available for general public orders!)?
>
> but the xilinx s3e-starter board has most bang for the buck so it pays to
> wait for it of course
>
> Antti

Oh well, will just have to wait.
Was hoping to get one to have something to play with over christmas
to have a break from working with TI dsps.

I'll see if the local Avnet guys get back to me later today.

Alex

ps. Sorry about the title. Thats what happens when you try and finish off 
some work on a friday
before heading home after being dragged along to a wine and cheese night. 



Article: 93276
Subject: Re: How to use ISE FPGA Editor to compare timing path easily?
From: Duane Clark <dclark@junkmail.com>
Date: Sun, 18 Dec 2005 16:32:27 GMT
Links: << >>  << T >>  << A >>
linq936@hotmail.com wrote:
> Hi,
>   I have a memory controller desing implemented for Virtex4 chip. I
> know there are some timing problem and suspect that it is because the
> delay difference between the different timing pathes are too much.
> 
>   There is a common clock generated from DCM driving all the logic.
> 
>   Currently I launtch the desing in FPGA Editor and try to collect the
> delay for all the pathes, but that is really a lot of work. I start
> from the DCM output, count the delay one net by one net up to the pad,
> and sum them up.

Are you not using the FFs in the IOBs? If not, why not?

To specifically answer your question, in a case where for some reason 
you do not want to use the IOB FFs, the easy way to do that is to set a 
timing constraint for FF to PAD delay for the paths in question. Then 
the static timing report (*.twr) will tell you exactly what paths are 
failing, and exactly what all the delays are within those failing paths.

Article: 93277
Subject: Re: Altera based Video development board
From: Markus Knauss <markus.knauss@gmx.net>
Date: Sun, 18 Dec 2005 21:22:17 +0100
Links: << >>  << T >>  << A >>
Karl wrote:
> This should fit your needs....
> 
> http://altera.com/education/univ/materials/boards/unv-de2-board.html

Hi Karl,

thanks for the hint, I didn't find this board on the altera website yet.

Unfortunately, it has no composite video output, but vga output.
For composite video output, you usually need a video encoder chip.

I think that this can't be used as a composite color video (FBAS) output.

But if I don't find a board with video out, I will take this one
and add a video encoder on a separate board.

Thanks!

Markus

Article: 93278
Subject: Re: Altera based Video development board
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Sun, 18 Dec 2005 20:54:19 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Sun, 18 Dec 2005 21:22:17 +0100) it happened Markus Knauss
<markus.knauss@gmx.net> wrote in <do4gc9$7rc$1@online.de>:

>Karl wrote:
>> This should fit your needs....
>> 
>> http://altera.com/education/univ/materials/boards/unv-de2-board.html
>
>Hi Karl,
>
>thanks for the hint, I didn't find this board on the altera website yet.
>
>Unfortunately, it has no composite video output, but vga output.
>For composite video output, you usually need a video encoder chip.
>
>I think that this can't be used as a composite color video (FBAS) output.
>
>But if I don't find a board with video out, I will take this one
>and add a video encoder on a separate board.
>
>Thanks!
>
>Markus
What makes you think that you could not use one of the RGB 10bit DA channels
for FBAS out (composite?) composite is only 1 Vpp (in Europe).
On opencores.org IIRC there is even a PAL modulator.
Not sure if it will fit with that clock.

Article: 93279
Subject: Re: FPGA-pci communication
From: "Nitesh" <nitesh.guinde@gmail.com>
Date: 18 Dec 2005 12:58:29 -0800
Links: << >>  << T >>  << A >>
Thanks. I will look into it.Could you suggest me some books or websites
where I can get related material.
Nitesh


Article: 93280
Subject: Re: FPGA-pci communication
From: john.orlando@gmail.com
Date: 18 Dec 2005 15:42:54 -0800
Links: << >>  << T >>  << A >>
> This is the PCI controller of your board which initiates the burst transfer
> (bus mastering) ,
> Before that, either your application  (C/linux) or your design (VHDL) must
> provide transfer length AND physical memory
> start adress.
> Lookt at your doc to see how the  actual 'go' signal (i.e start DMA
> transfer) is provided to the controller (onthe board i use at work, it is up
> to the C application to write to a register of the DMA ctlr)
>
So...lets say that the FPGA was capable of bus-mastering, and thus
could initiate a PCI write transaction.  Lets say that the main system
processor (x86 or whatever) had already provided a set of physical
addresses to the FPGA through some other means (perhaps as a totally
separate PCI write transaction from the x86 to the FPGA).  My
understanding is that the FPGA is then capable of initiating a PCI
write transaction, where it can write data to, say, SDRAM that is
connected up to the main system processor, without any intervention
from the system processor itself.  I think the order of events would go
like this:
0) FPGA arbitrates for the PCI bus
0.5) FPGA is granted the PCI bus
2) FPGA starts a write transaction, with the target address being that
of SDRAM hooked up to the system processor.
3) Each data word is then clocked onto the PCI bus, received by the PCI
controller hooked up to the system processor, which then arbitrates for
the processor's local bus in order to write data to the local SDRAM.
4) When the FPGA has written all the data it wants, it would assert one
of the INTx lines to indicate to the system controller that data is now
available at the previously-assigned physical address.

Thus, no intervention from the system processor at all here...any flaws
in this logic?  Also, I assume that if the FPGA can do a burst write in
step 3 above, all of the data that is bursted onto the bus by the FPGA
will end up in the sequential physical memory locations in the SDRAM,
until either the system processor/PCI controller stops the transaction
or the FPGA simply ends.

Does this make sense?  

TIA,

John


Article: 93281
Subject: Re: Get Start for XtremeDSP Developement Board -IV
From: "Scott Bekker" <scottbekker@gmail.com>
Date: 18 Dec 2005 23:07:12 -0800
Links: << >>  << T >>  << A >>
Hi,

We have this same board, and have used both the USB with the FUSE
software and JTAG through Impact in ISE to program it.  There is a
connector on the board that fits standard JTAG programming cables from
Xilinx.  There is a simple example program that comes with the board
showing ADC and DAC connections.  You could use this with say a CoreGen
DDS or FIR filter with very little new VHDL.

Scott


Article: 93282
Subject: Powering unused MGTs in XC4VFX20CES2
From: Peter Rauschert <usenet@rauschert-online.de>
Date: Mon, 19 Dec 2005 08:23:19 +0100
Links: << >>  << T >>  << A >>
Hi!

I just read the Virtex 4 documentation and the errata sheet for the
XC4VFX20CES2 device and I'm thinking about one aspect I found while
designing a PCB.

My design will not use any one of the included MGTs. I found in the
Xilinx answer database that even unused MGTs need to be powered. Here,
the AVCCAUXTRX/RX voltage in the errata sheet is 1.1V while it is -0.5
- 1.32 in the V4 datasheet.

Since I have a supply for VCCINT with 1.2V on my board, I'm wondering
if 1.1V are only neccessary to power used MGTs, while 1.2V can be used
to power unused MGTs in the CES2 device ??

Thanks,
Peter

Btw.: Do I need any filtering?



Article: 93283
Subject: Re: Powering unused MGTs in XC4VFX20CES2
From: Peter Rauschert <usenet@rauschert-online.de>
Date: Mon, 19 Dec 2005 08:29:56 +0100
Links: << >>  << T >>  << A >>
Sorry, I forgot to ask another question. Since I'm using the ES2, the
transceiver pins for  MGT_110 are not available. 

Do I also need to power this MGT_110 with the suggested voltage?

Thanks,
Peter


Article: 93284
Subject: where can i get a release copy of ISE 8i?
From: lioupayphone@gmail.com
Date: 19 Dec 2005 00:24:24 -0800
Links: << >>  << T >>  << A >>
many thanks! ^_^


Article: 93285
Subject: Re: where can i get a release copy of ISE 8i?
From: "Jon Beniston" <jon@beniston.com>
Date: 19 Dec 2005 02:32:32 -0800
Links: << >>  << T >>  << A >>
You can download it of Xilinx's web site, providing you have paid for
it.

Cheers,
Jon


Article: 93286
Subject: Problem with downloading elf file to ML403 using XMD
From: "Thomas" <easy.anderson@gmail.com>
Date: 19 Dec 2005 04:05:34 -0800
Links: << >>  << T >>  << A >>
Hi,

I am currently working on a new board based on a Xilinx Virtex-4
FPGA.We are using a ML403 board as SW a development platform. The plan
is to run VxWorks (Tornado 2.2.1/Vxworks 5.5.1) so now I am trying to
get the VxWorks bootrom to run on the ML403.

I have used the XPS - Base System Builder Wizard to build a base system
that seems to work (I can run the memory test application Ok).
Using the VxWorks BSP from XPS I have build a VxWorks bootrom
(bootrom_uncmp) without any errors. I have used a Xilinx app. note as a
reference for building the bootrom.

I connect to the ML403 using JTAG cable and download my design (.bit
file), then I connect to to PPC using XMD with no problems. When I try
to download the bootrom file (dow bootrom_uncmp) I get the following
error form XMD: "Invalid Profile Start & End Memory Address". The crazy
thing is that if I keep trying to download then sometimes it downloads
Ok:

XMD% dow bootrom_uncmp
        section, .text: 0x00c00000-0x00c72a10
        section, .data: 0x00c72a10-0x00c79ed0
        section, .bss: 0x00c79ed0-0x00c7cfa0
Downloaded Program bootrom_uncmp
Setting PC with program start addr = 0x00c00000
PC reset to 0x00c00000, Clearing MSR Register

I can then execute the bootrom using 'run'. It doesn't work but that is
the next problem ;)

Have anybody seen the error: "Invalid Profile Start & End Memory
Address" before?
And what does it mean?

TIA,
Thomas


Article: 93287
Subject: Re: where can i get a release copy of ISE 8i?
From: Eli Hughes <emh203@psu.edu>
Date: Mon, 19 Dec 2005 10:06:03 -0500
Links: << >>  << T >>  << A >>
lioupayphone@gmail.com wrote:
> many thanks! ^_^
> 


This is probably not the forum ask where you can illegally download 
software.


-Eli

Article: 93288
Subject: Re: Inverter Chain Synthesis Problem
From: "John Penton" <john.penton@arm.com>
Date: Mon, 19 Dec 2005 15:48:35 -0000
Links: << >>  << T >>  << A >>
Davy wrote:
> Hi,
>
>  I work on Xilinx ISE, and my synthesis tool is XST and synplify.
>  I use verilog to write a Inverter Chain (delay ) like out =
> ~(~(~(~...in)).
>  But the circuit be synthesised cancel all the invorter.
>
>  How to synthesis out all the inverter chain I want?

Again, noting other's comments about generating delays, the simplest way to 
do this is simply to instantiate them (and don't flatten).

not_gate u_not_1 (
  .in  (input),
  .out (sig1)
);

not_gate u_not_2 (
  .in  (sig1),
  .out (output)
);

etc.

-- 
John Penton, posting as an individual unless specifically indicated
otherwise. 



Article: 93289
Subject: Re: Inverter Chain Synthesis Problem
From: Javier Castillo <javier.castillo@urjc.es>
Date: Mon, 19 Dec 2005 17:00:36 +0100
Links: << >>  << T >>  << A >>
On 15 Dec 2005 19:35:22 -0800, "Davy" <zhushenli@gmail.com> wrote:

>Hi,
>
>  I work on Xilinx ISE, and my synthesis tool is XST and synplify.
>  I use verilog to write a Inverter Chain (delay ) like out =
>~(~(~(~...in)).
>  But the circuit be synthesised cancel all the invorter.
>
>  How to synthesis out all the inverter chain I want?
>
>Any suggestions will be appreciated!
>Best regards,
>Davy

There are some works about delay elements for asynchronous designs in
Xilinx FPGA. Google for them.


Article: 93290
Subject: Differential Pin Pairs in Lattice EC FPGAs
From: "ALuPin@web.de" <ALuPin@web.de>
Date: 19 Dec 2005 08:21:36 -0800
Links: << >>  << T >>  << A >>
Hi newsgroup,

Altera has a command which is described as follows:

>The Show Differential Pin Pairs command shows a red connection line betwee=
n a pair of >differential pins. When one of the pins is assigned to a node =
that has a differential I/O >standard assignment, the complementary pin is =
considered assigned and unavailable for >future pin assignments.

Does Lattice provide something similar for its EC/ECP familily ?

Rgds
Andr=E9


Article: 93291
Subject: Re: Powering unused MGTs in XC4VFX20CES2
From: Austin Lesea <austin@xilinx.com>
Date: Mon, 19 Dec 2005 08:29:55 -0800
Links: << >>  << T >>  << A >>
Peter,

The requirement to power unused MGTs is to meet ESD performance.  If the 
power and ground pins are left unconnected (to the MGT), it is unknown 
what the ESD protection performance will be (basically, it is not tested 
that way).

The voltage can be 1.2V (no issue with 1.1V, as you are not using the MGTs).

Also, filtering is not required (as they will not actually be enabled).

If one MGT is left unpowered, be sure the ground supply pin is connected 
to ground, at a minimum.

Austin

Peter Rauschert wrote:

> Hi!
> 
> I just read the Virtex 4 documentation and the errata sheet for the
> XC4VFX20CES2 device and I'm thinking about one aspect I found while
> designing a PCB.
> 
> My design will not use any one of the included MGTs. I found in the
> Xilinx answer database that even unused MGTs need to be powered. Here,
> the AVCCAUXTRX/RX voltage in the errata sheet is 1.1V while it is -0.5
> - 1.32 in the V4 datasheet.
> 
> Since I have a supply for VCCINT with 1.2V on my board, I'm wondering
> if 1.1V are only neccessary to power used MGTs, while 1.2V can be used
> to power unused MGTs in the CES2 device ??
> 
> Thanks,
> Peter
> 
> Btw.: Do I need any filtering?
> 
> 

Article: 93292
Subject: Re: Differential Pin Pairs in Lattice EC FPGAs
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 19 Dec 2005 17:31:29 +0100
Links: << >>  << T >>  << A >>

<ALuPin@web.de> schrieb im Newsbeitrag 
news:1135009295.991659.181970@g47g2000cwa.googlegroups.com...
Hi newsgroup,

Altera has a command which is described as follows:

>The Show Differential Pin Pairs command shows a red connection line between 
>a pair of >differential pins. When one of the pins is assigned to a node 
>that has a differential I/O >standard assignment, the complementary pin is 
>considered assigned and unavailable for >future pin assignments.

Does Lattice provide something similar for its EC/ECP familily ?

Rgds
André

yes they do

antti 



Article: 93293
Subject: Re: ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i
From: "kelau" <klau@redback.com>
Date: Mon, 19 Dec 2005 10:52:17 -0600
Links: << >>  << T >>  << A >>
>Hello,
>
>just tried to get the ml403_emb_ref-project working. During MAP I get 8
>errors of the following type:
>
>ERROR:Pack:1564 - The dual data rate register
>  plb_ddr_0/plb_ddr_0/DDR_CTRL_I/IO_REG_I/DDR_DQS_REG_V4_I3
>failed to join the OLOGIC component as required  The OLOGIC SR
>signal does not match the ILOGIC SR signal, or the ILOGIC SR signal
>is absent. The OLOGIC REV signal does not match the ILOGIC REV
>signal, or the ILOGIC REV signal is absent.
>
>
>Any hints?
>
>Thanks and greetings
>Udo
>
>

I'm having these errors too.  Anyone who had that problem?  Udo, did you
get that fixed?

Kelvin





Article: 93294
Subject: Virtex II Pro XC2VP100
From: "rmanand" <murugs_india@yahoo.com>
Date: Mon, 19 Dec 2005 10:52:37 -0600
Links: << >>  << T >>  << A >>
Hi friends 

The Virtex II pro (XC2VP100) device is not Configuring through Impact7.1e


When i try to check with CRO what is happeing at the BOUNDARY SCAN SIGNALS
TDO ,TDI,TCK ,TMS 

I found TDI,TMS,TDI signals are okay .THE TDO is always stuck at
one(pulled up by 220 ohm resisitor preferred by xilinix). 

The prog Pin is pulled up to 3.3V through 4.7k.The Init pin is pulled up
to 3.3v through 4.7k.These all are xilinx reccomendation. 

I could not understand what will be reason for the TDO is always high at
one and how to solve the problem. 
 

The impact is always throughing Impact -583 error. 
Expeting your valuabe replies

Thanks in advance 



Article: 93295
Subject: Re: Powering unused MGTs in XC4VFX20CES2
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Mon, 19 Dec 2005 09:16:18 -0800
Links: << >>  << T >>  << A >>
Peter Rauschert wrote:
> Hi!
> 
> I just read the Virtex 4 documentation and the errata sheet for the
> XC4VFX20CES2 device and I'm thinking about one aspect I found while
> designing a PCB.
> 
> My design will not use any one of the included MGTs. I found in the
> Xilinx answer database that even unused MGTs need to be powered. Here,
> the AVCCAUXTRX/RX voltage in the errata sheet is 1.1V while it is -0.5
> - 1.32 in the V4 datasheet.
> 
> Since I have a supply for VCCINT with 1.2V on my board, I'm wondering
> if 1.1V are only neccessary to power used MGTs, while 1.2V can be used
> to power unused MGTs in the CES2 device ??
> 
> Thanks,
> Peter
> 
> Btw.: Do I need any filtering?
> 
> 

The powering requirements for unused MGTs are to make sure that
everything on the part is in a known state.  This means that you
can cut some corners for these MGTs.  You can safely power the AVCCAUXTX
and AVCCAUXRX from your VCCINT 1.2V supply and not the 1.1V and you don't
need any power filtering on these pins.

You comment regarding 1.1V in the current errata vs -0.5 to 1.32V in the
V4 datasheet is a mistake.  The former is for AVCCAUXTX/RX and the later
is only for the VTRX supply.

Ed

Article: 93296
Subject: Re: Powering unused MGTs in XC4VFX20CES2
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Mon, 19 Dec 2005 09:17:23 -0800
Links: << >>  << T >>  << A >>
Peter Rauschert wrote:
> Sorry, I forgot to ask another question. Since I'm using the ES2, the
> transceiver pins for  MGT_110 are not available. 
> 
> Do I also need to power this MGT_110 with the suggested voltage?
> 
> Thanks,
> Peter
> 

Yes you need to power this transceiver as well.

Ed

Article: 93297
Subject: Re: Mean value filter
From: "JustJohn" <john.l.smith@titan.com>
Date: 19 Dec 2005 10:35:18 -0800
Links: << >>  << T >>  << A >>
Weng wrote:
>I am wondering if there is a median value filter algorithm to deal with
>1 pixel for 1 clock. That is, one pixel is in and one pixel is out in
>real time.
(Sigh)
Yes there is. The graphs in the note are part of what is needed to do
this. What was not shown in the note was the required line delay
buffers (see below). The note was intended to demonstrate how the
XC4000 carry logic could be used for more than simply adding and
subtracting, carry logic is also handy for sorting networks.

>Is there any advantage if the algorithm is found?
Advantage compared to what? And the algorithm is not missing. Weng, as
you do more designs, you will see that there are always trade-offs.
There is another clever implementation (possibly better for ASIC) that
takes a bit-serial approach, and can be modified for arbitrary rank.
This was worked out by Khaled Benkrid in a back issue of SPIE 'Journal
of Electronic Imaging' (I don't have the issue handy, you'll have to
look that up yourself). Another median implementation might use a
single comparator, some RAM, and 19  clock cycles (or 13 with partial
result re-use).

>The article and the algorithm you mentioned from Xilinx design paper
>uses 3 clock to handle 1 pixel.

No, wrong, look again. The graphs only represent the flow of data, and
both graphs in the note may be implemented to produce one output pixel
per clock (remember, lots of trade-offs are possible). Preceding the
graphs, you need to implement two line delay buffers. Source video
feeds the input of your first line delay. The output of the first line
delay feeds the input of the second line delay. Source video and the
two line delay buffer outputs feed into the pipelined version of the
sorting network. Add muxes to handle special cases for first and last
line output. This is video, so here's a picture. I haven't included the
muxes, but this is what feeds the sorting network. I've labeled the
pixels to correspond to fig. 3 in the xcell note.

(use fixed width font):
Video In --+-------------------->P1, P4, P7
           |  +------------+
           +->| Line Delay |--+->P2, P5, P8
              +------------+  |
           +------------------+
           |  +------------+
           +->| Line Delay |---->P3, P6, P9
              +------------+

Now Weng, I can't give you everything, you are going to have to figure
out for yourself how to do the line delays, and where to put and how to
wire the muxes. The exercise will do you good.

Regards, and good luck,
John


Article: 93298
Subject: Virtex-4 Startup
From: "=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=" <taileb.mehdi@gmail.com>
Date: 19 Dec 2005 10:42:53 -0800
Links: << >>  << T >>  << A >>
Hi all!
Can some one be kind and explain me the startup cycle of an Virtex-4?
Is the logic activated AFTER the GSR is asserted of should I add some
logic to wai for the end of the startup?
For what is the SARTUP_VIRTEX4 primitive?

Cheers
Mehdi


Article: 93299
Subject: Re: ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i
From: "Newman" <newman5382@yahoo.com>
Date: 19 Dec 2005 10:54:31 -0800
Links: << >>  << T >>  << A >>
Under EDK, did you try tools : clean : all? I'm using EDK 7.1.02i  ISE
7.1.04i

Newman




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1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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