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Steve wrote: > The Xilinx memory generator tool generates ucf files that have lines > in them such as: > > NET "ddr1_top0/data_read0/fifo*_wr_addr(*)" MAXDELAY = 2350ps; > > I get parsing errors on both the / and (). I need to replace with _ > and <> like: > > NET "ddr1_top0_data_read0_fifo*_wr_addr<*>" MAXDELAY = 2350ps; > > Is there a setting for this somewhere? In ISE6.3 it's in the Synthesis Options (right-click on "Synthesize - XST" in Project Navigator and chose "Properties"): Scroll down, there's two options, "Hierarchy Seperator" (which is for changing _ to / or vide versa) and "Bus Delimiter" (which is for changing () to <> or vice versa). You might have to activate the advanced settings mode (Menu "Edit" in Project Navigator -> "Preferences" -> "Processes" -> set "Property Display Level" to "Advanced") for these to show up. cu, SeanArticle: 81276
Hello from the Eighth Doctor (Apologies if this question is not group appropriate.) It seems my company's perenial problem with the PAL chips have sprouted again. The same individual that we created a something or other for, using a collection of PAL chips, and some normal glue logic wants us to make more of these things. Essentially a follow on to that thing. What it's supposed to do isn't the problem. Yet. It's the programming of the blank parts that is the problem. We've located which parts we want to use, and the PALASM software for writing the programs. But we need reccomendations on which programmer to select, and whose. --- Gregg drwho8 atsign att dot net "This signature disavows itself of the above message." However we need a programmer for the little devils.Article: 81277
The Eighth Doctor wrote: > Hello from the Eighth Doctor > (Apologies if this question is not group appropriate.) > It seems my company's perenial problem with the PAL chips have sprouted again. > The same individual that we created a something or other for, using a collection of > PAL chips, and some normal glue logic wants us to make more of these things. > Essentially a follow on to that thing. What it's supposed to do isn't the problem. > Yet. It's the programming of the blank parts that is the problem. We've located > which parts we want to use, and the PALASM software for writing the programs. > But we need reccomendations on which programmer to select, and whose. > --- > Gregg drwho8 atsign att dot net > "This signature disavows itself of the above message." > > However we need a programmer for the little devils. Some part numbers would help.. You need to look at the Programmer vendor web sites, such as eetools.com, and search their device lists. Just type the PAL part numbers into google, and it usually finds the programmer device lists, so you can work from those.Article: 81278
I have a problem when simulating with samsung ddr behavioral model, I have tested my design with micron behavioral model but micron is not accurate regarding the tDQSS time constraint. so I used the samsung model, but I don't know why the DQS bus in write transactions goes to X state. it seems that the behavioral model tries to force on the DQS while the controller tries to force on the DQS. so the result goes to X state. I am not sure, my design is in VHDL and the samsung model in Verilog I uses ModelSim 5.5e PLUS to do the simulation I dunno where is the problem, can anyone help?Article: 81279
Hi, i wrote a few mpeg decoding blocks (VLD, inv.ZigZag, inv.Quant, IDCT). By now i am able to decode a macroblock of a mpeg-1 I-Frame. This logic needs about 18 % of a XC3S1000 and is not very optimized. The largest block which is still missing is the motion compensation. So i think the Avnet board will be perfect for your needs. Thomas "Marc Randolph" <mrand@my-deja.com> wrote in message news:1111239707.556409.191840@o13g2000cwo.googlegroups.com... > kevin@nospam.nospam wrote: > > I'm looking for a development board to implement an MPEG-2 video > decoder, > > and currently interested in ADS-XLX-SP3-DEV1500 available from Avnet, > which > > comes with the following components: > > * Xilinx XC3S1500/2000-FG676 Spartan-3 FPGA > > * 128x64 OSRAM OLED graphical display > > * DB15 & video DAC > > * Audio CODEC > > * PS2 keyboard & mouse ports > [... snip stuff like the Piezo buzzer and connectors ...] > > * Micron DDR SDRAM (32 MB) > > * 16 MB FLASH > > * 2 MB SRAM > > * 10/100 Ethernet > > * USB 2.0 > [...] > > The peripherals seem more than enough, but I still wonder > > whether the logic resources in XC3S1500 is sufficient. > > Howdy Kevin, > > That's quite a development board! Seems like it would be perfect for > your project and you should have no problems fitting an mpeg decoder in > that device. Compared to past FPGA's, XC3S1500 is quite a large device > - in fact, Xilinx has an IP partner that has a mpg decoder core which > fits in a 3S1000: > > http://www.xilinx.com/bvdocs/ipcenter/data_sheet/Amphion_CS6651.pdf > > I see that their core runs at only 50 MHz. With just a little bit of > attention, running at 100 MHz in the S3 should not be a problem. Going > out on a limb just a bit (it's a pretty strong one), you could likely > code up two decoders in the space of their one, or one decoder that > takes up half the space of theirs. > > Have fun, > > Marc >Article: 81280
"Jason Lewis" <wyvwyv@yahoo.com> wrote in message news:<113snlfcb8rtt05@corp.supernews.com>... > Has anyone checked out the new TI power supply for FPGAs, the TPS75003: > http://focus.ti.com/docs/prod/folders/print/tps75003.html > > I was considering it for a potential Spartan-3E design and was looking for > feedback from anyone who has sampled it or knows more about it. In > particular, I was wondering if the reference design on page 7 of the > datasheet was well suited for the -3E, or if anyone recommended other parts > or modifications. > > Thanks :) We are now in the design phase of a product with two Spartan3 XC3S200 FPGA's. I could get samples from TI directly. I just used the reference design practically as is, with POSCAP capacitors on the outputs + a few ceramics. The prototype should be available in about one month. If you are interested in comments then, please feel free to address me a small E-Mail in a few weeks.Article: 81281
"Jason Lewis" <wyvwyv@yahoo.com> wrote in message news:113snlfcb8rtt05@corp.supernews.com... > Has anyone checked out the new TI power supply for FPGAs, the TPS75003: > http://focus.ti.com/docs/prod/folders/print/tps75003.html > > I was considering it for a potential Spartan-3E design and was looking for > feedback from anyone who has sampled it or knows more about it. In > particular, I was wondering if the reference design on page 7 of the > datasheet was well suited for the -3E, or if anyone recommended other > parts > or modifications. For this sort of thing, I usually get a couple of samples and make a simple test PCB for myself. I've just ordered a couple of samples to play with. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 81282
"Paul Marciano" <pm940@yahoo.com> wrote in message news:1111366024.805222.276390@o13g2000cwo.googlegroups.com... [snip > ll most likely get the larger > Digilent board, and forget about microblaze. >A shame though. > Hi Paul! Go for the Picoblaze instead, it's free and comes with tools. DJ --Article: 81283
Hello Vasanth, About the malloc function, as you said "this is a known limitation", can you tell me where this is written in the documentation ? (I knew the IOCM is a 32-bit write only port for the Virtex II Pro but I didn't read anything about relocation). thanks again Pierre (XPS & ISE v6.02) > Vasanth Asokan <vasanth.asokan@xilinx.com> wrote in message news:<422E5CDA.6080206@xilinx.com>... > > We compile newlib with -mrelocatable-lib option. This produces code that > > contains pointers stored in the .text, instead of the .data. Since, > > reading from the OCM on Virtex 2P is not supported, such code will not > > work. malloc is one of our library routines that will fail. This is a > > known limitation. Please move such library routines into other readable > > memories. Then your code will work. > > > > thanks, > >Article: 81284
lecroy7...@chek.com wrote: > > I am starting to suspect that the devices internal oscillator has a > problem. There is very little information about it. There appears > to be no way to detect it's failure. > If you ever are able to reproduce the problem at will, probably the easiest way to check the health of the internal CCLK is to place the part in master serial mode before initial powerup, so you can observe the behavior of the CCLK output under the lockup-generating conditions. Unfortunately, my earlier suggestion (copied below) of trying to switch the locked up part into master mode to observe CCLK won't work if the internal CCLK isn't present: the 'deglitching' samplers on PROG and RESET, needed to perform the switch, are driven by that same internal CCLK source. earlier, I wrote: > > When you next induce this problem, here are some random thoughts > on additional sticks with which to poke at the stuck FPGA: > > - longer ( >>6us ) reset and program pulses > > - send more config data than needed and look for data to appear > on DOUT > > - if possible, stop driving CCLK externally, switch the mode pins > on the stuck device to master serial, then reset and look for > CCLK coming out of the part > good luck, BrianArticle: 81285
leonqin wrote:
> Cyclone2 will be good
Good for what?
Best regards
Piotr Wyderski
Article: 81286
ibrahim_magdy_ibrahim@hotmail.com wrote:
> I have a problem when simulating with samsung ddr behavioral model, I
> have tested my design with micron behavioral model but micron is not
> accurate regarding the tDQSS time constraint. so I used the samsung
> model, but I don't know why the DQS bus in write transactions goes to X
>
> state. it seems that the behavioral model tries to force on the DQS
> while the controller tries to force on the DQS. so the result goes to X
>
> state.
> I am not sure, my design is in VHDL and the samsung model in Verilog I
> uses ModelSim 5.5e PLUS to do the simulation
> I dunno where is the problem, can anyone help?
>
Hi,
I am guessing you have the classic test bench where the inputs to the
unit under test (UUT) are being changed precisely at a clock edge????
This results in the indeterminate ("X") state.
If your test bench is in Verilog then an extra #1 at the start of your
initial block with respect to the clock generating loop should fix this.
For VHDL testbench a "wait for 1 ps" or something similar should do.
Enjoy,
Tim
Article: 81287On Sun, 2005-03-20 at 21:43 -0800, Jason Lewis wrote: > Has anyone checked out the new TI power supply for FPGAs, the TPS75003: > http://focus.ti.com/docs/prod/folders/print/tps75003.html > > I was considering it for a potential Spartan-3E design and was looking for > feedback from anyone who has sampled it or knows more about it. In > particular, I was wondering if the reference design on page 7 of the > datasheet was well suited for the -3E, or if anyone recommended other parts > or modifications. I have checked it out as well. One thing I noted is that for the 1.2V rail (which you'll need for the core) the maximum best-case efficiency from a 5V input is just shy of 80% and for everything other than load around 1A you're looking at max 75%. I am working on a Point-of-Load supply that supplies the same 3 outputs (3A for core, 3A for I/O of variable voltage, and 250mA for Vaux) but in a device similar to the POLA devices from TI and others. The initial circuit is getting around 86% efficiency at 2A on my bench from 5V input. I haven't fully qualified it through the range though. As an added bonus, there will be a serial PROM option that will save you even more board space by moving all the support circuitry for the FPGA onto a daughterboard. I intend to make this supply available for sale if you're interested. There is also a 6A version in the forecast as well for even more dense designs. Contact me at salNes2005@stOratSPfordAdigitMal.ca if you're interested (remove the CAPITAL letters from that email address). Cheers.Article: 81288
I am looking for the simplest Parallel port to virtex 2 IO voltage converter. I would like to use the default Virtex 2 IO standard which is used by ISE (Is it LVCMOS33?) I was aware that normal level converter output voltage follows the power supply and I don't want to trouble having a 3.3V power supply. Thank?you.?Article: 81289
"Lin MuIin" <lin_mulin@yah0o.c0m.au> wrote in message news:d1mh0m$jr6$1@reader01.singnet.com.sg... >I am looking for the simplest Parallel port to virtex 2 IO voltage >converter. > I would like to use the default Virtex 2 IO standard which is > used by ISE (Is it LVCMOS33?) > > I was aware that normal level converter output voltage follows > the power supply and I don't want to trouble having a 3.3V power supply. > > Thank?you.? > > > Parallel?port?to?LVTTL?standard?level?converter.? Anyone? Thanks.Article: 81290
I got my ISE 7.1 update DHL'd to me this morning, here is my experience so far A problem... I tried to install 7.1 in the same place as 6.3 (after accepting the de-install option) c:\program files\xilinx, but it didn't work, the installer displayed cryptic error messages about the disk being full - it wasn't. Okay so I'll try c:\programs\xilinx - this worked. Xilinx take note - if you no longer support spaces in file name THEN WHY DO YOU ALLOW ME TO ENTER THIS INTO IN THE FIRST PLACE? Disapointment... So now I've go it installed, and I'm hoping when I run it maybe they will have upgrade the UI since this is a major version upgrade. Whay do I find ? They've made the UI EVEN WORSE, THEY'VE ADDED EXTRA CLUNK! Yes ISE users, you know what I mean, the user interface looks like an application from the Window 3.1 era, but somehow they've made it look even worse! One example, now we have lovely icons to remind us the meaning of 'Errors' and 'Warnings' on the tabs for the messages window - they weren't there in in 6.3. Okay so looks aren't everything. So maybe this release they've updated the menu to show a function key shortcut for commonly used actions, such as process|re-run, it would be nice just to press F5 or something for this. Have they done this? No. Maybe I'll check the help just in case. Select help from the menu, select search, okay so where do I type in my search word? This just looks like an index to me not a search facility ! ARGGGGG Okay, I could go on and on about the lack of usability. Perhaps coming from a programming background I've just been spoilt by wonderful IDE's like IntelliJ IDEA that have been designed with the engineer in mind. I use the ISE Web Version at the moment, but I really don't ever want to shell out $2,500 for the Foundation version given my opinion of this software.... are there other alternatives around the same price bracket? Andy.Article: 81291
I'm sure you should just be able to tie the upper 16 to ground on a 64-bit controller? Hopefully synthesis will remove most of the registers and logic for those unused data lines. -- Pete Piotr Wyderski wrote: > Ben Twijnstra wrote: > > > I don't have definite specs handy, but Cyclone 1 can control DDR SDRAM > > at 133MHz (see the Twister board at http://www.fpga.nl). > > Yes, I have seen the same specification and I wonder why it is > so slow. I have some SDR memories with fmax = 183MHz, so > I would like to know whether it is possible to use them with a > Cyclone at that speed. The next problem is that the data path > width will be 48 bits and the megafunction documentation says > that the controller is capable of doing 16-, 32- and 64-bit transfers. > But how about 48 bits? :-) > > Best regards > Piotr WyderskiArticle: 81292
Hello, everyone. I could not find am answer on the web for the following question, which i am not quite comfortable to ask, but who else to ask it, except FPGA/ASIC people? Can anybody, please, point me to a website or give me any approximations about what salary is considered "average" and what is considered "top" in the following places, if we are talking about senior FPGA design engineer position? (I have 6 years of ASIC/FPGA design experience, 4 from Israel + 2 from Canada) (1) Montreal (2) Vancouver (3) Toronto (4) Ottawa I would also highly appreciate any info/weblinks about living cost in Vancouver. Thank you all very much for your time and attention. Sincerely, Vladislav MuravinArticle: 81293
Hi Andy, > I use the ISE Web Version at the moment, but I really don't ever want > to shell out $2,500 for the Foundation version given my opinion of this > software.... are there other alternatives around the same price > bracket? Try out Quartus II. You can download the free version (called "Web Edition") from our website www.altera.com. The Quartus GUI is generally pretty easy-to-use and has the look-and-feel of a modern Windows application. If you need help understanding the Altera flow, see AN307: Altera Design Flow for Xilinx Users (http://www.altera.com/literature/an/an307.pdf). Also useful is the Xilinx to Altera design migration website (http://www.altera.com/products/software/switching/x/qts-x2a_migration.html). Regards, Paul Leventis Altera Corp.Article: 81294
Hi Austin, thanks for your comments. As I understand you, the logic-fabric is the limiting factor in Spartan 3(E), not the IOs. I do not need Gbs-speed, just around 600 Mbs will be OK. (So I think I need 300MHz with DDR at the IO.) Can this be done in the Spartan3(E)? When doing simple tests with D-FFs and T-FFs, I got frequencies in the range from 300 to 600 MHz, not really reproducable. Strange... I have not tried to implement the complete serializer yet. Is there also a limit from the clock-network? In the datasheet I states, that the -4-speedgrade can produce up to 330MHz at the DLL-CLKOUT_FREQ_2X, so I think the clock-network can handle this frequency? I understand that you want to sell Virtex, but please understand that we want to buy Spartan or Cyclone, even if it are just 1000+ pieces ;-) Regards, Thomas "austin" <austin@xilinx.com> schrieb im Newsbeitrag news:d1k9tv$kae1@cliff.xsj.xilinx.com... > Thomas, > > The maximum speed of the LVDS buffers is a good question for me to try to > shed some light on in this forum. > > The LVDS buffers (both input, and output) are built from the 0.25 micron > gate oxide transistors we use for IO in all devices since Virtex II Pro. > These same devices are used for the 3.125 Gbs MGT front ends, so the > transistors themselves are extremely quick. > > But, it is all in the sizing, and a regular IO is burdened by having to > support 34 other IO standards. These LVDS IOs were not designed to work > beyond 1 Gbs. Not that we did anything intentional to make them slow, we > just didn't model them at all corners above 1 Gbs because is was not a > requirement. As such, the interconnect and logic is not sized for Gbs > speeds, either into, or out of, the IOB. > > Why isn't it a requirement? Well, the fabric can't handle it anyway. > > By that, I mean it is not the IO that is the limiting factor for any given > standard. Take Aurora, or SPI POS 4.X, or some other IO protocol and > signalling 'standard' for example. You must have a clock synchronization > system, data multiplexing/demultiplexing that meets the standard. And > also a core with the state maqchines, CRC, BRAM FIFO's, etc. > > In Virtex 4 (my favorite subject) we have the Source Synchronous IO blocks > for every I/O pin which is a serdes for each pin: this easily matches Gbs > speeds on DDR IO pins to the fabric at 1/2, 1/4, 1/8 (etc) speeds along > with allowing for fixed or dyanamic bit eye slicing to get the best > possible link. That hardware is definitely limited by the LVDS. The LVDS > in V4 is running at 1.4 to 1.5 Gbs (spec'd at 1 Gbs), but we haven't > characterized it over all corners, voltage and temperatures. We just may, > but only after we have the entire interface designed to support it. > > No reason to have fast IO if there is nothing to support it. The opposite > is also true, a fast core is useless without the fast IO. > > Basically, if you want Gbs performance, we have a cost effective part for > that, the Virtex 4. Spartan 3 and 3E (identical 90nm technologies) are > intended for large volume low cost applications below ~300 MHz global > clock speeds. > > The triple oxide technology in V4 provices us with a substantial increase > in interconnect performance required for 500 MHz clocked logic. Spartan 3 > and 3E don't have that Ace up their sleeves. > > Spartan 3, and 3E are intended to address the best IO/$, and the best > logic/$ sockets. I would not distinguish between them on the basis of > performance or speed: they represent vitually identical devices cost > optimized for the two different application spaces (logic vs. IO). > > Austin > > Thomas Entner wrote: > >> When we are talking about IO: Does anybody (i.e. Austin ;-) know the max. >> LVDS-transmit-rate of Spartan 3E, slowest speed-grade? >> >> Regards, >> >> Thomas >> >> www.entner-electronics.com >> >> "Luc" <lb.edc@pandora.be> schrieb im Newsbeitrag >> news:lmmm31lrm84tielfem34qtqdmfj9eu8gpg@4ax.com... >> >>>Ben & Paul, >>> >>>Thanks for the feedback. >>>I wonder what X & L could add to their defence. >>> >>>What about DDR or DDR2 support? >>>This is certainly somthing I'm looking for. Multipliers are benificial >>>but not a necessity. >>> >>>Regards, >>> >>>Luc >>>On 18 Mar 2005 13:55:56 -0800, "Paul Leventis" >>><paul.leventis@utoronto.ca> wrote: >>> >>> >>>>Hi Luc, >>>> >>>>I don't have much to add -- Ben has covered most of the high points. >>>> >>>> >>>>>Has someone seen samples yet, knows something more how they compare >>>>>(performance, pricewise). >>>> >>>>On a performance front, you will find that Cyclone and Cyclone II have >>>>a significant performance advantage over Spartan-3. We're talking >>>>50-60% (core performance on 100+ designs, comparing fastest speed grade >>>>to fastest speed grade using best-possible software settings). >>>> >>>>But don't take my word on it. Download our freely available Quartus II >>>>Web Edition and give your design a whirl in Cyclone/Cyclone II. Do the >>>>same for Spartan-3. >>>> >>>>Regards, >>>> >>>>Paul Leventis >>>>Altera Corp. >>> >>Article: 81295
Are you sure about that 11 Gbps figure? I've just had a look to the latest 'ug' from Xilinx http://direct.xilinx.com/bvdocs/userguides/ug076.pdf and still says it can run up to 10.3125 Gbps... so... a pity that they are missing OTU2 (10.709 Gbps). This implies you still need an LIU between your optics and your V4 if you want to go up to OTU2, doh! It will support OC192... probably with the xpensive/fastest speed grade. -- I.U. Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson "Wing Fong Wong" <wing@stu.edu.au> wrote in message news:d1gfc4$nap$1@enyo.uwa.edu.au... > Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: >> Our Virtex-II Pro X and Virtex-4 families have higher bandwidth >> RocketIO MGTs and can operate above 10 Gbps. >> > > Virtex 4 can do up to 11.1Gb/s to be exact. > > -- > > Wing Wong.Article: 81296
Hi <ibrahim_magdy_ibrahim@hotmail.com> wrote in message news:1111397625.457090.174770@f14g2000cwb.googlegroups.com... >I have a problem when simulating with samsung ddr behavioral model, I > have tested my design with micron behavioral model but micron is not > accurate regarding the tDQSS time constraint. so I used the samsung > model, but I don't know why the DQS bus in write transactions goes to X I have used the MICRON verilog model for my simulation... - MT46V32M16 (8 Mb x 16 x 4 Banks) - Micron 512 Mb SDRAM DDR (Double Data Rate) it worked fine in simulation, no problem with tDQSS and then it worked on the card ;O) one thing I suggest is just make sure you simulate your Clock2Out, Pad to Clock, DCM skew, PCB delays and all that stuff > > state. it seems that the behavioral model tries to force on the DQS > while the controller tries to force on the DQS. so the result goes to X Maybe your DDR controller things you are actually performing a RD command... > state. > I am not sure, my design is in VHDL and the samsung model in Verilog I > uses ModelSim 5.5e PLUS to do the simulation > I dunno where is the problem, can anyone help? Verilog mixed with VHDL no problem at all. -- I.Ulises Hernandez " I'm not normally a praying man, but if you're up there, please save me, Superman!" - Homer Simpson ;O)Article: 81297
Hi, I am thinking about implementing a WLAN Interface with a FPGA. Has anybody done this before, or does anybody have some information about this? regards, BenjaminArticle: 81298
> > I'm grateful to Xilinx and Altera for making their design entry and > synthesis tools available for free. I wish they'd do the same for > their EDK (but then, if they did, I'm sure I'd also want a free MAC, or > PCI core). > > Thanks for all the links Alex. I'll most likely get the larger > Digilent board, and forget about microblaze. A shame though. > Hi Paul, You can download a free evaluation of the complete set of Nios II tools here: https://www.altera.com/support/software/download/nios2/dnl-nios2.jsp?f=ni2hp&k=g2 Our system integration tool (SOPC Builder) is included free with Quartus, and with Nios II you get a whole suite of IP, configurable processor choices, and IDE: http://www.altera.com/products/ip/processors/nios2/ni2-index.html There are a lot of features and more are being constantly added (such as your choice of 100% vhdl or verilog, push-button RTL simulation of your system running code, clock-domain crossing with a couple of mouse-clicks, multi-processor debugging, RTOS integration (eCOS, uClinux, MicroC/OS-II, and several more), complex example designs, etc. The free evaluation tools are only crippled in one way: The Nios II CPU has to be used in a "tethered" mode where your download cable has to be connected to the target board; you can then evaluate the product in hardware as long as you want. The full-blown license is about $1K US with a very nice dev board, less for just the subscription to the processor only. We also recently introduced a $295US evaluation kit with Cyclone 1C12/flash/sdram, etc.: http://www.altera.com/products/devkits/altera/kit-nios_eval_1C12.html Hope you'll consider us as well. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 81299
When I purchased a development kit for my own projects, the development software played as much a factor in my decision as the target device. What it came down to was, me asking myself, what is going to effect my design more, the device or the design software? No matter what the specs are on the device if the design software had short comings, flaws or limited what I could do with the device, the target device no longer mattered as much. Searching this group I found users having problems installing and maintaing their development environment. Xilinx tech support seemed to help them find a solution but in the process how do you get back the time that you spent fixing your environment - some of these engineers had spent 1 -3 days fixing their environment. Going back to something my grandfather taught me, "Don't fix something that isn't broken." In the software world is if you have a working environment and the software vendor comes out with a new release don't upgrade unless there is a feature that you can't live without. Let the people who need the new features get burned by the new releases. Wait 2 -3 months for fixes and services packs come out to fix issues with a new release. Some of this is just plain common sense but find people today ignore the obvious. Derek
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