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Messages from 80475

Article: 80475
Subject: Re: Newby Getting started with FPGA
From: "Hendra" <u1000393@email.sjsu.edu>
Date: 6 Mar 2005 15:59:12 -0800
Links: << >>  << T >>  << A >>
Kryten wrote:
> If I were to make a project with LEDs and switches I would want to
have them
> mounted where I want and in my choice of colours, not fixed on the
FPGA
> board itself. The less pins the FPGA decides to use, the more freedom
I have
> to use them.

That's a very good point, Kryten! I am very dissapointed with the board
layout of Digilent S3 starter kit. Its board layout should have been
the same with their D2SB and D2FT board. D2SB and D2FT are bare bone
FPGA boards. They offer an extension board that has LEDs, Switches and
Buttons but since they can be plug in and plug out at will, no I/O pins
have been hardwired to the extension board. On the other hand, the
Digilent S3 starter kit has 32 I/O pins hardwired already to the
onboard switches, LEDs and buttons. Those 32 I/O pins are not available
for any other purposes.

Hendra


Article: 80476
Subject: Re: Newby Getting started with FPGA
From: "Kryten" <kryten_droid_obfusticator@ntlworld.com>
Date: Mon, 07 Mar 2005 01:27:32 GMT
Links: << >>  << T >>  << A >>

"Hendra" <u1000393@email.sjsu.edu> wrote in message 
news:1110153552.755274.22750@l41g2000cwc.googlegroups.com...

> That's a very good point, Kryten! I am very disappointed with the board
> layout of Digilent S3 starter kit. Its board layout should have been
> the same with their D2SB and D2FT board. D2SB and D2FT are bare bone
> FPGA boards.

Yes, the whole point of buying an FPGA board is because you have your own 
purposes for those pins.

But there's always some pointy haired sales droid who wants more features.


I never thought I'd object to something having more stuff for less than half 
the price of a competing product, but I can't help suspecting some 
unconventional business ethics here.
I'd expect the Digilent board to cost at least three times its price, given 
that it has more bits than the > 210 USD BurchEd board. from typical 
mark-ups (3x), I'd say the board was being sold at cost price. In which 
case, who is paying the production costs?

It is okay for Xilinx to give away software only they produce, but if they 
are paying Digilent to sell boards at cost then it is an underhand blow to 
the other manufacturers of Xilinx dev kits. Surely that would put them out 
of business eventually. Maybe Xilinx want to reduce the number of players to 
just their own favourite?





Article: 80477
Subject: VoIP & FPGA
From: "Leo" <linuxdock@gmail.com>
Date: 6 Mar 2005 18:55:26 -0800
Links: << >>  << T >>  << A >>
Hi guys,

Just a dummy level question. Is it possible to implement a VoIP
solution with the Xilinx SP3 kit? If not is there a better FPGA
solution for it? Thanks!

Leo


Article: 80478
Subject: Re: DCT in FPGA
From: "Pete Fraser" <pfraser@covad.net>
Date: Sun, 6 Mar 2005 19:19:57 -0800
Links: << >>  << T >>  << A >>

<DerekSimmons@FrontierNet.net> wrote in message 
news:1110135080.825209.182220@o13g2000cwo.googlegroups.com...
>
> Wojtek wrote:
>> Discret cosinus transform algorithms in FPGA.

> Did you check out http://www.opencores.org? Quick look I found:
>
> Video Compress:
> http://www.opencores.org/projects.cgi/web/video_systems/overview
>
> JPEG Hardware Compressor
> http://www.opencores.org/projects.cgi/web/jpeg/overview
>
Also check out Xilinx app notes. 



Article: 80479
Subject: Re: Newby Getting started with FPGA
From: Mike Harrison <mike@whitewing.co.uk>
Date: Mon, 07 Mar 2005 09:28:33 GMT
Links: << >>  << T >>  << A >>
On Mon, 07 Mar 2005 01:27:32 GMT, "Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote:

>
>"Hendra" <u1000393@email.sjsu.edu> wrote in message 
>news:1110153552.755274.22750@l41g2000cwc.googlegroups.com...
>
>> That's a very good point, Kryten! I am very disappointed with the board
>> layout of Digilent S3 starter kit. Its board layout should have been
>> the same with their D2SB and D2FT board. D2SB and D2FT are bare bone
>> FPGA boards.
>
>Yes, the whole point of buying an FPGA board is because you have your own 
>purposes for those pins.
>
>But there's always some pointy haired sales droid who wants more features.
>
Nobody ever got fired for putting more flashing LEDs on aproduct....!


Article: 80480
Subject: Re: Newby Getting started with FPGA
From: Mike Harrison <mike@whitewing.co.uk>
Date: Mon, 07 Mar 2005 09:33:10 GMT
Links: << >>  << T >>  << A >>

>I never thought I'd object to something having more stuff for less than half 
>the price of a competing product, but I can't help suspecting some 
>unconventional business ethics here.
>I'd expect the Digilent board to cost at least three times its price, given 
>that it has more bits than the > 210 USD BurchEd board. from typical 
>mark-ups (3x), I'd say the board was being sold at cost price. In which 
>case, who is paying the production costs?
>
>It is okay for Xilinx to give away software only they produce, but if they 
>are paying Digilent to sell boards at cost then it is an underhand blow to 
>the other manufacturers of Xilinx dev kits. Surely that would put them out 
>of business eventually. Maybe Xilinx want to reduce the number of players to 
>just their own favourite?

Xilinx want to sell chips. Getting cheap devkits available helps this, whether they make them
themselves or fund third parties to do it makes little difference - I can't see how this is any way
underhand.. 
In practice, third parties can often do a better job as they are typically smaller companies more in
touch with the needs of lower-end users, and are more geared up to manufacturing than chip making
companies.
Any third party making devkits independendtly of the manufacturer knows that there is always a risk
of the manufacturer undercutting them when they decide to do a sales push/promotion etc. Any company
whos survival depends on selling devkits for a single chip manufacturer's product is on shaky ground
unless they have a very good relationship with the manufacturer. 
 


Article: 80481
Subject: Re: Help with 22v10 and WinCupl :(
From: Mike Harrison <mike@whitewing.co.uk>
Date: Mon, 07 Mar 2005 09:39:14 GMT
Links: << >>  << T >>  << A >>
On Sun, 6 Mar 2005 22:48:36 -0000, "Stephen Lannard" <s.l@nospamplease.com> wrote:

>
>>>>>I'm new to this and maybe i'm expecting too much of the 22v10.
>>
>> The 22V10 is at the bottom end of the scale, only the 16V8
>> is below it ....
>
>I chose the 22v10 because it was a basic unit, I hoped to learn on this 
>before embarking upon anything of note.
>I'm basically trying to replace a timing pulse and a bunch of ttl logic as 
>my first step into PLD.
>
>> Easier, but not as precise.
>> You could also look at the ATF750, which is pin-pin with the 22V10, but 
>> has 20 Macrocells, and if physical details are not nailed down, the 32 
>> Macrocell devices like ATF1502ASL et al...
>
>If I manage to work out this CUPL those chips will be added to my list of 
>things to play with :-)
>It's proving a little difficult at the moment to grasp the language.

Before trying to grasp the language, be sure you understand the chip as the two are intimately
linked.

The basic approach is to decide how each macrocell is to be used, and write an equation describing
the functionality you need for each one. 
Remember it is a hardware description language, NOT a programming language.
Start with one of the example files, breadboard a device and get it working as-is, then start
tweaking it slightly to get a feel for how it all works.
 CUPL is not a difficult system to use once you understand the underlying hardware and what you are
trying to do with it. 
 

Article: 80482
Subject: Re: adding SDRAM to the S3 starter kit
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Mon, 07 Mar 2005 10:41:13 +0100
Links: << >>  << T >>  << A >>

>>
>> NuHorizons HW-AFX-SP3-400-DB ($199)
>> http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html
>> XC3S400, 64Mbits SDRAM
>>
>> XESS XSA-3S1000 ($199)
>> http://www.xess.com/prod035.php3
>> XC3S1000, 32Mbyte SDRAM
>>
>> Memec Design  Spartan-3MB ($795)
>> http://www.memec.com/?cmd=detail&articleid=1479
>> XC3S1500, 16Mx16 DDR SDRAM
> 
> 
> I've been looking - the problem is that all of them seem to use a 16-bit 
> interface to memory, and while I could write an interface that fetched 2 
> words before returning it to the microblaze (use burst mode, hold of RDY 
> until both returned, done), it wouldn't model what I ultimately want, 
> and of course it'd be slower :-(

Take a board that uses 16bits DDR like the Memec one. In one clock cycle, you
have 32bits. Or clock your SDRAM twice as fast (66Mhz Microblaze and 133Mhz SDRAM).
Any way on a S3 you can't clock the Microblaze up to the frequency supported by your
SDRAM. Even running it a 87Mhz seems in the high limit.


Also, why write the interface ? You could use one of the EDK. I know the one for
DDR (opb_ddr) is part of EDK.



	Sylvain

Article: 80483
Subject: Re: DCT in FPGA
From: "Thomas Gebauer" <th.gebauer@gmx.de>
Date: Mon, 7 Mar 2005 11:43:54 +0100
Links: << >>  << T >>  << A >>
The DCT from opencores.org are not that ideal for FPGAs because they uses
too much resources (64 multipliers) but they are extremly fast (one DCT per
clock).
The one described in Xilinx XAPP611 is great if you have build in
multipliers.
I have implemented a bit serail approach based on distributed arithmetics as
described in
http://www-li5.ti.uni-mannheim.de/publications/ElectronicPublications/lienhart01.pdf .
It is quite slow (about 500 clocks per IDCT) but utilises mainly LUTs. With
a little bit faster FPGA device you can achive the count of IDCTs per second
you need for PAL resolution (720 x 576 x 25).

Regards Thomas


"Pete Fraser" <pfraser@covad.net> wrote in message
news:112ni2npl8haod9@news.supernews.com...
>
> <DerekSimmons@FrontierNet.net> wrote in message
> news:1110135080.825209.182220@o13g2000cwo.googlegroups.com...
> >
> > Wojtek wrote:
> >> Discret cosinus transform algorithms in FPGA.
>
> > Did you check out http://www.opencores.org? Quick look I found:
> >
> > Video Compress:
> > http://www.opencores.org/projects.cgi/web/video_systems/overview
> >
> > JPEG Hardware Compressor
> > http://www.opencores.org/projects.cgi/web/jpeg/overview
> >
> Also check out Xilinx app notes.
>
>



Article: 80484
Subject: Re: EST Guide
From: Marco <>
Date: Mon, 7 Mar 2005 03:16:24 -0800
Links: << >>  << T >>  << A >>
yes, it is.

Many Thanks Marco

Article: 80485
Subject: Cheap alternatives to Mach 210s
From: "Fred" <Fred@nospam.com>
Date: Mon, 7 Mar 2005 12:08:20 -0000
Links: << >>  << T >>  << A >>
I have an old board I'm updating which has 2 of these.  I need a similar 
device to revamp the board and give it a new life.

Can anyone suggest an affordable replacement?

Cost is the principle issue.




Article: 80486
Subject: Re: Cheap alternatives to Mach 210s
From: Luc <lb.edc@pandora.be>
Date: Mon, 07 Mar 2005 13:47:23 +0100
Links: << >>  << T >>  << A >>
Depending on the voltages you want to use (Mach210 is a 5V device).
You could use the M4A5-32/32 which has a very similar spec and
architecture (I once did the excercise). If you want to drive the cost
further down and have 3.3V on the PCB you could use the LC4032V
(superset of the M4A5). The device is 5V tolerant.
You will need to work with your locl disti or direct Lattice sales
channel for pricing.

Regards,

Luc

On Mon, 7 Mar 2005 12:08:20 -0000, "Fred" <Fred@nospam.com> wrote:

>I have an old board I'm updating which has 2 of these.  I need a similar 
>device to revamp the board and give it a new life.
>
>Can anyone suggest an affordable replacement?
>
>Cost is the principle issue.
>
>


Article: 80487
Subject: Re: VoIP & FPGA
From: "Marc Randolph" <mrand@my-deja.com>
Date: 7 Mar 2005 05:36:44 -0800
Links: << >>  << T >>  << A >>

Leo wrote:
> Hi guys,
>
> Just a dummy level question. Is it possible to implement a VoIP
> solution with the Xilinx SP3 kit? If not is there a better FPGA
> solution for it? Thanks!

Howdy Leo,

   Not knowing what you consider a "solution" to be, it's difficult to
answer your question.  Stuff like if it needs to be a real-time demo,
the number of VoIP channels, where the audio will come from and go to,
etc.

The Xilinx S3 kit doesn't seem to have A/D or D/A converters, so you'd
have to do that elsewhere (your computer?).  Amazingly, even in this
Internet age, it also doesn't look like it has an Ethernet phy, which
in my mind, would mostly rule it out for your application if your
intent is real-time.  There are plenty of other FPGA demo boards (from
third parties) which have both A/D, D/A, and Ethernet ports.  Might not
be quite as inexpensive, but shouldn't break the bank either.

Once you figure out how to get the voice in and out of the FPGA, the
actual VoIP encoding should be a piece of cake to do in *any* FPGA.
Well, I suppose it could vary from a piece of bunt cake to a whole
wedding cake, depending on which encoding standard(s) you want to
support and your experience with them.

Have fun,

   Marc


Article: 80488
Subject: Re: Cheap alternatives to Mach 210s
From: "Fred" <Fred@nospam.com>
Date: Mon, 7 Mar 2005 13:55:27 -0000
Links: << >>  << T >>  << A >>
Many thanks for your reply.

It's not essential I use the Lattice devices although it is an obvious 
migration.  Some time ago there was talk of an equivalent Cypress part.  It 
doesn't have to be a direct equivalent.  I need 64 macrocells and around 36 
I/Os.  One device of twice the macrocells and I/Os is a possibility but 
these have historically cost more than 2 x the cost of a single smaller 
device.  I just wanted a feel for what's around.

Many thanks again.



"Luc" <lb.edc@pandora.be> wrote in message 
news:72jo215iclnr3e4i4hrvqeu7n3dvf6tklc@4ax.com...
> Depending on the voltages you want to use (Mach210 is a 5V device).
> You could use the M4A5-32/32 which has a very similar spec and
> architecture (I once did the excercise). If you want to drive the cost
> further down and have 3.3V on the PCB you could use the LC4032V
> (superset of the M4A5). The device is 5V tolerant.
> You will need to work with your locl disti or direct Lattice sales
> channel for pricing.
>
> Regards,
>
> Luc
>
> On Mon, 7 Mar 2005 12:08:20 -0000, "Fred" <Fred@nospam.com> wrote:
>
>>I have an old board I'm updating which has 2 of these.  I need a similar
>>device to revamp the board and give it a new life.
>>
>>Can anyone suggest an affordable replacement?
>>
>>Cost is the principle issue.
>>
>>
> 



Article: 80489
Subject: Readback
From: "VSR" <vijaysai@gmail.com>
Date: 7 Mar 2005 06:59:31 -0800
Links: << >>  << T >>  << A >>
How to read back a configuration? I am using a Xess-50 board with
Sparatan2 on it. Please refer to any good tutorial on readback, if
possible. 
Thanks, 
Vijay


Article: 80490
Subject: Xilinx / Altera TCLK termination (Pull up or down)
From: lecroy7200@chek.com
Date: 7 Mar 2005 07:11:57 -0800
Links: << >>  << T >>  << A >>
To enter JTAG, the TCLK pin is sampled on the rising edge.  With Altera
devices, the TCLK pin is pulled low and the other JTAG pins are pulled
high to prevent sampling of the clock.  Looking at XAPP501 and others
it appears Xilinx is using a pull-up.  This would seem to be a possible
source for problems.  Is this really what Xilinx is wanting, or is
there a problem with their documentation?

Thanks


Article: 80491
Subject: Re: XST block ram init in include files
From: "Gabor" <gabor@alacron.com>
Date: 7 Mar 2005 07:35:18 -0800
Links: << >>  << T >>  << A >>

Arlet wrote:
> hi,
>
> I'm having trouble initializing some memory in a verilog include
file.
> If I do the following :
>
> BRAM16_S9 memory ( ... );
> // synthesis attribute init_00 of memory is "...."
>
> Everything works fine.
>
> However, I really want to have the memory initialization done in an
> include file (because it is generated), like such:
>
> BRAM16_S9 memory ( ... );
> `include "init.v"
>
> (with the init.v file containing the // synthesis attribute ...).
>
> But then I get an error from XST:
>
> Cannot find <memory> in module <Unknown Module>
>
> Is there a way to make this work ?
>
> Arlet

Did you try to put the memory instantiation in the include file?  I
am assuming it won't change from build to build so you could just
think of it as a header to the generated file.  The tools should
be able to deal with this if the memory and its initialization are
in the same file (but I haven't tried it myself).


Article: 80492
Subject: Re: state encoding in FSM for simple cases ?
From: "Arash Salarian" <arash.salarian@epfl.ch>
Date: Mon, 7 Mar 2005 17:06:21 +0100
Links: << >>  << T >>  << A >>
While I agree that theoretically state assignment is a tough problem, yet in 
practice an FPGA designer rarely would need to get involved and can safely 
leave it to the synthesize tool. For small designs it does not really matter 
and for large/critical designs, better synthesize tools like Synplify give 
you the freedom to choose between several possible state assignment 
algorithms and the designer can SEE the quality of the output (in terms of 
the used resources/speed) and decide upon it (Synpfily Pro even tries to do 
this automatically).
I think "generally" it is a bad idea for a designer to try to do the 
state-assignment by hand and would recommend using symbolic names for the 
states and let the synthesize tool do the "dirty" job. Why? First, this is a 
difficult job and for large state-machines can easily get tedious and 
potentially produce bugs. Also, what if you want to port your VHDL code from 
say, Altera to Xilinx or even ASIC? Optimal state assignment can be 
different on different architectures. However, the problem itself is very 
interesting and very IMPORTANT for the synthesize tool designers...

Regards
Arash

"Michel Billaud" <billaud@labri.u-bordeaux.fr> wrote in message 
news:7zekeupgbe.fsf@serveur5.labri.fr...
>
> Hi, I'm discovering the wonderful world of FPGA, so please excuse the
> probably stupid question and use of improper terminology.
>
> It seems to be a trivial case of the difficult "state assignment
> problem" but i must admit i'm to lazy to read the 199 pages of
> http://alexandria.tue.nl/extra2/200413270.pdf now :-/)
>
> There are 2 very simple situations in FSM
> 1. n-step cycle   S1 -> S2 ->  Sn -> S1 -> S2 -> ....
> 2. n-step, last is a sink : S1 -> S2 -> Sn -> Sn -> Sn -> Sn ...
> that can be easily implemented with counters, binary, gray code,
> whatever.
>
> The question is: what's your favorite representation when you
> have strong restrictions on the number of gates/FF ?
>
> I guess everybody uses a standard binary counter for large values,
> say N>1000) with initial state = 0 and last = N-1, or the other way,
> but are there "good practices" for small ones ?
>
> Michel Billaud
>
> -- 
> Michel BILLAUD                  billaud@labri.fr
> LABRI-Université Bordeaux I     tel 05 4000 6922 / 05 5684 5792
> 351, cours de la Libération     http://www.labri.fr/~billaud
> 33405 Talence  (FRANCE) 



Article: 80493
Subject: Asynchronous processor !?!
From: "Peter Sommerfeld" <psommerfeld@gmail.com>
Date: 7 Mar 2005 08:18:54 -0800
Links: << >>  << T >>  << A >>
I was amazed by this press release:

http://www.epson.co.jp/e/newsroom/2005/news_2005_02_09.htm

Apparently the asynchronous design uses 70% less power compared to its
synchronous counterpart.

What do you think they mean by an asynchronous processor? I find it
hard to believe the majority of the circuitry (pipeline, etc) is
asynchronous.

Will asynch design ever be feasible in FPGAs? I suppose it would
require a new tool chain and new ways of thinking, but having never
done it, I have no idea.

Just something that's got me really curious.

-- Pete


Article: 80494
Subject: Re: Spartan 3 - insurge current
From: "paul" <paul_sereno@hotmail.com>
Date: 7 Mar 2005 08:36:42 -0800
Links: << >>  << T >>  << A >>

Steven K. Knapp wrote:
> "paul" <paul_sereno@hotmail.com> wrote in message
> news:1110062577.195830.218960@o13g2000cwo.googlegroups.com...
> >
> > Any of you has concrete numbers of the insurge current for the
> > XC3S1000? how long does it take to go through the high current
period?
> >
> > I'll appreciate any feedback.
>
> Any of the more modern Xilinx architectures (Virtex-II, Virtex-II
Pro,
> Spartan-3/-3E) do not have a power-on surge current requirement in
order to
> power on the FPGA.  The current requirements are essentially the same
as the
> maximum quiescent requirements listed in the data sheet.
>
> For example, the XC3S1000 limits are described in Table 7, page 5 of
the
> following document.
> http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
>
> ---------------------------------
> Steven K. Knapp
> Applications Manager, Xilinx Inc.
> General Products Division
> Spartan-3/-3E FPGAs
> http://www.xilinx.com/spartan3e
> ---------------------------------
> The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.


Pet, Steve,
              Thanks for your quick response. I really appreciate it.

Paul


Article: 80495
Subject: Re: Cheap alternatives to Mach 210s
From: "M.Randelzhofer" <techseller@gmx.de>
Date: Mon, 7 Mar 2005 17:48:36 +0100
Links: << >>  << T >>  << A >>
"Fred" <Fred@nospam.com> schrieb im Newsbeitrag
news:422c4449$0$8754$db0fefd9@news.zen.co.uk...
> I have an old board I'm updating which has 2 of these.  I need a similar
> device to revamp the board and give it a new life.
>
> Can anyone suggest an affordable replacement?
>
> Cost is the principle issue.
>
>
>

Xilinx XC9572XL is the best choice for cost and logic density.
It is in system programmable.
However it needs a 3.3V supply voltage, and has only 34 I/O's availlable in
a 44pin package, so use a VQ64 package:
http://direct.xilinx.com/bvdocs/publications/ds057.pdf


MIKE



Article: 80496
Subject: Re: DCT in FPGA
From: "Wojtek" <woytecc@poczta.fm>
Date: Mon, 7 Mar 2005 18:14:02 +0100
Links: << >>  << T >>  << A >>
Thanks, but i need source code (my mistake) of DCT/IDCT algorithm in VHDL
language. This is for my engineer project in High School (sorry for my
english:)

Regards


Użytkownik "Thomas Gebauer" <th.gebauer@gmx.de> napisał w wiadomości
news:d0hb9c$cri$1@news.mch.sbs.de...
> The DCT from opencores.org are not that ideal for FPGAs because they uses
> too much resources (64 multipliers) but they are extremly fast (one DCT
per
> clock).
> The one described in Xilinx XAPP611 is great if you have build in
> multipliers.
> I have implemented a bit serail approach based on distributed arithmetics
as
> described in
>
http://www-li5.ti.uni-mannheim.de/publications/ElectronicPublications/lienha
rt01.pdf .
> It is quite slow (about 500 clocks per IDCT) but utilises mainly LUTs.
With
> a little bit faster FPGA device you can achive the count of IDCTs per
second
> you need for PAL resolution (720 x 576 x 25).
>
> Regards Thomas
>
>
> "Pete Fraser" <pfraser@covad.net> wrote in message
> news:112ni2npl8haod9@news.supernews.com...
> >
> > <DerekSimmons@FrontierNet.net> wrote in message
> > news:1110135080.825209.182220@o13g2000cwo.googlegroups.com...
> > >
> > > Wojtek wrote:
> > >> Discret cosinus transform algorithms in FPGA.
> >
> > > Did you check out http://www.opencores.org? Quick look I found:
> > >
> > > Video Compress:
> > > http://www.opencores.org/projects.cgi/web/video_systems/overview
> > >
> > > JPEG Hardware Compressor
> > > http://www.opencores.org/projects.cgi/web/jpeg/overview
> > >
> > Also check out Xilinx app notes.
> >
> >
>
>



Article: 80497
Subject: Re: adding SDRAM to the S3 starter kit
From: google@gornall.net
Date: 7 Mar 2005 09:18:12 -0800
Links: << >>  << T >>  << A >>
It had occurred to me to clock the microblaze at 'only' 66 MHz, and
clock-double the SRAM. That would probably be fine, in fact, but it
seemed a bit of a waste to "lose" 20MHz of CPU frequency. The 87 MHz
comes from their selection options, nothing more - I don't actually
know if it really runs that fast, but they do claim 85 (I think) in
their literature for the S3.

I wasn't actually aware about the supplied DDR IP - The kit only
arrived on Saturday [grin]. If it's there and it works, then that's
probably the way I'll go. I didn't really fancy trying to make the S3
do fast DDR access - from what I've read you need to play tricks that
are under NDA in order to get it to work.

Cheers,

Simon


Article: 80498
Subject: Re: Xilinx / Altera TCLK termination (Pull up or down)
From: "Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com>
Date: Mon, 07 Mar 2005 18:39:02 +0100
Links: << >>  << T >>  << A >>
lecroy7200@chek.com wrote:
> To enter JTAG, the TCLK pin is sampled on the rising edge.  With Altera
> devices, the TCLK pin is pulled low and the other JTAG pins are pulled
> high to prevent sampling of the clock.  Looking at XAPP501 and others
> it appears Xilinx is using a pull-up.  This would seem to be a possible
> source for problems.  Is this really what Xilinx is wanting, or is
> there a problem with their documentation?
> 
> Thanks
> 


Hi, both pull-up or pull-down will be OK. The goal is to prevent an 
undefined (floating) level on TCK pin.

The difference between the use of pull-up or pull-down will be on the 
power-on of the target board.

Using a pull-up, you will generate a max 1 clk.
Anyway, this 1 clk will not be able to do something wrong in the JTAG 
TAP controller of any device.

Anyway, when starting an JTAG communication (for debug or boundary 
scan), the first thing you will do is to do a soft-reset of the JTAG TAP 
by driving 5 clk with tms '1'.

Regards,
Laurent Gauch
www.amontec.com
___________________________
Unlocking the power of JTAG




Article: 80499
Subject: Re: Asynchronous processor !?!
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 07 Mar 2005 09:55:27 -0800
Links: << >>  << T >>  << A >>
Peter Sommerfeld wrote:

> I was amazed by this press release:

> http://www.epson.co.jp/e/newsroom/2005/news_2005_02_09.htm

> Apparently the asynchronous design uses 70% less power compared to its
> synchronous counterpart.

> What do you think they mean by an asynchronous processor? I find it
> hard to believe the majority of the circuitry (pipeline, etc) is
> asynchronous.

I believe it is also known as "self-timed logic", and much 
easier to search for using that name.

-- glen




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