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Messages from 20400

Article: 20400
Subject: Re: Spartan II availability and pricing
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 08 Feb 2000 16:55:13 -0800
Links: << >>  << T >>  << A >>


Larry Doolittle wrote:

> I'm not sure you can define and differentiate "consumer", "industrial",
> and "telecom" in a way that holds water in the age of networked markets.
> Especially since "consumer" technologies have to be developed and tested
> in small quantities on a real life workbench, just like everything else.
>

We were debating pricing philophies.
During development and debugging, the difference between $40 and $10 per chip
should really be irrelevant. Salaries dominate. What really matters is the
projected high-volume price and availability, when you need the parts sometime
in the future.

If you don't like my words "consumer", substitute it with "price-sensitive
high-volume" market ( as opposed to more performance-oriented modest-volume
industrial and telecom market ).

Now please let me get out of marketing talk back into engineering, where I am
more at home, and what I am being paid for.

Peter Alfke

Article: 20401
Subject: Re: ADC to DSP... FIFO?
From: rk <stellare@nospam.erols.com>
Date: Tue, 08 Feb 2000 20:20:11 -0500
Links: << >>  << T >>  << A >>
Paul Butler wrote:

> rk <stellare@nospam.erols.com> wrote in message
> news:389FA8ED.775E5513@nospam.erols.com...
> > Another case that I've seen, when analyzing a failed design, is when a
> piece of
> > CAE code took a flip-flop and an inverter and converted it into two
> flip-flops,
> > one with a complemented output.  The two flip-flops wound up in an
> "inconsistent
> > state" and since the outputs were controlling some high current switches
> in a
> > motor, well, BOOM!  While originally mis-diagnosed as a failed FPGA - how
> can a
> > flip-flop output and it's inversion be the same value? - it turned out the
> > designer was not aware of how the CAE software helped him out.
>
> Yikes!  Can you tell us more?  What CAE software did this?

Well, this same software also had an asynchronous input going into two
flip-flops, where only one was originally intended.  This, too, was hidden
behind the software.  Not good for the metastable state thingie.  To paraphrase
the expression, "Don't quit your day job," I shall say, "Don't toss out your
schematic capture license and dongle."

I don't think it's terribly important whose software did the deed.  CAE design
software is not specified (i.e., there is no specification that tells you what
comes out for what goes in) and not under any soft of configuration control.
With each rev, perhaps a monthly or quarterly release, you can get all new
algorithms.  One designer got burned, as we found in a design review, when he
updated his synthesizer and was building his chip in blocks.  Same product, just
a new revision.  However, he used a Boolean signal in the interface and the
different versions of the synthesizer defined True and False differently and was
not compatible with itself.  Both were legal VHDL.

Back to the original problem, the standard method of verification of black box
testing with a test bench will not pick up the fact that the CAE tool designed a
LOUSY circuit.  If this happenned in the "field," it would have been very very
expensive and embarrassing.

=======================================

> If the synthesizer duplicates a synchronizing FF, any FSM controlled by that
> synchronizer could occasionally sense conflicting signals from those FFs and
> end up in a bad state.  If you can advise the rest of us on how to avoid
> that problem, we'd appreciate it.

Yeah, like I said up above (probably should read the whole thing before I babble
on).  The main point is, which I tried to make earlier, was that you can not
look at an ASCII VHDL file and say you understand the circuitry.  It may or may
not be a good circuit.  For evaluation purposes, I took a simple two-phase,
non-overlapping clock generator and ran it through many synthesizers, some
synthesizers with different settings.  I got a large range of different answers
(used schematic generator to view them from EDIF netlist).  Even more
interesting, was running the same VHDL again through the same synthesizers,
about a year later, with updated software; the behaviour for some of them
changed radically.

I shall note that one manufacturer is implementing a "safe" mode for state
machine, as the "others" clause doesn't cover all physical states, just the
logically defined ones in the VHDL domain (i.e., that's a fancy way of saying
it's easy to get screwed with one-hot encoding).  For binary encoded machines,
even if you have a number of states that is an integral power of 2 and have
transitions defined for all of the states, you can still get screwed, as some
optimizers will declare the states "unreachable" and then optimze them out.  For
that, you need an input to force the FSM to have transitions through each state
(and I suggest having an output two, so the f-f's don't get vaporized on you for
not having any effect on the output; this was the case that our good friend
Rickman saw in FPGA express; I haven't used that one, but I have previously seen
this happen in other software).

Obviously, there are other methods, too, but it is a bit late and not sure how
many people are interested in this babble.  Most people I know ignore the lockup
set of states problem.  A PC mentality, just hit the little red button on the
front of the machine. :-)

Have a good evening,

----------------------------------------------------------------------
rk                               The world of space holds vast promise
stellar engineering, ltd.        for the service of man, and it is a
stellare@erols.com.NOSPAM        world we have only begun to explore.
Hi-Rel Digital Systems Design    -- James E. Webb, 1968

Article: 20402
Subject: Re: XC3000 series w/Foundation Student Edition?
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 8 Feb 2000 18:43:27 -0700
Links: << >>  << T >>  << A >>
Ewan D. Milne wrote in message <87prpd$h9d$1@sunfish.hi.com>...
>Hello all...
>
>I've been working with the Foundation Student Edition for
>a while now, and it's pretty good for what I want to do.
>However, I have an old design I did on paper a couple of
>years ago for an XC3030 device that I'd like to actually
>implement.  The problem is that the Student Edition
>software doesn't appear to contain support for the older
>devices.
>
>Is there any way to implement my design in this older
>family without purchasing the entire full-blown Foundation
>package?  Did Xilinx deliberately leave out support for
>the older families from the Student Edition in order to
>discourage their use?

Sorry, the full-blown version of the new tools doesn't support the old
chips, either.  They left the old chips out because they don't want anyone
using them for new designs.  Which is a reasonable thing to want.

>I could implement it in an XC4003, but last I checked,
>that part was not offered in the 44pin PLCC package.
>In fact, none of the XC4000 series parts were.


Why not look at something in the 84-pin PLCC?  Maybe one of the CPLDs will
fit the bill.  Were you using all of the 3030?

>Would there be any chance of an older version of XACT
>being available somewhere?  (Assuming the dongle would
>still work after all these years...)


We're keeping ours because we have some old parts to support, too.  Sorry.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

Spelling Counts!  You don't loose your money - you lose it.



Article: 20403
Subject: Re: ADC to DSP... FIFO?
From: murray@pa.dec.com (Hal Murray)
Date: 9 Feb 2000 02:52:47 GMT
Links: << >>  << T >>  << A >>

> ...Or when you use a device that is not fully supported by schematic entry (Virtex
> comes to mind), or when a customer (US Gov't for example) requires VHDL?

Anybody make a schematic to VHDL conversion tool?

Reminds me of the old automatic flowchart programs.  [For the
youngster who don't remember that far back, there was
a small industry back in the 60s that would take your program
and print a pretty flow chart on a line printer.  A big program
would make a big pile of paper.  Of course, it wasn't good for
anything except checking the flow-chart box on the contract.]

-- 
These are my opinions, not necessarily my employers.
Article: 20404
Subject: Re: ADC to DSP... FIFO?
From: rk <stellare@nospam.erols.com>
Date: Tue, 08 Feb 2000 22:00:06 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote:

> > ...Or when you use a device that is not fully supported by schematic entry (Virtex
> > comes to mind), or when a customer (US Gov't for example) requires VHDL?
>
> Anybody make a schematic to VHDL conversion tool?

I know that Viewlogic has one.  I used this as a data entry method for Gatefield FPGAs.

===================================

> Reminds me of the old automatic flowchart programs.  [For the
> youngster who don't remember that far back, there was
> a small industry back in the 60s that would take your program
> and print a pretty flow chart on a line printer.  A big program
> would make a big pile of paper.  Of course, it wasn't good for
> anything except checking the flow-chart box on the contract.]

I believe that about 8-10 years ago, when "CASE" was the big buzzword, they had software
programs that would injest application programs and spit out MIL-SPEC,
contract-compatible documentation.

rk

Article: 20405
Subject: Re: Xilinx "WebCD" gripes
From: "Domagoj" <abednego@africamail.com>
Date: Wed, 9 Feb 2000 04:40:31 +0100
Links: << >>  << T >>  << A >>
Hi,

   Have you tried to take Applinx cd out without
closing netscape, and then close netscape? Try it.
I also don't understand 'Cd has expired'. How?
The critic about bad organization on disk stays.
They've put so much junk on it. But search option is
great. You can find exactly what you're looking
for among all that junk (in most cases).
    About DLLs, there's also a havy weapon to
combat this evil: Cleansweep (Symantec), It has
saved so many hours of unnecessary searching after
unwanted DLLs and registry entries. 5 exe, 3 DLL
files and 1 registry entry (WebCD) is a piece of
cake for Cleansweep. But, I hate when I must install
something unnecessary.
    I also don't like Xilinx alliance 1.5i Dyna text
- it's horrible. Printing just a part of text is
mission impossible. Has anything changed in 2.1i?

----------------
=  Domagoj   =
----------------




Article: 20406
Subject: Re: Xilinx "WebCD" gripes
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Tue, 8 Feb 2000 20:37:18 -0800
Links: << >>  << T >>  << A >>
Domagoj <abednego@africamail.com> wrote in message
news:87qnq9$sah$1@bagan.srce.hr...
>     I also don't like Xilinx alliance 1.5i Dyna text
> - it's horrible. Printing just a part of text is
> mission impossible. Has anything changed in 2.1i?

Yes!  It's all HTML (plus Java-related stuff) in 2.1i.  It's much better;
the files are much small.  About the only complaint I have is that it takes
slightly longer to load at first (get the JIT comper loaded or something?).
Searching is much faster, however.

Note that Inso, the guys who put out Dynatext, also wrote Quick View, which
is bundled in with all current Microsquish operating systems.  Like
Dynatext, it gets the job done, but they definitely didn't win any awards
for innovative programming.

---Joel Kolstad



Article: 20407
Subject: Re: Why does Virtex has no EPROM support like XC4000
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Tue, 8 Feb 2000 20:46:32 -0800
Links: << >>  << T >>  << A >>
Kai Troester <troester@imms.de> wrote in message
news:389EDCE2.42873A06@imms.de...
> Maybe someone asked this question before. but i don't understand why the
> designers of the Virtex family did not include the possibility to
> download from an EPROM without an additional PLD. The XC4000 family had
> this feature and I liked it very much. Does Xilinx has to much low
> density pld and want to ship with every virtex one of these. But I think
> a lot of Virtex users will take an Altera for this job. Or is there a
> more lucid explanation ?

I find it interesting that every single board I've ever seen with a Virtex
part that used power-on time parallel configuration (e.g., the Nallatech
board -- I've only seen about 2 or 3 besides this) uses a flash ROM plus a
CPLD.  I was going to argue that you needed the CPLD to re-program the flash
ROM anyway, but in retrospect I can't see why you don't just let the Virtex
part re-program its own flash ROM after booting (...and presumably configure
the FPGA via JTAG or some such the very first time out).

You're right, it is odd.  My only guess is that so few people used it on the
4K series (I'd bet it was at least 100:1 for serial mode configuration vs.
parallel mode configuration designs) that they didn't even think about
adding a master parallel mode.

---Joel Kolstad



Article: 20408
Subject: Re: Can hobbyist buy altera in uk?
From: Leon Heller <leon_heller@hotmail.com>
Date: Wed, 09 Feb 2000 08:25:03 GMT
Links: << >>  << T >>  << A >>
We use Altera devices where I work, and get them from Impact Memec
(01844 261188). You shouldn't have any problems getting small
quantities from them, I sometimes do this for components I need for
home use.


Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20409
Subject: Lattice isp programming problems
From: "Andrew Dow" <andrew.dow@gecm.com>
Date: Wed, 9 Feb 2000 08:30:41 -0000
Links: << >>  << T >>  << A >>
As anyone had any problems with in system programming of Lattice devices or
have any suggestion to the following problem.

I've started working on piece of hardware that hasn't been programmed during
the time I've been working on it. It decided I wanted to read the contents
out of the EPLD's I was working on and had got to the stage of putting the
download cable into the board and turning on the hardware. The power supply
immediately cut out and once the cable had been removed the system stopped
working.

I think the ispEN line has been damaged as it is sitting below 1V and
comparing to other boards in the system it should be at 3.5V approx.

I have been trying to work out how this could happen, as I do not want to
replace the chip for the whole thing to happen again.  I have the ground
differences  and they seem OK.

Any suggestions?

Andrew Dow


Article: 20410
Subject: Mapped design file
From: Steven Derrien <sderrien@irisa.fr>
Date: Wed, 09 Feb 2000 10:32:40 +0100
Links: << >>  << T >>  << A >>
Hello,

I'm using Foudation Express 2.1 with Virtex as target device and VHDL as
description language. I would like to retrieve a description in a human
redable format of my mapped design (i.e my circuit mapped to IOB,
Slices, DFF, etc ...) and placed design (same as previous but with
additionnal informations containg placement information)

Although the design flow engine produces some intermediate files, they
seems to be only partially readable (part of it is made of ascii text
(symbol name), but must information si encoded . Does anyone knows how
to extract info from these files ?

Thanks

Steven



Article: 20411
Subject: Re: Why does Virtex has no EPROM support like XC4000
From: Ray Andraka <randraka@ids.net>
Date: Wed, 09 Feb 2000 10:18:53 GMT
Links: << >>  << T >>  << A >>
The sync peripheral mode (slave parallel) on the 4025E's was actually broken for
quite a while before someone stumbled on it.  Apparently, I am one of the few
who used that mode.

Joel Kolstad wrote:

> Kai Troester <troester@imms.de> wrote in message
> news:389EDCE2.42873A06@imms.de...
> > Maybe someone asked this question before. but i don't understand why the
> > designers of the Virtex family did not include the possibility to
> > download from an EPROM without an additional PLD. The XC4000 family had
> > this feature and I liked it very much. Does Xilinx has to much low
> > density pld and want to ship with every virtex one of these. But I think
> > a lot of Virtex users will take an Altera for this job. Or is there a
> > more lucid explanation ?
>
> I find it interesting that every single board I've ever seen with a Virtex
> part that used power-on time parallel configuration (e.g., the Nallatech
> board -- I've only seen about 2 or 3 besides this) uses a flash ROM plus a
> CPLD.  I was going to argue that you needed the CPLD to re-program the flash
> ROM anyway, but in retrospect I can't see why you don't just let the Virtex
> part re-program its own flash ROM after booting (...and presumably configure
> the FPGA via JTAG or some such the very first time out).
>
> You're right, it is odd.  My only guess is that so few people used it on the
> 4K series (I'd bet it was at least 100:1 for serial mode configuration vs.
> parallel mode configuration designs) that they didn't even think about
> adding a master parallel mode.
>
> ---Joel Kolstad

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20412
Subject: Viterbi Dec. in VHDL (on Xilinx XC4000)
From: Marc Reinert <reinert@tu-harburg.de>
Date: Wed, 09 Feb 2000 13:52:23 +0100
Links: << >>  << T >>  << A >>
Has anybody experience with (or information about) implementing a
Viterbi Decoder into a Xilinx FPGA?

I'm going to develop a decoder to decode a variable convolutional code
(rate 1/2 or 1/3, Number of states min. 128 / better 256 or 512). I will
use a soft decision input (4 Bit quantisation). Optionally the decoder
shall compute a Soft Decision Output (SOVA). Very important is the
possibility of a high thourghput (>20 MBit/s).

I'm going to use Xilinx tools (VHDL in Foundation Express 2.1) and
Xilinx FPGA('s) (for example XC4062 XLA).

I'm thankful for any information about Viterbi Decoding on programable
logic  or for elements of VDHL-Code that implement parts of the decoder
like Add-Compare-Select-Unit, fast memory-management etc. .

Maybe anybody can help me! Thank U!

                              Marc

Article: 20413
Subject: Re: odd behavior of Virtex RAM Block model
From: <qwerty@scottfamily.cc>
Date: Wed, 09 Feb 2000 14:06:34 GMT
Links: << >>  << T >>  << A >>

I had the same issue- and simply set the simulation resolution to 
ns rather than ps.  For functional sim, the worked fine.


Ray Andraka <randraka@ids.net> wrote:
> Set the TimingChecksOn generic to "FALSE", that should suppress the
> checks.  I'm not sure why those are defaulted TRUE in the unisim
> library.  If you look at the vital source, you'll see that generic along
> with a whole list of timing generics.

> Arrigo Benedetti wrote:

>> Dear all,
>>
>> I was wondering if others have noticed any strange results from the
>> *functional* simulation of VHDL design using the Virtex SelectRAM
>> Block model from the UNISIM library (I'm using Synopsys). First,
>> I get warnings about setup time violations and I don't see why
>> since I'm doing a functional simulation:
>>
>> "*/RAMB4_S2_S4 HOLD  Low VIOLATION ON WEB WITH RESPECT TO CLKB;
>>   Expected := 0.01 NS; Observed := 0 NS; At : 146575.1 NS"
>> Assertion WARNING at 146575100 PS in design unit VITAL_TIMING from
>> process /BENCH/U1/U2/BRAM1/VITALBEHAVIOR:
>>
>> A quick fix of course is delaying the signal WEB with respect to
>> CLKB by 10ps with an after clause in the signal assignment,
>> but I should not get this worning at all I think.
>>
>> I also noticed that the DOA (port A outputs) go active as soon as ENA
>> goes from 0 to 1 instead of going active with the transition of
>> the clock from 0 to 1.
>>
>> Any ideas?
>>
>> Thanks in advance,
>>
>> -Arrigo
>> --
>> Dr. Arrigo Benedetti                e-mail: arrigo@vision.caltech.edu
>> Caltech, MS 136-93                              phone: (626) 395-3695
>> Pasadena, CA 91125                              fax:   (626) 795-8649

> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka


Article: 20414
Subject: Reconfigurable Computing Jobs
From: Jon Huppenthal <hupp@srccomp.com>
Date: Wed, 09 Feb 2000 08:12:42 -0700
Links: << >>  << T >>  << A >>
SRC Computers, founded by Seymour Cray in 1996, is looking for several
senior FPGA design engineers to be part of a team incorporating high
performance reconfigurable computationsl elements into current and
future products. SRC is a pre-public company located in beautiful
Colorado Springs, Colorado and offers competative salaries and benefits
including founders stock. If you have a desire to be part of a growing
company that is pushing the state of the art send your resume to
RPM@SRCCOMP.COM or fax it to Human Resources Dept 719-262-0223.
Article: 20415
Subject: Re: ADC to DSP... FIFO?
From: Jerry Avins <jya@ieee.org>
Date: Wed, 09 Feb 2000 10:28:20 -0500
Links: << >>  << T >>  << A >>
rk wrote:
> 
[snip using boning knife]
> 
> Obviously, there are other methods, too, but it is a bit late and not sure how
> many people are interested in this babble.  Most people I know ignore the lockup
> set of states problem.  A PC mentality, just hit the little red button on the
> front of the machine. :-)
> 
> Have a good evening,
> 
> ----------------------------------------------------------------------
> rk                               The world of space holds vast promise
> stellar engineering, ltd.        for the service of man, and it is a
> stellare@erols.com.NOSPAM        world we have only begun to explore.
> Hi-Rel Digital Systems Design    -- James E. Webb, 1968

This thread is both interesting and important. It is a cautionary tale
for the optimistic and a text for the cautious. Whatever can be done to
highlight and weed out the PC mentality is "in the service of man".

Jerry
-- 
Engineering is the art of making what you want from things you can get.
-----------------------------------------------------------------------
Article: 20416
Subject: Using Xilinx Serial EEPROMs
From: another_bbrekke@my-deja.com
Date: Wed, 09 Feb 2000 15:58:56 GMT
Links: << >>  << T >>  << A >>
I plan on using an XCV400 with an XC1804
configuration prom in the Master
Serial Mode.  Once configured, the design will
download calibration data
from a second EEPROM into a Block RAM in the
FPGA.  The calibration data
is unique to analog devices on the board that I
would like to be able to
alter without disturbing the configuration data,
and therefore cannot be
part of the configuration data. What I would like
to do is somehow partition
the XC1804 and use it to store the calibration
data after the configuration
data, thereby eliminating the second EEPROM.  I
searched the Website AppNotes
and Answers Database, but I haven't found any
supportive details on accomplishing
this.  Is there any practical way of doing this?
As a an alternative to this,
I am considering using a second, smaller XC18xx
type to store the calibration
data separately that could be loaded via JTAG and
once the FPGA is configured,
download the data serially under User I/O
control.  What I am not clear about
is converting the calibration data from a text
format into a .bit file format
that can be loaded into the XC18xx.  Does this
sound doable? Thanks.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20417
Subject: launching a FPGA cores start-up
From: fpgaer@my-deja.com
Date: Wed, 09 Feb 2000 16:24:47 GMT
Links: << >>  << T >>  << A >>
Hi,

wld. appreciate if anyone cld. share their views on launching a co.
which delivers custom-made FPGA cores ? Wld. the effort be worth in
terms of time ( & money ) ...... specifically, is there a demanding
market for FPGA cores ???

Any comments wld. be highly appreciated !!!

Thanks in advance........


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20418
Subject: 12+ month contract-NJ
From: Bob - Commtech Services <commtech@nac.net>
Date: Wed, 09 Feb 2000 11:49:43 -0500
Links: << >>  << T >>  << A >>
Contributing member to an ASIC team that is developing state of the art
      ASIC's. Candidate will be joining a team that is working to
develop
      ASIC's using .25 micron technology and smaller. Responsibilities
are
      ASIC/FPGA hardware design and devlelopment including participating
in
      system-level architectural decisions, identifying opportunities
for
      ASIC/FPGA design and implementing the design from RFQ to
evaluating
      models. SKILLS and EXPERIENCE: Must have good communication and
      documentation skills; Proven experience in ASIC design a must;
SONET,
      ATM and ICORE experience a strong plus. Experience with CAD tools:

      Synopsys Synthesis, VHDL capture on Summit VisualHDL, MTI
      simulation, Chrysalis and PrimeTime; EDUCATION: MSEE or MSCS
contact Bob Richards
973-361-8600
bob@gocommtech.com

Article: 20419
Subject: Re: launching a FPGA cores start-up
From: David Kessner <davidk@free-ip.com>
Date: Wed, 09 Feb 2000 10:22:26 -0700
Links: << >>  << T >>  << A >>
fpgaer@my-deja.com wrote:
> wld. appreciate if anyone cld. share their views on launching a co.
> which delivers custom-made FPGA cores ? Wld. the effort be worth in
> terms of time ( & money ) ...... specifically, is there a demanding
> market for FPGA cores ???
> 
> Any comments wld. be highly appreciated !!!

Making money in the IP business is difficult and not for the 
faint of heart.  There is an article in the latest EETIMES
that says it better than I could.  My experience with IP 
backs up what this article says.  The link to it is:

	http://www.eetimes.com/story/design/OEG20000203S0051

Hope that helps!

David Kessner
davidk@free-ip.com	http://www.free-ip.com/
Article: 20420
Subject: Re: Lattice isp programming problems
From: mikeandmax@aol.com (Mikeandmax)
Date: 09 Feb 2000 18:58:32 GMT
Links: << >>  << T >>  << A >>
Andrew wrote -
> had got to the stage of putting the
>download cable into the board and turning on the hardware. The power supply
>immediately cut out and once the cable had been removed the system stopped
>working.

Andrew - 
Sounds like you may have plugged the cable on backwards?  there is a keying
plug on pin 5 of the 8pin connector, which is intended to prevent reversing the
cable.  Inside the programming cable shell is a HCMOS buffer which is powered
by the system under test.  If you can, I would strongly suggest getting in
touch with the local FAE, and walk the problem through with him/her.   If the
ISPEN pin on the device is at ~-1v, it most likely is 'gone'.  Have you used
the programming cable and s/w successfully in the past, and can you still use
the cable with another test pcb - 'known good' is preferable.  For the
bench/pcb supply to cut out, a short of the supply pins is most likely, and a
reversed cable can do that.  If you need assistance in contacting your local
support, please send me an email, or call if in the US, and I will steer you to
the right office.
good luck-

Michael Thomas
LSC SFAE
516-874-4968 fax 516-874-4977
michael.thomas@latticesemi.com
for the latest info on Lattice/Vantis -
www.latticesemi.com


Article: 20421
Subject: RECONFIGURABLE board for image processign
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Wed, 09 Feb 2000 21:11:30 +0100
Links: << >>  << T >>  << A >>
Hello all,
I´m looking for a reconfigurable board (PCI, ISA) to develop REAL image
processing projects.
Any ideas?

--
===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion (TIC)
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
Ap. Correos 99, E-03080 ALICANTE
ESPAÑA (SPAIN)
email   : sergio@dtic.ua.es
Phone : +34 96 590 39 34
Fax     : +34 96 590 39 02
===================================================================


Article: 20422
Subject: Re: odd behavior of Virtex RAM Block model
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 09 Feb 2000 12:28:27 -0800
Links: << >>  << T >>  << A >>

Both hints solved the problems. Thanks to Ray and qwerty@scottfamily.cc.

-Arrigo

<qwerty@scottfamily.cc> writes:

> I had the same issue- and simply set the simulation resolution to 
> ns rather than ps.  For functional sim, the worked fine.
> 
> 
> Ray Andraka <randraka@ids.net> wrote:
> > Set the TimingChecksOn generic to "FALSE", that should suppress the
> > checks.  I'm not sure why those are defaulted TRUE in the unisim
> > library.  If you look at the vital source, you'll see that generic along
> > with a whole list of timing generics.
> 
> > Arrigo Benedetti wrote:
> 
> >> Dear all,
> >>
> >> I was wondering if others have noticed any strange results from the
> >> *functional* simulation of VHDL design using the Virtex SelectRAM
> >> Block model from the UNISIM library (I'm using Synopsys). First,
> >> I get warnings about setup time violations and I don't see why
> >> since I'm doing a functional simulation:
> >>
> >> "*/RAMB4_S2_S4 HOLD  Low VIOLATION ON WEB WITH RESPECT TO CLKB;
> >>   Expected := 0.01 NS; Observed := 0 NS; At : 146575.1 NS"
> >> Assertion WARNING at 146575100 PS in design unit VITAL_TIMING from
> >> process /BENCH/U1/U2/BRAM1/VITALBEHAVIOR:
> >>
> >> A quick fix of course is delaying the signal WEB with respect to
> >> CLKB by 10ps with an after clause in the signal assignment,
> >> but I should not get this worning at all I think.
> >>
> >> I also noticed that the DOA (port A outputs) go active as soon as ENA
> >> goes from 0 to 1 instead of going active with the transition of
> >> the clock from 0 to 1.
> >>
> >> Any ideas?
> >>
> >> Thanks in advance,
> >>
> >> -Arrigo
> >> --
> >> Dr. Arrigo Benedetti                e-mail: arrigo@vision.caltech.edu
> >> Caltech, MS 136-93                              phone: (626) 395-3695
> >> Pasadena, CA 91125                              fax:   (626) 795-8649
> 
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email randraka@ids.net
> > http://users.ids.net/~randraka
Article: 20423
Subject: Spartan and timing analyzer: clock nets using non-dedicated resources
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Wed, 9 Feb 2000 15:33:05 -0700
Links: << >>  << T >>  << A >>
I've got a fairly simple all-VHDL Spartan design (easily fits into an
XCS20XL-4 using 119 of the 400 CLBs) with an annoying "problem."  Tools are
FPGA Express v3.3 and F2.1i SP4.  It takes in an 80 MHz clock and uses that
clock for some of the logic, and also divides it by two to generate a 40 MHz
clock which drives the rest of the logic.

The tools are smart: FPGA Express inferred a BUFGLS for the 80 MHz clock and
another one for the 40 MHz clock.  I confirmed this by looking at the design
in the FPGA Editor.  I set up period constraints for the 80 MHz and the 40
MHz logic.  P+R was fine and the timing analyzer tells me that I meet all of
my constraints with margin to spare.

But there's a warning: "Timing:33:Clock nets using non-dedicated resources
were found in this design.  Clock skew on these resources will not be
automatically adress during path analysis.  To create a timing report that
analyzes clock skew for these paths, run trce with the '-skew' option."

OK, I did and I still meet timing.  My question:

How do I (easily) find what/where these alleged non-dedicated resources are?

-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Money is property; it is not speech."
            -- Justice John Paul Stevens


Article: 20424
Subject: Re: EDIF info
From: "Sébastien Buschini" <sbusch@club-internet.fr>
Date: Wed, 09 Feb 2000 23:56:28 +0100
Links: << >>  << T >>  << A >>


Jose a écrit:

> Hi, I would like to obtain more info about EDIF especification.
> Thanks.
>
> --
> Jose (a_k_y@hotmail.com)

Did you try http://www.edif.org ?



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