Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 22725

Article: 22725
Subject: Re: FPGA emultaion of a microprocessor
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Fri, 19 May 2000 22:08:58 +0200
Links: << >>  << T >>  << A >>
Have you thought about implementing a translator from one instruction set to
another?
If you let the FPGA fetch old style instructions and create new style
instructions
to a standard high speed RISC CPU, you could perhaps get a more cost
effective approach...



--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden

"J.W. Krych" <jwkrych@n2net.net> wrote in message
news:3924b101$1_2@athena.netset.com...
> Hello!
>
> I am currently in the R & D phase of a potential new product. We need to
> have a replicated microprocessor, but have it running at far greater
speeds
> than currently available through the normal manufacturer.
>
> We are more than willing to use the much larger FPGA's out there to
> accomplish this. Anyone who has experience in creating/emulating computer
> designs with FPGA's, please get ahold of me. I will discuss more and have
> greater in-depth questions.
>
>
> Regards,
>
> Jim W. Krych


Article: 22726
Subject: Re: SpartanXL driving 5V CMOS input
From: Lasse Langwadt Christensen <Langwadt@ieee.org>
Date: Fri, 19 May 2000 22:57:48 +0200
Links: << >>  << T >>  << A >>


Peter Alfke wrote:
> 
> Don't forget: Every Xilinx output pin is always also an input pin, whether you want it or not.
> The speed-up trick uses no additional device pin, since the 2-input AND gate is internal to the device.
> You have to use a CLB to implement the AND function,
> and you may remember that it is desirable to have a few extra ns of delay in this path, since that gives the output a chance to rise higher than just the input
> threshold.
> 
> It's one of the nicest tricks I have ever seen. ( Idid not invent it, a European Xilinx FAE did ).
> 

yes nice trick, some of the ports on a 80c51 uses something similar
they have weak pullups so that can be used as both input and output,
but when used as output the first 2 cycles after each 0-1 transition 
an extra pull is turned on   

-- Lasse
(+)--------------------------(+)
 | Lasse Langwadt Christensen |
 | Aalborg, Denmark           |  
(+)--------------------------(+)

Article: 22727
Subject: Re: Spartan II availability and pricing
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 19 May 2000 19:37:05 -0400
Links: << >>  << T >>  << A >>
Rick Collins wrote:
> 
> I found what looks like a marketing glossy, but is really an app note in disguise
> showing recommended pad and via layouts for the CS and FG packages. They show
> annular rings of 5 mil widths. So I guess I can go with an FG or CS package and at
> least not make my board fab any worse.

To Etienne Racine:

The file name of the document is hivolpkg.pdf. The URL is
http://www.xilinx.com/products/spartan2/hivolpkg.pdf


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22728
Subject: Processor
From: Sreedhar Sampath <sreedhar@capsl.udel.edu>
Date: Fri, 19 May 2000 21:29:54 -0400
Links: << >>  << T >>  << A >>
Hello!
         We are looking towards implementing one of our Architectural
design of a processor(PARALLEL). The architecture has several nodes and
each node consists of two processors. One to communicate with other modes
and other just executes the job given to it.
We are looking for an FPGA implemetation of this Synchronisation unit.

This unit has to talk to other processor of the node which is called
Execution Unit(EU)  and also has to read data from MEMORY. All this is
done using a PCI interface which will be 33/66 MHZ. This is defintely a
deadlock for the speed. This makes the HOST processor (EU) wait till
the Synchronisation unit has performed its job. Right now we
have a S/W implementation of both the processors. 

I was wondering if that were the case do we have any processors
implemented at all on FPGA. HOw could this problem be solved. Then how do
we say that FPGA implemntation is better.

Thanks in advance.

-Sreedhar


Article: 22729
Subject: Tech: looking for Allpro programming software
From: gonzothegreat@juno.com (Al McCormick)
Date: Sat, 20 May 2000 07:51:18 GMT
Links: << >>  << T >>  << A >>
I recently purchased an old Allpro device programmer and I need the software 
to use it. Their website was less than useless and after reading about them on 
USENET, its not surprising.

Thanks

Virtu-Al
Article: 22730
Subject: What is ASIC and FPGA?
From: "Arkady Skorokhod" <skorohod@techunix.technion.co.il>
Date: Sat, 20 May 2000 20:45:18 +0300
Links: << >>  << T >>  << A >>
Please, where I can find explanation what is ASIC and FPGA?

Thanks.


Article: 22731
Subject: Re: Printed magazines
From: "Leroy Davis" <lsdavis@spacey.net>
Date: Sat, 20 May 2000 16:07:12 -0400
Links: << >>  << T >>  << A >>
Per quarter:
http://www.vhdl.org/vhdl_intl/vltimes/index.html

Could be they would mail it to you


"Thorsten Bunte" <t.bunte@beckhoff.de> wrote in message
news:8g2ov6$hg67$1@fu-berlin.de...
> Hello,
>
> Are there any vendor independent printed magazines about VHDL and/or
> FPGA/ASIC designs available?
>
> If yes, where can I get them in Germany?
>
> Thanks in advance,
>
> Thorsten
>
>
>
>




-----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
-----==  Over 80,000 Newsgroups - 16 Different Servers! =-----
Article: 22732
Subject: Re: Do you know xilinx FPGAs well?
From: edick@hotmail.com (Richard Erlacher)
Date: Sun, 21 May 2000 05:07:40 GMT
Links: << >>  << T >>  << A >>
On Fri, 12 May 2000 10:14:24 GMT, shahzad2512@my-deja.com wrote:

>I have to implement the following:
>1. 8032 microcontroller,
>2. 64kbytes SRAM,
>3. some 8 latches and two 3x8 decoders,
>4. 12kHz Generator
>5. 16kHz detection
>6. DTMF dialer.
>
>The above is the customized solution for a telephone set for some
>telecom company.
>
>After some initial study, i think that Virtex could give me solution.
>There is also an A/D converter(which i might need) in the Virtex and
>such a large memory could only be implemented in an Virtex.
>
>But then i thought that since Virtex is expensive, this is not a good
>solution. I thought of SPARTAN II but then SRAM is out.
>What do u thing and suggest.
>Any comments........?
>Thanks and Regards,
>SHAH
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.
========================================================================
this is dirt simple to implement in the form of the components you've
listed, and will not only cost about 1% of what an FPGA capable of
doing this (not even considering the development tools) will cost but
won't really take much more board space.  The RAM, CPU, and the PROM,
which you've left out but without which the system won't work, take
one relatively small IC each and a small CPLD will do the latches and
decoders.  the 8032's timers will easily do your rate generation, and
the dtmf can be handled in firmware PWM as well.  There are
8032-compatible processors (Philips, Siemens)  with six or eight I/O
ports, so you may not need all those latches, and that might alleviate
the need for decoding logic as well.  A little poking around on the
various 805x-compatible chip-makers' web sites will probably yield at
least one part that has all the features you list.  

Now, about that ADC . . . don't EVER put in a featue that's not
required.  Required means that you get fired if you leave it out.
Putting it in often means you get fired because you wasted $.01 of the
boss' money times 5 million units . . . you know how he feels about
wasting paper clips . . . 

Dick

Article: 22733
Subject: Re: Why are there no "cheap" FPGAs?
From: edick@hotmail.com (Richard Erlacher)
Date: Sun, 21 May 2000 05:20:03 GMT
Links: << >>  << T >>  << A >>
Maybe you need to forget about FPGA's and consider CPLD's.  They're
not so costly if yo don't mind the somewhat smaller gate count.
Remember, though a CPLD has fewer gates, it's practical to consider
using them all, while you're  lucky to get to use half of the gates in
an FPGA.  Higher utilization requires many weeks of careful
floorplanning and attention to resource allocation details generally
not a concern with CPLD's.  

The FPGA vendors can't claim their process is too costly to allow for
low-cost devices, since they don't make them differ for each customer.
It's just that they need the dough to stay ahead of their competitors.


If you want a small, low-cost part, the other alternative is the
high-speed but cheap and small SCENIX 100 MIPS microprocessor.  Think
of it as a funcional block rather than a microcomputer, and you'll
surprise yourself with the clever things you can do.  What's more, you
don't have to deal with the many kilobuck investment in buggy
development software.  You'll see less cost, though the software isn't
bug-free either.

Dick


On Sat, 29 Apr 2000 08:03:25 +0000, z80@ds2.com (Peter) wrote:

>
>Xilinx are busy churning out devices with billions of gates, and the
>cost per gate is certainly falling.
>
>But they don't seem to do something for say $2 - at the same cost per
>gate this should yield a few thousand gates, for the cost of a low
>power 22V10.
>
>I know Xilinx etc are growing and doing well, but the fact remains
>that only a very tiny proportion of today's products actually contains
>an FPGA. Far more designs use a PLD somewhere, with some ordinary
>logic as well.
>
>A few years ago I met a large direct Xilinx user who said he was
>getting the XC3020 for $4.50 on a 50k/year quantity - so low prices
>are possible but only in vast quantities, and such prices would never
>be officially mentioned.
>
>
>Peter.
>--
>Return address is invalid to help stop junk mail.
>E-mail replies to zX80@digiYserve.com but remove the X and the Y.
>Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 22734
Subject: Re: Why are there no "cheap" FPGAs?
From: Ray Andraka <ray@andraka.com>
Date: Sun, 21 May 2000 06:02:54 GMT
Links: << >>  << T >>  << A >>


Richard Erlacher wrote:

> Maybe you need to forget about FPGA's and consider CPLD's.  They're
> not so costly if yo don't mind the somewhat smaller gate count.
> Remember, though a CPLD has fewer gates, it's practical to consider
> using them all, while you're  lucky to get to use half of the gates in
> an FPGA.  Higher utilization requires many weeks of careful
> floorplanning and attention to resource allocation details generally
> not a concern with CPLD's.

Au contraire!  CPLDs can have their fair share of fitting problems as well,
especially if you are using most of the macrocells and need the speed.
Lattice 1032Es come to mind.  Not all FPGAs are high priced either.  Look
at the prices marshall is posting for small quantities of Xilinx spartan
2's for example: XC2S100-5FG256C = $27.11  XC2S50-5FG256 = $18.10.  These
are 100K and 50K marketing gates respectively, and include block RAM.
FPGAs aren't just for the deep pocketed any more.

>
>
> The FPGA vendors can't claim their process is too costly to allow for
> low-cost devices, since they don't make them differ for each customer.
> It's just that they need the dough to stay ahead of their competitors.
>
> If you want a small, low-cost part, the other alternative is the
> high-speed but cheap and small SCENIX 100 MIPS microprocessor.  Think
> of it as a funcional block rather than a microcomputer, and you'll
> surprise yourself with the clever things you can do.  What's more, you
> don't have to deal with the many kilobuck investment in buggy
> development software.  You'll see less cost, though the software isn't
> bug-free either.
>
> Dick
>
> On Sat, 29 Apr 2000 08:03:25 +0000, z80@ds2.com (Peter) wrote:
>
> >
> >Xilinx are busy churning out devices with billions of gates, and the
> >cost per gate is certainly falling.
> >
> >But they don't seem to do something for say $2 - at the same cost per
> >gate this should yield a few thousand gates, for the cost of a low
> >power 22V10.

What about the Spartan XCS05?  It's in the $2 range.

>
> >
> >I know Xilinx etc are growing and doing well, but the fact remains
> >that only a very tiny proportion of today's products actually contains
> >an FPGA. Far more designs use a PLD somewhere, with some ordinary
> >logic as well.
> >
> >A few years ago I met a large direct Xilinx user who said he was
> >getting the XC3020 for $4.50 on a 50k/year quantity - so low prices
> >are possible but only in vast quantities, and such prices would never
> >be officially mentioned.

Check the latest pricing for single quantities at http://www.avnet.com
under the price and availability.  I think you might be surprised at the
pricing on the Spartan and Spartan 2 lines.


--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22735
Subject: Re: Creating custom flip-flops in Altera MAX+Plus II
From: "Johan Küstner" <kustner@intekom.co.za>
Date: Sun, 21 May 2000 12:31:35 +0200
Links: << >>  << T >>  << A >>
Hi,

You need to play around with the Max+plus II software a bit to get used to
it. It has a lot of good features, if used correctly. The only way to figure
things out is to work at it. Get yourself an Altera Data CD from the Altera
website or download information from their website. Everything is there. You
just have to look deep enough.

--
Regards

Johan F. M. Küstner
Telephone (27) (11) 818-4850
E-mail kustner@intekom.co.za
Ashok Mahadevan <ashokm1@earthlink.net> wrote in message
news:392216F8.78E9786D@earthlink.net...
> Hello,
>
>    I am a *very* new user to this FPGA stuff and I am using the
> schematic capture feature in Altera MAX+Plus II 9.6 Baseline for
> my design and have the following questions:
>
> 1) I need some custom D and T flip-flops - by custom I mean that I
>    want some with ENABLE, some with CLEAR, some with PRESET and
>    various combinations of the above, all with programmable polarity
>    and programmable clock polarity too. I cannot seem to find a way
>    to take the generic D/T flip-flop and modify it for my needs. Is
>    this possible? Or am I stuck with using inverters and tying the
>    unused inputs of the f/f's to Vcc/GND as appropriate? I really do
>    not want to use any LPM stuff for this.
>
> 2) I am using the LPM module for my custom multiplexer and demux
>    modules and when the module is placed on the sheet, two boxes show
>    up -  one with the mux/demux itself and one on the upper right hand
>    corner with the mux/demux specifications (width, etc.). Is there a
>    way to turn off or hide this annoying specification box? And is
>    there a way to move this box without moving the mux/demux symbol
>    too?
>
> 3) Is there a way create "bubbles" (for inversion) at the input of
>    logic gates? There are gates with these bubbles on *all* the inputs,
>    but I want to be able to place these inverters on just some of them.
>    I like the bubble scheme instead of actual NOT gates since it saves
>    space on the schematic.
>
> Thank you for your time!
> Ashok
>
>


Article: 22736
Subject: Help for a novice of Xilinx Foundation
From: "l'landre" <andmars@tin.it>
Date: Sun, 21 May 2000 17:17:47 +0200
Links: << >>  << T >>  << A >>
I've just started to use the Xilinx Foundation development toolset.
I encountered some problems and I want to understand, with your help,
 if they are due to my mistakes or not.
The designs I make are schematic-oriented; I use the version 2.1i
(Service Pack 5 installed)  for the Spartan family.
Here it is a list of problems I had:
1) When I tried to create macros written in VHDL, sometimes the
graphical symbol does not have all the I/O pins I defined in the entity
though it is synthesized.
2) I used a 16MHz clock from which, through a counter, I got some
other frequencies (8MHz, 4MHz and so on) that I outputted on different
pins. With the oscilloscope I noted that these 'derived' frequencies are not
stable compared to the 'master' clock (16MHz). I mean that you can see
that their waveforms 'slide' in a random way, while the 16MHz is fixed on
the
oscilloscope screen.
3) Sometimes the schematic editor links different nets by itself! You don't
see
the graphical wire but when you compile the project you get an obviuos
error.
Through the query tool I can see that they are really linked!
I solved this problem in the following way: I select the entire schematic,
then I cut and paste it to force the editor to re-create the netlist.


I really hope the someone can help me because I'm really going crazy.
Thanks a lot in advance.

Andrea



e-mail: andmars@tin.it
web: www.dei.unipd.it/~patch






Article: 22737
Subject: Dynamically configuring Vertex/Spartan II
From: "Andy Krumel" <andy@krumel.com>
Date: Sun, 21 May 2000 08:40:17 -0700
Links: << >>  << T >>  << A >>
We are currently using a PIC microcontroller and flash to configure our
FPGAs since we need to choose from one of several stored configurations. As
has been widely reported, flash is hard to get and prices are very unstable.
Even worse, trying to get a flash device that is 1 or 2 Mb is getting more
difficult as manufacturers continue towards producing larger sizes. We also
update the flash based configurations over time.

Seems kind of crazy that as FPGA prices for devices like the Spartan II and
ACEX get attractively priced, the dynamic configuration resources start  to
consume a significant chunk of device costs. As memory costs head up, that
seems to be where things are going.

To reduce costs I would love to hear any alternatives to using a
microcontroller/flash. I can get a suitable processor for $2-$3 in quantity.
Any idea what a suitable CPLD would run? Do CPLDs that are up to the job get
that cheap?

EEPROMs seem to cost a lot more than flash so we have kind of ruled those
out. RAM is cheaper than flash but is nonvolatile. Does anyone have an
economical idea for long term storage of several FPGA bit streams besides
flash? We have been looking at Atmel flash parts so far. Any experience on
price, service, availability vs. vendor?

Thanks,
Andy


Article: 22738
Subject: Re: Best choice between FPGA and CPLD
From: "Robert Weber" <weber@snet.net>
Date: Sun, 21 May 2000 13:14:48 -0400
Links: << >>  << T >>  << A >>
This seems like it would need relatively few macrocells (for combinatorial
logic, flip-flops and registers). A CPLD in the 128 macrocell range is
probably what you would need (just a wild guess here). This is in the area
of 5K gate equivalent for an FPGA. If you need 50K gates, the FPGA is the
way to go.

The timing issues on the CPLD are easier to deal with than the FPGA. Also,
once programmed, the CPLD will come up alive immediately, while SRAM based
FPGA (like Altera and Xilinx) require the program to be loaded from an
external memory source. If the logic is used for address decoding, it might
be needed immediately on powerup.

Bob W.


Simon Bilodeau wrote in message <9qhU4.91$3F3.1719@wagner.videotron.net>...
>Hi i'm quite new in FPGA and CPLD world.
>
>I have to design a board with address decoding and a few event counters (16
>bit counters) interfaced with an PC104 bus.
>
>Is it better to use CPLD or FPGA? Why?
>
>Thanks
>
>
>Simon
>
>
>


Article: 22739
Subject: Re: Help for a novice of Xilinx Foundation
From: Christian Mautner <at@utanet.cmautner>
Date: 21 May 2000 19:26:19 +0200
Links: << >>  << T >>  << A >>
"l'landre" <andmars@tin.it> writes:

> I've just started to use the Xilinx Foundation development toolset.
> I encountered some problems and I want to understand, with your help,
>  if they are due to my mistakes or not.
> The designs I make are schematic-oriented; I use the version 2.1i
> (Service Pack 5 installed)  for the Spartan family.
> Here it is a list of problems I had:
> 1) When I tried to create macros written in VHDL, sometimes the
> graphical symbol does not have all the I/O pins I defined in the entity
> though it is synthesized.

I'd guess that they were optimized away by the synthesis engine. Are
you sure that all your inputs really drive logic, and that all your
outputs are driven?

> 2) I used a 16MHz clock from which, through a counter, I got some
> other frequencies (8MHz, 4MHz and so on) that I outputted on different
> pins. With the oscilloscope I noted that these 'derived' frequencies are not
> stable compared to the 'master' clock (16MHz). I mean that you can see
> that their waveforms 'slide' in a random way, while the 16MHz is fixed on
> the
> oscilloscope screen.

This sounds to me like either a timing problem (which is unlikely at
these low speeds) or problems due to asynchronous design. It's hard to
say without seeing your sourcecode/schematic. (That is one the reasons
why I prefer HDLs over schematics; try posting your schematic... ;)

> 3) Sometimes the schematic editor links different nets by itself! You don't
> see
> the graphical wire but when you compile the project you get an obviuos
> error.
> Through the query tool I can see that they are really linked!
> I solved this problem in the following way: I select the entire schematic,
> then I cut and paste it to force the editor to re-create the netlist.

Sorry, cannot help you with this one.

chm.

-- 
cmautner@  -  Christian Mautner
utanet.at  -  Vienna/Austria/Europe
Article: 22740
Subject: Re: Help for a novice of Xilinx Foundation
From: Ray Andraka <ray@andraka.com>
Date: Sun, 21 May 2000 20:16:14 GMT
Links: << >>  << T >>  << A >>


Christian Mautner wrote:

>
> > 2) I used a 16MHz clock from which, through a counter, I got some
> > other frequencies (8MHz, 4MHz and so on) that I outputted on different
> > pins. With the oscilloscope I noted that these 'derived' frequencies are not
> > stable compared to the 'master' clock (16MHz). I mean that you can see
> > that their waveforms 'slide' in a random way, while the 16MHz is fixed on
> > the
> > oscilloscope screen.
>
> This sounds to me like either a timing problem (which is unlikely at
> these low speeds) or problems due to asynchronous design. It's hard to
> say without seeing your sourcecode/schematic. (That is one the reasons
> why I prefer HDLs over schematics; try posting your schematic... ;)
>

More likely, it is a setup problem with the test.  If you are triggering the
O'scope on the 16 MHz clock, then the start position of the derived clocks is not
going to be the same on each trace.  Trigger your scope with the lowest frequency
derived clock.

>
> > 3) Sometimes the schematic editor links different nets by itself! You don't
> > see
> > the graphical wire but when you compile the project you get an obviuos
> > error.
> > Through the query tool I can see that they are really linked!
> > I solved this problem in the following way: I select the entire schematic,
> > then I cut and paste it to force the editor to re-create the netlist.
>

Are the net names the same?

--
P.S.  Please note the new email address and website url

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22741
Subject: Re: Spartan 2 Industrial temp range versions
From: "Mark Harvey" <mark.harvey@iol.it>
Date: Mon, 22 May 2000 09:37:29 GMT
Links: << >>  << T >>  << A >>
The Spartan-II devices will be available in industrial grade, it's just that
Xilinx want you to order 10's of thousands...


Allan Herriman <allan.herriman.hates.spam@fujitsu.com.au> wrote in message
news:38c8f1db.41872769@newshost.fujitsu.com.au...
> Hi,
>
> The current Spartan 2 datasheet (0.9) doesn't indicate that any parts
> are available in industrial temperature range versions.
>
> Does anyone know which parts are planned to be made available in this
> temperature range?
>
> The XC2S150 in the FG456 package is just perfect for my application,
> but I can't use a commercial temp range part.
>
> Thanks,
> Allan.


Article: 22742
Subject: Re: verilog modules into viewlogic designs
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 22 May 2000 14:18:35 +0300
Links: << >>  << T >>  << A >>
maespin wrote:

> What is the best (easiest/fastest/most efficient) way to get verilog
> modules into a xilinx fpga design which was created using viewlogic's
> viewdraw schematic capture tool?
>
> Thanks,
> Mark

http://toolbox.xilinx.com/docsan/2_1i/data/alliance/vli/vli.htm
is Xilinx-Viewlogic Interface Guide, gives you how to do
what you want above.

Utku

--
I feel better than James Brown.



Article: 22743
Subject: About Xilinx DLL
From: "Simon Zhang" <zhangyuc@online.sh.cn>
Date: Mon, 22 May 2000 19:46:26 +0800
Links: << >>  << T >>  << A >>
Hi, there,

I am newbie here, wonder if anyone can help me with the following questions.

I use Xilinx Virtex in my project.  It seems that I have to feed DLLs on
different side of the FPGA with the same clock root.  It is not allowed by
Alliance, the PAR tool.  Do I have to route the clock net outside the chip,
on PCB, or there is other way to do so?

I found manually locate logics in certain CLB will do much help to the PAR.
How often do you use the internal tools of Alliance, such as Floorplan and
FPGA Editor?  Every PAR or only in fine tune?

Can I locate a bus to several pads of the equivalent number but without
specify loc of each pin?

Thank you in advance!

Simon Zhang


Article: 22744
Subject: Web page for FPGA design jobs???
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Mon, 22 May 2000 15:33:37 GMT
Links: << >>  << T >>  << A >>
I am looking for work as an FPGA designer.
My specialty is graphics/video/imaging.

Are there any good web pages dedicated to this field ?

Thanks
Dan


Article: 22745
Subject: Xilinx tools
From: Rickman <spamgoeshere4@yahoo.com>
Date: Mon, 22 May 2000 12:42:04 -0400
Links: << >>  << T >>  << A >>
I was just looking at the Xilinx web site to get info on their current
tools and I now see that they no longer sell the tools. Rather Xilinx
rents the tools to you for 1 year at a time. At the end of the year you
can no longer use the tool for new designs. 

I have heard of some of the ASIC tool vendors doing this as a means to
enhance their revenue. They are constantly trying to adjust their
business model to maximize revenue since this is what they make money
on. 

So now it looks like Xilinx is not happy with customers buying a given
version of the tools and using that one version for new designs as long
as they are happy with the known bugs in it. After a year, the tools
will no longer let you start any new designs unless you pay the licence
fee again. 

I don't get it. Xilinx keeps telling us that they want to make money
from their chips and not the software. But this sure looks to me like
they are trying to maximize the revenue from the tool sets. 

What do others think about this?


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 22746
Subject: Coregen generated FIFO not working
From: khoi ha <kha@fallschurch.esys.com>
Date: Mon, 22 May 2000 12:59:21 -0400
Links: << >>  << T >>  << A >>
Hello,

I created a 255 deep by 32 bit fifo using Coregen and I am having
problem getting it to simulate.  The device does not seem to be doing
anything, even the reset input does not work.  I know this is a lot to
ask but hopefully there is something I missed that are easy to see.  I
followed exactly what the Coregen's user manual told me to do.  Here are

my tools environment:

Window NT
Using Virtex 1000 series
Using Modelsim PE/VHDL 5.3b
Using Coregen 2.1i
Using C_IP5

Attached is my vhdl file that instantiated the files (.vho) produced by
Coregen.

Thanks
Khoi Ha
Raytheon Systems
(703)560-5000 x4481



Article: 22747
Subject: Programming Virtex FPGAs using VPR and JBits
From: vgarg@spock.ecs.umass.edu (VIBHOR GARG )
Date: 22 May 2000 19:19:06 GMT
Links: << >>  << T >>  << A >>
Hi all,

We at the Reconfigurable Computing Group and VLSI Testing Laboratory at
University of Massachusetts,Amherst have developed a tool which can generate
a bitstream for programming the Xilinx Virtex FPGAs using VPack, VPR and
JBits2.0.1(API from Xilinx). The tool starts with a blif description of the
circuit and goes through the design tool and creates the bitstream.
The tool at present is under development. It makes use of only single lines
for routing purposes and works for combinational circuits.
The tool is available at www-unix.ecs.umass.edu/~rramaswa/jbits/jbits.html

Regards,
Reconfigurable Computing Group
VLSI Testing Laboratory


Article: 22748
Subject: US-IL-In desperate need of FPGA engineer
From: "Technisource Inc." <jobs@tsi.net>
Date: Mon, 22 May 2000 16:18:41 -0400
Links: << >>  << T >>  << A >>
Hi Everyone,
    I don't mean to interrupt, but I know that you are all experts in
digital design and I would like to ask for a little of your help.  I
currently have a couple of openings for a FPGA designer for a company in the
suburbs of Chicago.  This position is looking for someone to do the design,
simulation and timing of a digital design, a FPGA with a high number of
gates, approaching 1 million.
    I would appreciate it if you would help me in any way in filling these
positions.  We currently have 3 available so if you know of anyone that
might be looking or if you are looking please contact me at enolan@tsrc.net
or at 1-800-330-3308 et 209.  Also, any help in other places to look for
qualified individuals would be appreciated.
    Once again, I apologize for the interruption, but this is a great
opportunity with a growing company.  Thank you all for your time.

Erin Nolan
Technisource
enolan@tsrc.net
800-330-3308 ext 209


Article: 22749
Subject: Re: Xilinx tools
From: Christian Mautner <at@utanet.cmautner>
Date: 22 May 2000 23:13:49 +0200
Links: << >>  << T >>  << A >>
Rickman <spamgoeshere4@yahoo.com> writes:

> I was just looking at the Xilinx web site to get info on their current
> tools and I now see that they no longer sell the tools. Rather Xilinx
> rents the tools to you for 1 year at a time. At the end of the year you
> can no longer use the tool for new designs. 
> 
> I have heard of some of the ASIC tool vendors doing this as a means to
> enhance their revenue. They are constantly trying to adjust their
> business model to maximize revenue since this is what they make money
> on. 
> 
> So now it looks like Xilinx is not happy with customers buying a given
> version of the tools and using that one version for new designs as long
> as they are happy with the known bugs in it. After a year, the tools
> will no longer let you start any new designs unless you pay the licence
> fee again. 
> 
> I don't get it. Xilinx keeps telling us that they want to make money
> from their chips and not the software. But this sure looks to me like
> they are trying to maximize the revenue from the tool sets. 
> 
> What do others think about this?
> 

I think that this is not good idea, not for the customers and not for
Xilinx. Especially if you consider that Altera is giving away a (not
100% but useful) version of their tools (including a decent synthesis
tool) for free.

Furthermore, IMHO this is not even legal in most European
countries. But I'm not sure about this one.

chm.

-- 
cmautner@  -  Christian Mautner
utanet.at  -  Vienna/Austria/Europe


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search