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Messages from 86925

Article: 86925
Subject: Re: Timespec for DCM outputs (Spartan 3) ?
From: "Dave" <starfire151@cableone.net>
Date: Sat, 9 Jul 2005 10:02:12 -0600
Links: << >>  << T >>  << A >>
Hi Paul -

This is a very interesting application.  I've done something similar with an 
Actel Axcelerator and 4 clock phases.  Each phase was skewed by 1ns from the 
next phase.  I ran the internal PLLs with a 62.5MHz input and set the PLLs 
up for a 4X operation and an output of 250MHz.  This gave an overall system 
of 4 clock phases at 250MHz with 1ns between phases.  With 4 phases, the 
programmed precision of delays was adequate.  The Actel devices had a 
resolution of 130ps step sizes for programmed delay.  This application wound 
up being very successful, though.

One thing to watch, though, is the jitter on the clock input line.  If 
multiple modules are driven from the same clock, each module may have a 
slightly different jitter value.  Since you're depending on pretty precise 
alignments between phases, these values may affect overall precision.

I would be very interested in hearing of your progress.  I am looking at 
implementing an enhanced version of our current design using more clock 
phases.

Dave

"Paul Boven" <p.boven@chello.nl> wrote in message 
news:1120867584.826621@blaat.sara.nl...
> Hi Vladislav, everyone,
>
> Vladislav Muravin wrote:
>
>> One alternative is:
>> Lock each clock output to a pre-defined BUFGMUX location.
>
> That wouldn't work: I have 4 DCMs with 4 outputs each, which would require 
> 16 BUFGMUX, but there are only 8 of them. And using a BUFGMUX seems a bit 
> overkill for a net that only connects to one flipflop.
>
>> Then, describing each FFs in a different block (per different clock 
>> domain),
>> assign area constraints as to place it as close as possible.
>>
>> Another:
>> After you define a TNM group, specify the maximum delay (never tried this 
>> one, but it should be ok in terms of contraints)
>
> I've figured out how to define TNM or TIMEGRP entities, but not how to 
> apply constraints like maxdelay or maxskew to them. Any hints?
>
>> But what exactly is your application?
>
> My application is a reciprocal frequency counter. There will be two input 
> signals: a 100MHz reference clock, and an unknown input. I want to measure 
> the time between two rising edges of the input signal as accurately as 
> possible. The input signal is used as the data input to 16 D-flipflops. 
> Each flip flop is clocked from a different DCM. The first DCM provides 0, 
> 90, 180 and 270 degrees of my original 100MHz reference. Hence, it 
> quadruples my resolution. The second DCM has a fixed phase offset of 32 
> (45 degrees) and produces clock signals at 45, 135, 225 and 315 degrees, 
> doubling my resolution once more: Using all four DCMs gives me the ability 
> to determine where the rising edge of the input signal falls in 
> relationship to the 100MHz input with a resolution of 22.5 degrees or 
> 1/16th of a full phase. This corresponds to a resolution of 625ps, or an 
> equivalent reference of 1.6 GHz.
>
> For this to work, I need to make sure that the delay from the DCM outputs 
> to all the clock inputs on the flipflops are as equal and as low as 
> possible.
>
> All the (single wire) nets that connect a DCM output to its flipflop, I've 
> named "net_DCMx_y" where x = the number of the DCM (0 - 3) and Y the 
> phase-shift of the signal.
> I've tried setting "net net_DCM* maxdelay=1ns;" in my UCF. I'm not sure 
> whether it does very much: Mostly it just happily reports that it violated 
> 6 out of 8 timing constraints.
>
> Maxskew is related to a single net, and is without meaning on nets that 
> consist of a single wire. If I could somehow constrain the differences in 
> delay of all the net_DCM* to be small, that would be very helpfull. 
> Perhaps this should be possible with TNM or TIMEGRP, but I haven't been 
> able to figure out how to use those.
>
> Any suggestions are very much appreciated.
>
> Regards, Paul Boven. 



Article: 86926
Subject: Re: Possible bug in Vertex-4 Rocket-IO?
From: shuo.huang@fibre.com
Date: 9 Jul 2005 09:05:15 -0700
Links: << >>  << T >>  << A >>
The number of parallel output words is correct. I do not get more
clocks at output. Every 40th word's value is replaced by the 39th. I
have checked the serial data. It is correct. It is the Rocket-IO that
works incorrect.

Marko wrote:
> So, you are getting more clocks output than you are inputting?  This
> must be the case if you are repeating codes.  I guess the other
> possibility is that you are inadvertently sending the same code twice
> and your receiver is working properly.


Article: 86927
Subject: Re: Ethernet reference design for ML310?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 09 Jul 2005 10:47:58 -0700
Links: << >>  << T >>  << A >>
Joseph wrote:
> After looking more closely at the block diagram of the ML310:
> http://direct.xilinx.com/products/boards/ml310/current/images/ml310_block.jpg
> It looks like what I really want is to add a pci bridge on the opb bus.

Well, the diagram shows that all of the interesting IO
is on the pci bus. Wouldn't make much of a Linux
machine without that bus.

>  Given a functional bridge, it should recognize NIC on the board as a
> PCI device, right?  

If that's already in the BSP, then yes
else you write PPC405 code.

Can anyone verify that I am on the right track?

You can. Try it and see.

        -- Mike Treseler

Article: 86928
Subject: Re: Announce: Impulse C-to-RTL Version 2 now available
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 09 Jul 2005 10:55:15 -0700
Links: << >>  << T >>  << A >>
David Pellerin wrote:

> Impulse CoDeveloper is a C-to-RTL tool targeting FPGAs and FPGA-based 
> hardware/software platforms. In addition to performing C-to-RTL compilation 
> from untimed C, . . .

How about adding a simple example of C source in and HDL out.
That might help you sell some books and get some evals.


               -- Mike Treseler

Article: 86929
Subject: Re: Possible bug in Vertex-4 Rocket-IO?
From: Marko <cantsay@comcast.net>
Date: Sat, 09 Jul 2005 11:07:35 -0700
Links: << >>  << T >>  << A >>
So, you get word 1-38, 39, 39, 41, 42 ... Is that correct?
You repeat word 39 and skip word 40?

Is the problem data dependent?  If you change the data, is the effect
the same?

Do you have a comma alignment character embedded?

Is this a single channel application or are you bonding multiple
channels together?



On 9 Jul 2005 09:05:15 -0700, shuo.huang@fibre.com wrote:

>The number of parallel output words is correct. I do not get more
>clocks at output. Every 40th word's value is replaced by the 39th. I
>have checked the serial data. It is correct. It is the Rocket-IO that
>works incorrect.
>
>Marko wrote:
>> So, you are getting more clocks output than you are inputting?  This
>> must be the case if you are repeating codes.  I guess the other
>> possibility is that you are inadvertently sending the same code twice
>> and your receiver is working properly.


Article: 86930
Subject: Re: Announce: Impulse C-to-RTL Version 2 now available
From: "JJ" <johnjakson@yahoo.com>
Date: 9 Jul 2005 13:46:13 -0700
Links: << >>  << T >>  << A >>
I am not really convinced of basic un RTL C to RTL conversion myself,
since its already possible to write  RTL in C to some degree but why
don't the plain C to RTL folks  try to persuade me with examples.

My other doubt comes from the fact that for FPGA, HDLs are almost free
except for large designs and does C bring anything to the table for the
high end.

Lets see perhaps a quicksort or other obviously NOT HW type algorithm C
code from the Sedgewick or any algorithm book along with output and
give us the synth results without having to touch the HDL code, and
compare that with hand designed HDL version. I am curious to know what
the upfront C tax cost is v potential coding effort savings, and
relative speed, used resources of the two approaches.

And how does Impulse C compare with Precision C, HandelC, even SystemC,
are they all using occam/CSP add ons to specify timing and parallelism?

johnjakson at usa dot com

I'll look out for the book though


Article: 86931
Subject: Re: Possible bug in Vertex-4 Rocket-IO?
From: shuo.huang@fibre.com
Date: 9 Jul 2005 14:35:40 -0700
Links: << >>  << T >>  << A >>
The problem is not data dependent. I did not enable comma alignment.
This is a single channel application.

Did you have succesfull experience with similar settings?


Article: 86932
Subject: Re: Possible bug in Vertex-4 Rocket-IO?
From: shuo.huang@fibre.com
Date: 9 Jul 2005 14:45:05 -0700
Links: << >>  << T >>  << A >>
Forgot to confirm your first paragraph. Yes. That is the pattern I see
in the simulation.

Thanks for your help.


Article: 86933
Subject: Altera QII WE Tutorials
From: "farnel" <d_tonkes@fanshaweonline.ca>
Date: 9 Jul 2005 16:54:36 -0700
Links: << >>  << T >>  << A >>
Looking for some help/advice in using Altera QII-WE. I am an
electronics student working with MSI & SSI 7400LS chip sets.My current
school places no empahsis on PLD`s at all. I am changing schools to one
which uses the quartus system and would like to get up-to-speed before
starting. I would like some links or information to help bridge the gap
between the two styles of learning. I have looked at the Altera
tutorial, but I was hoping someone may have some other introductory
training material available. 
Thanks, Dan.


Article: 86934
Subject: Re: Altera QII WE Tutorials
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sun, 10 Jul 2005 13:14:39 +1200
Links: << >>  << T >>  << A >>
farnel wrote:
> Looking for some help/advice in using Altera QII-WE. I am an
> electronics student working with MSI & SSI 7400LS chip sets.My current
> school places no empahsis on PLD`s at all. I am changing schools to one
> which uses the quartus system and would like to get up-to-speed before
> starting. I would like some links or information to help bridge the gap
> between the two styles of learning. I have looked at the Altera
> tutorial, but I was hoping someone may have some other introductory
> training material available. 
> Thanks, Dan.

  You could try running, then change, the application notes at
http://www.altera.com/literature/lit-m3k.jsp
http://www.altera.com/literature/lit-m7k.jsp
http://www.altera.com/literature/lit-max2.jsp

  Altera, besides VHDL & Verilog, Altera also have their own Boolean 
entry language called AHDL, and that is easier to learn for simple
applications, and migration to PLDs from SSI/MSI background.

-jg




Article: 86935
Subject: Re: Announce: Impulse C-to-RTL Version 2 now available
From: "Hans" <hans64@ht-lab.com>
Date: Sun, 10 Jul 2005 09:48:21 GMT
Links: << >>  << T >>  << A >>
"JJ" <johnjakson@yahoo.com> wrote in message 
news:1120941973.045383.237510@o13g2000cwo.googlegroups.com...
>I am not really convinced of basic un RTL C to RTL conversion myself,
> since its already possible to write  RTL in C to some degree

The problem is that any HDL language is still timed and you have to sort out 
the concurrency. How many engineers write an algorithm in C/C++ (matlab, 
http://www.accelchip.com/) first before translating it to HDL? probably 
quite a lot (including myself :-).  Using a sequential untimed language like 
C is much easier to learn than any HDL language and for some applications 
far more suited. So why not bypass the whole algorithm to HDL translation 
and go straight to gates, it makes sense to me.

>but why
> don't the plain C to RTL folks  try to persuade me with examples.

Have a look at the free Spark tool http://mesl.ucsd.edu/spark/download.shtml

> My other doubt comes from the fact that for FPGA, HDLs are almost free
> except for large designs and does C bring anything to the table for the
> high end.
> Lets see perhaps a quicksort or other obviously NOT HW type algorithm C
> code from the Sedgewick or any algorithm book along with output and
> give us the synth results without having to touch the HDL code, and
> compare that with hand designed HDL version.

The issue is that you can take a complex algorithm written is a "simple" 
sequential language and then use the synthesis tool to perform architectural 
exploration. Once you start hand coding the algorithm in HDL it is very 
difficult to change the architecture later. I am pretty sure that the HDL 
written quicksort is smaller/faster than the C-translated one, but on a 
similar note it is easier to write quicksort in C than it is in assembly.

>I am curious to know what
> the upfront C tax cost is v potential coding effort savings, and
> relative speed, used resources of the two approaches.

I believe that most arguments will be similar to the assembly/high-level 
language discussions of 2 decades ago.

Personally, I believe in these tools simply because I still code in C first. 
I was also very impressed by the Catapult-C demo at DAC but from what I 
understand the price is the same as for a nice villa in the south of France 
:-)

Hans
www.ht-lab.com

>
> And how does Impulse C compare with Precision C, HandelC, even SystemC,
> are they all using occam/CSP add ons to specify timing and parallelism?
> johnjakson at usa dot com
>
> I'll look out for the book though








Article: 86936
Subject: design does not fit in device
From: nahum_barnea@yahoo.com
Date: 10 Jul 2005 04:18:15 -0700
Links: << >>  << T >>  << A >>

Hi.

I have a design target to xilinx virtex2pro30 device.
In the map stage I get "ERROR:342 design does not fit in device".

But although I run "map -detail", the tool does not give me any details
such as how far I am off the device limitation, in what category my
design does not fit (registers or luts) etc ...

Is there a way to extract this information from the Xilinx ISE tools ?

ThankX,
NAHUM


Article: 86937
Subject: Re: design does not fit in device
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 10 Jul 2005 14:15:29 +0200
Links: << >>  << T >>  << A >>

<nahum_barnea@yahoo.com> schrieb im Newsbeitrag
news:1120994295.239520.89300@f14g2000cwb.googlegroups.com...
>
> Hi.
>
> I have a design target to xilinx virtex2pro30 device.
> In the map stage I get "ERROR:342 design does not fit in device".
>
> But although I run "map -detail", the tool does not give me any details
> such as how far I am off the device limitation, in what category my
> design does not fit (registers or luts) etc ...

Are you sure? Usually it clearly says what kind of component is over
thelimit (LUTs, Slices, BRAMS, BUFGs etc.)
Have a closer look again.

Regards
Falk




Article: 86938
Subject: Quartus Timing Issues
From: "Paul Solomon" <psolomon@tpg.com.au>
Date: Sun, 10 Jul 2005 22:54:18 +1000
Links: << >>  << T >>  << A >>
Hi Guys,

I am a relatively inexperienced user of Quartus (I did a thesis on it and 
now I am mucking around trying to get a FM demod working), and I have run 
into some issues on timing as my design grows large.

I am using a straix part and it is clocked at 80MHz, and I have a number of 
FIR filters in the design. There are currently 2 FIR filters that need to 
run at 80MSPS and then a seriec of filters that these feed into after 
decimation, so these other filters run a lower clock rates.

When I compile etc, the timing analysis gives a stack of critical warnings 
about the signals between the filters not having enough hold time etc. 
however it is basing th necessary hold times on the 80MHz clock (I think). I 
wantd to know how to:

1) Tell the timing analysier that these components are running at different 
clock speeds, and
2) Tell the fitter that 2 filters need to be fit to run at 80MHz and the 
others dont matter so much, so that I dont end up with the 80MSPS filters 
being spread out and not meeting the timing requirements whilst the slow 
ones do.

I hope someone has some clues and that I made sense.

Regards,

Paul 



Article: 86939
Subject: Re: Running prog from PROM
From: m.bodenbach@ifen.com
Date: 10 Jul 2005 07:57:48 -0700
Links: << >>  << T >>  << A >>


Joey schrieb:
> > Hi Joey,
> >
> > if your programm don't fit in the BRAMs (i think you have plb/opb BRAM
> > in your PPC design) you have a problem.
> > It sounds like you use a Memex Eval board. Is this right?
> >
> > Best regards,
> >
> > Michael
>
> Hey Michael, you are great !! IT IS a Memec Eval board and my prog is
> defenitely much bigger than what 8 BRAM blocks could ever hold. Are you
> saying that there is no other possibility, other than running it with a
> debugger. Well thats all I know (I give in that I am new in this field :( )
>
> Joey

Hi Joey,

what type of board do yopu have. Can you send me you design?
With Memec boards it isn't possible to store or read user data from
PROMs, cause the CE pin of the PROM are connected to the DONE pin.

Best regards,

Michael


Article: 86940
Subject: Re: Quartus Timing Issues
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 10 Jul 2005 08:01:29 -0700
Links: << >>  << T >>  << A >>
Paul Solomon wrote:

> I am using a straix part and it is clocked at 80MHz, and I have a number of 
> FIR filters in the design. There are currently 2 FIR filters that need to 
> run at 80MSPS and then a seriec of filters that these feed into after 
> decimation, so these other filters run a lower clock rates.

Consider running everything at 80MHz and use
clock enable inputs where needed for lower
effective rates.

         -- Mike Treseler

Article: 86941
Subject: Re: Max Sample Rate for Signal Tap in Altera Quartus?
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 10 Jul 2005 14:00:04 -0700
Links: << >>  << T >>  << A >>
We are using the Stratix.
joe

Thomas Entner wrote:
> <jjlindula@hotmail.com> schrieb im Newsbeitrag
> news:1120839025.730535.307150@g47g2000cwa.googlegroups.com...
> > Hello,
> >
> > My FPGA is running at 80Mhz and I've heard the max sample rate is
> > 50Mhz, so I just wanted to see if it can go higher.
> >
> > joe
> >
>
> If you have a "modern" FPGA, 80MHz should be no problem for SignalTap...
> 
> Thomas


Article: 86942
Subject: Re: Quartus Timing Issues
From: "Paul Solomon" <psolomon@tpg.com.au>
Date: Mon, 11 Jul 2005 10:27:36 +1000
Links: << >>  << T >>  << A >>
"Mike Treseler" <mike_treseler@comcast.net> wrote in message 
news:B9KdndA-gtbXpUzfRVn-iw@comcast.com...
> Paul Solomon wrote:
>
>> I am using a straix part and it is clocked at 80MHz, and I have a number 
>> of FIR filters in the design. There are currently 2 FIR filters that need 
>> to run at 80MSPS and then a seriec of filters that these feed into after 
>> decimation, so these other filters run a lower clock rates.
>
> Consider running everything at 80MHz and use
> clock enable inputs where needed for lower
> effective rates.
>
>         -- Mike Treseler

Hi Mike,

This seems to have solved my problems, I dont claim to understand how but it 
does seem to work.

Can you explain why this fixes the problem? As I thought forcing all the 
filters to be clocked at 80MHz
would add additional constraints that would lessen the chance of a correct 
fit.

Regards,

Paul 



Article: 86943
Subject: Re: Possible bug in Vertex-4 Rocket-IO?
From: Marko <cantsay@comcast.net>
Date: Sun, 10 Jul 2005 18:37:48 -0700
Links: << >>  << T >>  << A >>
I had good luck with Rocket IO in Virtex2Pro.  I used comma alignment,
bonded two channels together and use the recovered clock to clock
everything in the receiver (except the refclk).  My bit rate was only
about 1Gbps.  In my case, everything worked in simulation and in
hardware.

If you don't use comma alignment, how to you align the serial stream
to the word boundary?  Are you using a standard protocol or custom?

You say this happens in simulation.  I presume you don't have
hardware?  I presume you purchased the smart model extension for
ModelSim?  If so, can you get support from ModelTech and/or Xilinx on
this issue?  Have you followed all the rules for proper simulation.
One rule I remember was that simulation must run at pico-second speed.

Sorry I can't be of more help.


On 9 Jul 2005 14:35:40 -0700, shuo.huang@fibre.com wrote:

>The problem is not data dependent. I did not enable comma alignment.
>This is a single channel application.
>
>Did you have succesfull experience with similar settings?


Article: 86944
Subject: Re: Possible bug in Vertex-4 Rocket-IO?
From: shuo.huang@fibre.com
Date: 10 Jul 2005 22:31:21 -0700
Links: << >>  << T >>  << A >>
Thanks Marko for sharing your experience.

I do not use comma alignment inside the Rocket-IO. I have circuit after
it to do the alignment. I am planning to use Virtex-4 device (if it
works). I do not think there is any hardware available yet.

I used VCS (from Synopsys) to simulate. It takes smartmodel as well. I
am trying to get help from Xilinx for a number of weeks. But I have not
got any helpful solution yet.

I noticed that in Roket-IO model the time scale (time unit definition
in Verilog) is defined in ps. I tried to modify my test bench from ns
to ps. Nothing was changed. In Verilog it is allowed to have different
time scales in different modules. I think the simulation with
smartmodel settings should be correct, because otherwise it would not
work at all. It would not be only at every 40th output.

Thanks for your time. I will post the final result when I have it.


Article: 86945
Subject: Search for FPGA
From: Thomas Reinemann <Thomas.Reinemann@masch-bau.uni-magdeburg.de>
Date: Mon, 11 Jul 2005 09:42:57 +0200
Links: << >>  << T >>  << A >>
Hello,

I'm looking for a small FPGA which needs only one voltage source and has
about 10 kByte internal RAM.Since we have experience with Xilinx, I
would prefer a Spartan, but they need three voltages. That's right?

Bye Tom.

Article: 86946
Subject: new PLD and FPGA devices from Lattice
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 11 Jul 2005 09:46:34 +0200
Links: << >>  << T >>  << A >>
just a pre-pre info:

a press release from Lattice is to be expected this week about some new
products.

New products are both 'sides' from existing FPGAs, eg to lower end and to
higher end.
(the presse release may announce only part of the new devices I am not sure
about this).

The new lowest end FPGAs are well, hmm nice, that I can say - specially as
they have
feature(s) that low end PLDs have never had until now. That feature makes
them really
attractive as target platform for tiny SoftCore processors.
Pricing would be at the same or below Altera MAX2

(Yes, Thomas the IDEAL target silicon for ERIC5 will be available from
Lattice in september, at least that was the target date for the availability
of the member of the new low cost family that would be 'fit' for ERIC5)!

Antti
PS I think I said about much as can :) and for details I also need to wait
for friday to see the actual press release, etc..



Article: 86947
Subject: Re: Search for FPGA
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 11 Jul 2005 09:51:07 +0200
Links: << >>  << T >>  << A >>
"Thomas Reinemann" <Thomas.Reinemann@masch-bau.uni-magdeburg.de> schrieb im
Newsbeitrag news:dat7u2$rtp$1@fuerst.cs.uni-magdeburg.de...
> Hello,
>
> I'm looking for a small FPGA which needs only one voltage source and has
> about 10 kByte internal RAM.Since we have experience with Xilinx, I
> would prefer a Spartan, but they need three voltages. That's right?
>
> Bye Tom.

almost all devices need more than one voltage, with the exception of
LatticeXP that comes in several variants and can be powered from single 3.3V
supply. Ah ok the ProAsic3 is also single voltage capable but to my
knoweledge there is no ProAsic3 shipping at the moment. Butr Lattice XP10
should be already available.

If single voltage is requirement I would go with XP10 it has 24KByte of
BRAMs as well


Antti



Article: 86948
Subject: Re: Search for FPGA
From: Michael Bodenbach <m.bodenbach@ifen.com>
Date: Mon, 11 Jul 2005 07:56:04 GMT
Links: << >>  << T >>  << A >>
Thomas Reinemann wrote:
> Hello,
> 
> I'm looking for a small FPGA which needs only one voltage source and has
> about 10 kByte internal RAM.Since we have experience with Xilinx, I
> would prefer a Spartan, but they need three voltages. That's right?
> 
> Bye Tom.
Hi Tom,

what I/O voltages do you need?
3.3V? 2.5V?.......


Best regards,


Michael

Article: 86949
Subject: Re: Search for FPGA
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 11 Jul 2005 09:24:41 +0100
Links: << >>  << T >>  << A >>
Not so common to find used these days but the older families are still 
available if you must have a low rail count. Otherwise you can reduce your 
rail count by making the I/O operate at the same as Vccint say 2.5V for a 
Spartan-3.

Another way to reduce the pain is to use multi-output regulators. We use TI 
parts TPS70402 for exactly this reason and get two rails out of a fairly 
small package. You can also consider using a diode drop from 3.2/3.3V to 
generate a Vccaux of 2.5V.

John Adair
Enterpoint Ltd. - Home of MINI-CAN, PCI and CAN Development Board.
http://www.enterpoint.co.uk


"Thomas Reinemann" <Thomas.Reinemann@masch-bau.uni-magdeburg.de> wrote in 
message news:dat7u2$rtp$1@fuerst.cs.uni-magdeburg.de...
> Hello,
>
> I'm looking for a small FPGA which needs only one voltage source and has
> about 10 kByte internal RAM.Since we have experience with Xilinx, I
> would prefer a Spartan, but they need three voltages. That's right?
>
> Bye Tom. 





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