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Messages from 21600

Article: 21600
Subject: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
From: z80@ds2.com (Peter)
Date: Sun, 26 Mar 2000 06:50:14 +0000
Links: << >>  << T >>  << A >>

I wonder what would happen if Xilinx dropped the range, or just some
parts?

What other "zero power" solutions are there? There are the static-CMOS
FPGAs, at quite high prices especially by the time you include the
serial EPROM etc. 

I do think someone else makes a "zero power" 22V10, though.

It would be interesting to hear from Xilinx. Even a private email
would be interesting.

>We have the PZ128C in a design and are having extreme difficulties. The
>problem is that Philips seem to have stopped making it, or at least declared
>it obsolete so that Philips dealers no longer have any stock, whereas Xilinx
>don't seem to have ramped up yet ... sigh!


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 21601
Subject: Re: No- FPGA openness
From: ldoolitt@recycle (Larry Doolittle)
Date: 26 Mar 2000 06:54:44 GMT
Links: << >>  << T >>  << A >>
Zoltan Kocsi (root@127.0.0.1) wrote:
: I, by the way, am quite curious why exactly the FPGA vendors keep
: the bitstream info closed ?  Both the "protecting the customers' 
: designs" and the "so that we don't have to support it" are quite
: fishy PR-talk, as has been shown in the thread. 

Simple.  If they released that info to the general public,
they could no longer demand bribes^H^H^H^H^H^Hfees from their
"Software partner program" or whatever they call the arrangement
they have with Synopsis, Mentor, et al.

     - Larry Doolittle   <LRDoolittle@lbl.gov>
Article: 21602
Subject: Re: FPGA openness
From: Ray Andraka <randraka@ids.net>
Date: Sun, 26 Mar 2000 06:56:50 GMT
Links: << >>  << T >>  << A >>
Actually as I recall, Xilinx did end up supporting users who were using the
Neocad tools.  During those couple of years before Neocad was asimilated,
the hotline guys got to asking which tools you were using and they did not
hang up on you if you said Neocad.

Rickman wrote:

> Robert Carney wrote:
> >
> > Rickman <spamgoeshere4@yahoo.com> wrote in message
> > news:38DBF65C.3CFB958A@yahoo.com...
> > .....snip
> > >
> > > As I see it, that is the main reason that a user buys a Xilinx
> > toolset.
> > > You get support directly from the source. I looked at buying
> > Neocad
> > > software years ago and one of the many reasons that I didn't
> > was because
> > > they were "third party" and would never be able to supply a
> > complete
> > > support package. They never made any indication that Xilinx
> > would
> > > support their products in any way. In fact they said that
> > Xilinx
> > > initially was very uncooperative in providing any info on the
> > bitstream
> > > or chip designs. But they worked around that and Xilinx
> > ultimately
> > > decided that it was in their own interests to provide
> > information to
> > > Neocad, very much like what Greg is asking for. Information
> > without
> > > obligation for support.
> > >
> >
> > Didn't they buy Neocad shortly after that?
>
> Xilinx did buy Neocad, but it was some years after they started shipping
> product. But my point was that when Xilinx decided it was in their best
> interest, they provided the support that Neocad needed and that this did
> not obligate them to provide any additional support to the end users.
>
> Also after Xilinx did buy Neocad, they spent literally years reworking
> the software to assimilate it into the Xilinx tools. A large part of
> this was likely to be sure that they could provide the needed support
> for their customers.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21603
Subject: Re: FPGA openness
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 26 Mar 2000 06:57:07 GMT
Links: << >>  << T >>  << A >>
Please, let us terminate this thread.
We have let a guy who describes himself as a "punk kid", and calls some of us
"asshole"  ( an all-time record low point ) monopolize this newsgroup for a week.
Let's ignore him. It's not worth the effort we are wasting here.
Certain people will never be convinvced by a rational argument.
We all have better things to do.
If we just ignore him, even Greg may stop his ranting.

An unmoderated newsgroup is a very fragile thing.
We just had a demonstration how easily it can be crippled.

Peter Alfke

Article: 21604
Subject: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 26 Mar 2000 07:08:24 GMT
Links: << >>  << T >>  << A >>
I will reply on Monday. Please give me a chance to get back to work and do some
investigating.  CoolRunner is alive and well at Xilinx. We are happy, the
ex-Philips developers in Albuq. are happy in the Xilinx camp, and I expect the
user community will be happy...
BTW, I would not call the smaller SpartanXL devices "high-priced", not even with
their SPROM. But they are not a reasonable 22V10 substitute. I remember the
22V10 from 20 years ago at AMD...

Peter Alfke, Xilinx Applications
====================================
Peter wrote:

> I wonder what would happen if Xilinx dropped the range, or just some
> parts?
>
> What other "zero power" solutions are there? There are the static-CMOS
> FPGAs, at quite high prices especially by the time you include the
> serial EPROM etc.
>
> I do think someone else makes a "zero power" 22V10, though.
>
> It would be interesting to hear from Xilinx. Even a private email
> would be interesting.
>
> >We have the PZ128C in a design and are having extreme difficulties. The
> >problem is that Philips seem to have stopped making it, or at least declared
> >it obsolete so that Philips dealers no longer have any stock, whereas Xilinx
> >don't seem to have ramped up yet ... sigh!
>
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 21605
Subject: Re: FPGA openness
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 26 Mar 2000 07:17:39 GMT
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> Actually as I recall, Xilinx did end up supporting users who were using the
> Neocad tools.  During those couple of years before Neocad was asimilated,
> the hotline guys got to asking which tools you were using and they did not
> hang up on you if you said Neocad.

Of course we support everybody using Xilinx chips. It's not because we are
nice guys ( we are! ), but because we have to support our chip business.  I
have even gone so far to help people who bought their XC3000s from ATT/Lucent.
Some of them saw the light and came back to us...

Peter Alfke, Xilinx Applications

Article: 21606
Subject: RTL vs. gate level simulation
From: Taras Zima <tzima1@jps.net>
Date: Sat, 25 Mar 2000 23:21:14 -0800
Links: << >>  << T >>  << A >>
In our design the result of Verilog RTL simulation does not agree with
simulation of the gate level file. We are using Xilinx SpartanXL device
and Modelsim Verilog simulator (Xilinx edition). We have registers with
chip enable inputs and muxes generated by Xilinx Core Generator. The
problem is that after writing to a register and then reading from it we
are getting unknown values. We do not think that there is a timing
problem here since in the test bench we provide planty of time between
assigning values.
Does any one out there have any similar problems? Any help will be
appreciated.

tz

Article: 21607
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 08:05:25 GMT
Links: << >>  << T >>  << A >>
You, sir, should be embarrassed.  You work for a company which has
technology that could probably "catch on" more, and the best way to catch
on is to interest students in it because then they will use your
technology later in bigger better projects.  I come here and ask questions
and before I get rude I'm rudely addressed by you.  That I eventually
become rude myself is of course no credit to myself, but I'm just a punk
kid, I'm not the professional.  Me being an asshole should surprise no
one.
	Do you want me to buy your stuff or not?
	If you ignore me, btw, I will definitely stop.  If you actually
read what I say in these posts it is entirely correcting misconceptions.
I've said "I would rather use my own software even if it's not as good" at
least 3 times, and I've explained that I am after more than just
practicality at least half a dozen times, and I've explained that I am not
advocating that the rest of the world follow my patterns several times,
and I've explained that I have no interest in full-featured place&route
software at least half a dozen times.  I've explained that I have no
interest in writing better software than Xilinx as many times.
	I never explained those things because I think anyone cares, I've
explained those things in response to people asserting (or making
assertions that had the obvious assumptions) that I had thought or said
differently.
	At any rate, I argue that it has not been crippled.  Larry
Doolittle, who has a lot more experience both with FPGAs and with working
with engineers than I do has posted some very interesting material you
should all read (as have some others) and has actually converted someone,
an action that I've never seen happen on usenet (ever).  Even the biggest
fan of big and fat proprietary software has now at least seen a hint that
there are people who believe differently (destroying the myth of consensus
is the first step to freeing the mind), and my questions have been
answered, while not in the way I'd prefer (with bitstream specs or open
source software) with a suggestion to use XLD, which is exactly what I
want (minus the fact that XLD -> bitstream needs DOS, but I can handle
DOS).  They reduced a very difficult problem (how to get the information
I need to obtain satisfaction from your chips) with a practical problem
(how to obtain makebits cheaply and get it to run under DOSemu).
	In other words, while you were flaming me and saying how horrible
a programmer I am (or, alternatively, showing off and saying how great
programmers you Xilinx folk are -- I don't have any doubt of either
statement actually) and how useless all my attempts to gain satisfaction
with Xilinx products will be, some people here have convinced me that I might
be able to obtain satisfaction with Xilinx products.  Who's promoting the
company?  I can make a list of people -- I probably should to send them
thank you letters because I've been quite a hassle here -- but you are
certainly not one of them. 

	I am not too proud of all of my actions here, but let he who is
without fault throw the first stone.

In article <38DDB4E3.8FC65B4@earthlink.net>, Peter Alfke wrote:
>Please, let us terminate this thread.
>We have let a guy who describes himself as a "punk kid", and calls some of us
>"asshole"  ( an all-time record low point ) monopolize this newsgroup for a week.
>Let's ignore him. It's not worth the effort we are wasting here.
>Certain people will never be convinvced by a rational argument.
>We all have better things to do.
>If we just ignore him, even Greg may stop his ranting.
>
>An unmoderated newsgroup is a very fragile thing.
>We just had a demonstration how easily it can be crippled.
>
>Peter Alfke
>
Article: 21608
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 08:09:58 GMT
Links: << >>  << T >>  << A >>
In article <38DDB265.5EB1AFFA@ids.net>, Ray Andraka wrote:
>Naw, Atmel's bitstream is proprietary too.  They do give away the software
>though, so that would avoid the money issue.  A number of years ago I wrote a
>generator for a FIR filter in C that worked right above the bitstream in
>atmel 6K.  That file was ascii, but without the secret decoder ring I don't
>think I'd want to do it either (it was bad enough with information).
>
>That said, the atmel 6K part is not one I'd recommend to a novice designer.
>Its cell is not a LUT, rather it is a collection of gates set up more or less
>as a half adder with a flip-flop on the sum output and with the carry output
>inverted.  A few extra gates in the cell let it realize some but not all
>additional 2 and 3 input boolean functions.  The routing is not real robust,
>so to really take advantage of that array you wind up doing detailed place
>and routing by hand, plus lots of iterations between entry and editor to do
>DeMorgan permutations to make it fit better.  The bitstream is quite a bit
>simpler than xilinx:  Each cell is 16 bits of configuration and there is not
>much extra overhead for the routing, as most of it is nearest neighbor
>connections set by the cell configurations.  Greg, you might have some fun
>with that array, but you might also get rather frustrated/disappointed with
>it if you want to do bit parallel math.  Some of the older papers on my
>website deal with that architecture.  The 40K is a quite different
>architecture.  It uses 4 input LUTs ala xilinx and altera for its cell, which
>makes it considerably easier to use.  The cell is bigger, so it is not as
>fast or as dense (smaller number of cells) as the 6K.  Both support partial
>reconfiguration, as do their tools.  Atmel would be my first choice for an
>application where I needed to do partial reconfiguration and did not require
>fast carrys.

Thank you for the introduction.  I will look more into the Atmel parts.
There sure is a lot of variety in this field.
Article: 21609
Subject: Re: FPGA openness
From: Tom Burgess <tom.burgess@home.com>
Date: Sun, 26 Mar 2000 09:09:31 GMT
Links: << >>  << T >>  << A >>
Despite my better judgment, I feel impelled to point out that though I wholly agree
with the ultimate goal of open information on FPGA internals, I have little
patience with the "rude, ignorant, obnoxious zealot" persona that you are perhaps
unconsciously projecting. Give us all a break, learn something about existing
FPGAs and tools, then resume posting when you have something useful to say. This
is my first and LAST post to this thread, which I hope dies soon, to be reborn 
in time as a rational discourse rather than a level 0 slashdot rantathon.

... And dissin' the Xilinx guru is awesome bad wah - you better watch your step
goin' down those dark alleys to your crib.
 
regards, tom

Greg Alexander wrote:
> 
> You, sir, should be embarrassed.  You work for a company which has
> technology that could probably "catch on" more, and the best way to catch
> on is to interest students in it because then they will use your
>
etc. etc.
Article: 21610
Subject: Re: FPGA & single point failure
From: Tom Burgess <tom.burgess@home.com>
Date: Sun, 26 Mar 2000 09:47:15 GMT
Links: << >>  << T >>  << A >>
Yes, Greg's interpretation makes sense. One solution would be to wire 2
FPGAs in parallel, with independent configuration paths, leaving one
always unconfigured (tri-state). If the host could detect a fault, it could
configure the other one. Of course if any output becomes stuck active, this
doesn't work, so you could use CMOS bus switches, but if these break, you are
screwed. No wonder space shuttle toilets are so expensive ... but then they
have zip-lock baggies to fall back on. (ooof!)

regards, tom

Greg Alexander wrote:
> 
> In article <38DC94F7.D2D0B8D6@home.com>, Tom Burgess wrote:
> >Seeing the lack of responses, I can guess that many were mystified by your
> >use of the unfamiliar terms "clue point" and "redound". The context is
> >not sufficient to make them clear, to me at least. What's disconcerting
> >is that the rest of the message appears to be mostly coherent English.
> 
> My guess is that "clue point" = "key point" -- simple mental error or
> perhaps somehow equivalent term (beats me).  And "redound" is probably a
> synonym for "make redundant," perhaps the word even implies some special
> method (such as having 3 redundant systems and a comparator).  I would
> guess that nobody replied because nobody really knows what type of
> standards he needs in terms of reliability so nobody is confident to say
> "don't worry about it, just assume the FPGA won't break" or etc.  I would
> be very surprised if very many people who have the time to read Usenet are
> familiar enough with REALLY critical apps to have much to say to such a
> general question.
> 
> >EDM wrote:
> >>
> >> I've got a problem with a space mission payload system.  I want to use a
> >> FPGA as a clue point of a payload electronic unit. Can anybody clarify me
> >> how do I manage the concept of "single point failure tolerant" in the
> >> system, If I cannot redound the board where this FPGA is included. Do I
> >> redound the FPGA itself inside the board? Is it possible? And is it normally
> >> foreseen? Or is there anything else that I have to take into account? Or
> >> other good solutions that you can suggest me?
> >>
> >> Thanks for any advice and suggestion you can give me
> >>
> >> --
> >>
> >> edemarchi@hotmail.com
Article: 21611
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 10:11:23 GMT
Links: << >>  << T >>  << A >>
In article <38DDD515.C8C6292A@home.com>, Tom Burgess wrote:
>Despite my better judgment, I feel impelled to point out that though I wholly agree
>with the ultimate goal of open information on FPGA internals, I have little
>patience with the "rude, ignorant, obnoxious zealot" persona that you are perhaps
>unconsciously projecting. Give us all a break, learn something about existing
>FPGAs and tools, then resume posting when you have something useful to say. This

My entire complaint was that they are hiding information, and you are
telling me to obtain information.  I don't think that's very useful.

>is my first and LAST post to this thread, which I hope dies soon, to be reborn 
>in time as a rational discourse rather than a level 0 slashdot rantathon.
>
>... And dissin' the Xilinx guru is awesome bad wah - you better watch your step
>goin' down those dark alleys to your crib.

The Xilinx guru started it.
Article: 21612
Subject: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
From: gerald coe <devantech@devantech.demon.co.uk>
Date: Sun, 26 Mar 2000 11:53:52 +0100
Links: << >>  << T >>  << A >>
In article <8ifqds0ds7q6hg1qic7ehndh6n04tk6vfj@4ax.com>, Peter
<z80@ds2.com> writes
>
>I wonder what would happen if Xilinx dropped the range, or just some
>parts?
>
>What other "zero power" solutions are there? There are the static-CMOS
>FPGAs, at quite high prices especially by the time you include the
>serial EPROM etc. 
>
>I do think someone else makes a "zero power" 22V10, though.
TI makes them, however the price is out of all proportion to the amount
of logic you can get in them.

>
>It would be interesting to hear from Xilinx. Even a private email
>would be interesting.
>
>>We have the PZ128C in a design and are having extreme difficulties. The
>>problem is that Philips seem to have stopped making it, or at least declared
>>it obsolete so that Philips dealers no longer have any stock, whereas Xilinx
>>don't seem to have ramped up yet ... sigh!
>
>
>Peter.
>--
>Return address is invalid to help stop junk mail.
>E-mail replies to zX80@digiYserve.com but remove the X and the Y.
>Please do NOT copy usenet posts to email - it is NOT necessary.

If you need low power rather than zero power, have a look at xilinx's
95xxXL family. For example the 9536XL consumes around 10mA for 36
macrocells. There cheap too.

-- 
Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031,
Gerald Coe      | .demon.co.uk    | 68302, 64180, 80C188EB cpu modules. 
http://www.devantech.demon.co.uk  | Full custom uP control systems designed.
Article: 21613
Subject: Re: FPGA openness
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 26 Mar 2000 08:48:25 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Ray Andraka wrote:
> 
> > Actually as I recall, Xilinx did end up supporting users who were using the
> > Neocad tools.  During those couple of years before Neocad was asimilated,
> > the hotline guys got to asking which tools you were using and they did not
> > hang up on you if you said Neocad.
> 
> Of course we support everybody using Xilinx chips. It's not because we are
> nice guys ( we are! ), but because we have to support our chip business.  I
> have even gone so far to help people who bought their XC3000s from ATT/Lucent.
> Some of them saw the light and came back to us...
> 
> Peter Alfke, Xilinx Applications

I stand corrected. I was not aware that Xilinx ever provided support to
Neocad users. That would have been very special indeed. 

But I think my point is still valid. I doubt that anyone would expect
Xilinx to provide such support. It would be a far reach of the mind for
a user to expect anyone to support the operation of tools that they did
not provide. Again, the analogy would be like asking Intel to support
the GNU tools. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21614
Subject: Re: Clock nets using non-dedicated resources
From: "James C. LaLone" <lalone@worldnet.att.net>
Date: Sun, 26 Mar 2000 15:26:57 GMT
Links: << >>  << T >>  << A >>
In the timing analyzer, select analyze -> clocks.  That should give you
a list of all the nets that the Xilinx tool considers to be clocks.
-Jim

boniolopez@my-deja.com wrote:
> 
> So I have tried to find this clock as you write, but all clock from
> section 8 are using bufG or bufGP.
> 
> I have in my design following construction
> Clock2<=clock1 and enable_clock2
> PIN_probe1<=clock1;
> PIN_probe2<=clock1;
> 
> Clok2 uses BufG, clock1 uses bufGP
> 
> My last question: Do you think that this could be a cause of warnings,
> we are speaking about? (if yes why even this warning)
> regards,
> bonio
> 
> In article <8b5mrk$k76$1@nnrp1.deja.com>,
> boniolopez@my-deja.com wrote:
> > Hi all,
> > I'm not very new in FPGA design but I can't find the issue of
> following
> > problem:
> >
> > WARNING:Timing:33 - Clock nets using non-dedicated resources were
> found
> > in this
> > design. Clock skew on these resources will not be automatically
> > addressed
> > during path analysis. To create a timing report that analyzes clock
> > skew for
> > these paths, run trce with the '-skew' option.
> >
> > I'm quite sure to use in my design the deducted clock resources only
> > (and connected to BufG or Buf GP). I think the syntheses tool can'
> > recognise some part in my design and form it so, that clock some FF
> > with the gated signal. But I cant find where.
> >
> > THE QUESTION: How I can find out where the Alliance 2.1i found the
> non-
> > dedicated resources(which signal is such clock)?
> >
> > Any help will be appreciated,
> > Bonio
> > Remove_this_Bonio.lopez@gmx.ch_remove_this
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
> >
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 21615
Subject: Re: FPGA openness
From: muzo <muzok@nospam.pacbell.net>
Date: 26 Mar 2000 14:57:24 EST
Links: << >>  << T >>  << A >>
Ray,
Maybe a couple of exceptions. Very small groups who understand the
technology well can do wonders, my comments were mostly for large
group efforts. Also I suspect your design is mostly data path in which
it is little bit easier to generate large gate counts because the
system is mostly replicated calculations. complex control logic
development takes more time to develop and verify.
Also in my experience an FPGA gate is 4 to 5 times less dense than an
standard cell gate.

Ray Andraka <randraka@ids.net> wrote:

>
>
>muzo wrote:
>
>> ...
>> designing with ones and zeros. With million gate SoC designs, you
>> can't fill a chip by desiging at the level of 2x1 muxes or JK
>> flip-flops. You have to use HDLs and behavioral compilers etc.
>
>Not so!  I think it is much more important to make heavy use of hierarchy so
>that you can reuse design pieces.  Even where I am using HDLs, I'm still
>doing alot of low level design (down at the primitives level).  And yes, I
>am doing million gate designs.  I'm just finishing one now that reports
>999,376 equivalent gates at the tools output in the fuller chip of the two
>chip design - it runs at 134MHz in a 70 % full Virtex1000 -4.  Guess what?
>A good deal of the design was done at the primitive level complete with
>floorplanning in the VHDL source.  How long did it take?  about 600 hours
>including design verification. About 20% of that time was algorithm
>development in Matlab.

Article: 21616
Subject: Re: FPGA openness
From: muzo <muzok@nospam.pacbell.net>
Date: 26 Mar 2000 15:00:51 EST
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:

>On 24 Mar 2000 15:33:09 EST, muzo <muzok@nospam.pacbell.net> wrote:
>
>>Theron Hicks <hicksthe@egr.msu.edu> wrote:
>>>> I've been doing some interviewing recently, for VHDL people. All were
>>>> electronic engineers, and also claimed to know and use VHDL. Out of
>>>> about 10 or 12 people:
>>>>
>>>> (1) about half couldn't draw up a gate-level 2->1 multiplexer
>>>> (2) most didn't know what a JK was
>>>> (3) almost nobody could design a gate-level counter, or
>>>> (4) knew how to create an FSM from scratch, with pencil and paper
>>>> (5) very few knew anything about line termination
>>>> and so on.
>>
>>this reminds me the dilbert cartoon where a couple of bearded, bald
>>guys talk about having to code only with ones and zeros and dilbert
>>tops them off with "then you are lucky, we didn't even have ones. We
>>had to write code only with zeros". Most people these days are not
>>designing with ones and zeros. With million gate SoC designs, you
>>can't fill a chip by desiging at the level of 2x1 muxes or JK
>>flip-flops. You have to use HDLs and behavioral compilers etc.
>
>I can't agree. I use HDLs all the time, to fill "million gate"
>devices. 

So I am suggesting that we need to use HDLs and higher level
abstraction tools to develop "million gate" chips, you say you do that
all the time and still disagree with me ?

> HDLs and behavioural compilers are just tools. You can
>have the best chisel in the world, but it's not going to turn you into
>Michelangelo.

Here I am assuming reasonably competent engineers and suggesting that
HDLs and other better tools give them an edge in designing complex
systems with a fast TTM. No tool has ever made an idiot into a good
designer.
Article: 21617
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 20:40:56 GMT
Links: << >>  << T >>  << A >>
In article <38DE1529.F491AE42@yahoo.com>, Rickman wrote:
>Peter Alfke wrote:
>> 
>> Ray Andraka wrote:
>> 
>> > Actually as I recall, Xilinx did end up supporting users who were using the
>> > Neocad tools.  During those couple of years before Neocad was asimilated,
>> > the hotline guys got to asking which tools you were using and they did not
>> > hang up on you if you said Neocad.
>> 
>> Of course we support everybody using Xilinx chips. It's not because we are
>> nice guys ( we are! ), but because we have to support our chip business.  I
>> have even gone so far to help people who bought their XC3000s from ATT/Lucent.
>> Some of them saw the light and came back to us...
>> 
>> Peter Alfke, Xilinx Applications
>
>I stand corrected. I was not aware that Xilinx ever provided support to
>Neocad users. That would have been very special indeed. 
>
>But I think my point is still valid. I doubt that anyone would expect
>Xilinx to provide such support. It would be a far reach of the mind for
>a user to expect anyone to support the operation of tools that they did
>not provide. Again, the analogy would be like asking Intel to support
>the GNU tools. 

Not really, since Intel releases specs to allow the GNU tools to exist.
The analogy would only be complete if Xilinx opened up their specs.
Perhaps any company which keeps closed specs /does/ have a responsibility
to help people who use third party tools developed through reverse
engineering.  It doesn't make any sense, but it explains why Intel doesn't
feel responsibility to support GNU tools while Xilinx does feel
responsibility to support Neocad.
Article: 21618
Subject: Re: FPGA & single point failure
From: Greg Neff <gregneff@my-deja.com>
Date: Sun, 26 Mar 2000 22:35:15 GMT
Links: << >>  << T >>  << A >>
In article <38DC94F7.D2D0B8D6@home.com>,
Tom Burgess <tom.burgess@home.com> wrote:
> Seeing the lack of responses, I can guess that many were mystified by
your
> use of the unfamiliar terms "clue point" and "redound". The context is
> not sufficient to make them clear, to me at least. What's
disconcerting
> is that the rest of the message appears to be mostly coherent English.
>
(snip)

This is a new one on me too.  I did a little digging:

From Merriam-Webster ( http://www.m-w.com/dictionary.htm )

Main Entry: re·dound
Pronunciation: ri-'daund
Function: intransitive verb
Etymology: Middle English, from Middle French redonder, from Latin
redundare, from re-, red- re- + unda wave -- more at WATER
Date: 14th century
1 archaic : to become swollen : OVERFLOW
2 : to have an effect for good or ill <new power alignments which may
or may not redound to the faculty's benefit -- G. W. Bonham>
3 : to become transferred or added : ACCRUE
4 : REBOUND, REFLECT

This didn't help me understand the question, but maybe this will help
someone else get it...

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21619
Subject: Re: FPGA openness
From: ldoolitt@recycle (Larry Doolittle)
Date: 26 Mar 2000 23:17:07 GMT
Links: << >>  << T >>  << A >>
Peter Alfke (palfke@earthlink.net) wrote:
: Please, let us terminate this thread.

Um, why?  Because people might actually learn something about Xilinx
XDL, and what Xilinx does and does not keep as a proprietary secret?

: We have let a guy who describes himself as a "punk kid", and calls some of us
: "asshole"  ( an all-time record low point ) monopolize this newsgroup for a week.

Hey, at least he apologized.

: Let's ignore him. It's not worth the effort we are wasting here.
: Certain people will never be convinvced by a rational argument.

And what, exactly, are you "rationally arguing" he do?
He wants to study the internals of an FPGA on a development
board he bought (or might buy), in the hopes of making it
do something |<ewl.  Do you know of an FPGA vendor that
will let him do that?  Why would you want to ignore a
person with such a goal?  I have some ideas, but would
like to see someone from a corporate FPGA entity come out
and say it for everyone to hear.  No marketing-speak, please.

: If we just ignore him, even Greg may stop his ranting.

His ranting went toe-to-toe with the people who told him
he was an idiot for asking for programming information on
a chip.  Have any of those people apologized?

: An unmoderated newsgroup is a very fragile thing.
: We just had a demonstration how easily it can be crippled.

Oh, hoh!  Does this mean Xilinx would like discussions like
this censored?  Let's wait until AOL-Time-Warner buys Xilinx,
and then see what happens to discussions like this!

    - Larry Doolittle   <LRDoolittle@lbl.gov>
      (You bet I'm speaking for myself.  lbl.gov is as risk-averse
       and tied in with proprietary design tools as any company.)
Article: 21620
Subject: FPGA open source
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Sun, 26 Mar 2000 16:54:18 -0700
Links: << >>  << T >>  << A >>
One advantage of open source information of the programming formats is
that you can "clone" the chip. Second source-ing of FPGA's does not seem
to be available except for the small PAL'S.
Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
The Lagging edge of technology:
http://www.jetnet.ab.ca/users/bfranchuk/woodelf/index.html
Article: 21621
Subject: Virtex DLL Spread-spectrum clock sensitivity
From: jjcook@ews.uiuc.edu (jeffrey j cook)
Date: Mon, 27 Mar 2000 00:27:29 GMT
Links: << >>  << T >>  << A >>
Is anyone aware of any hindering issues of using a spread-spectrum clock when
driving the Virtex, especially when it comes to using the DLL's?

Thanks.

Jeffrey J. Cook
jjc@ieee.org
-- 
"Sometimes the easiest way to get something done is to be a little naļve
about it -- and just ship it."
Bill Joy, Sun Microsystems  - Jini Engineer
Article: 21622
Subject: Re: Clock on non-dedicate pin
From: spyng@my-deja.com
Date: Mon, 27 Mar 2000 01:31:07 GMT
Links: << >>  << T >>  << A >>
I am using virtex xcv 1000 from Xilinx, and foundation series for
development.

thanks
spyng

In article <38DC9ED1.61E4EBFA@sigma.krakow.pl>,
Jaroslaw Kubica <jkubica@sigma.krakow.pl> wrote:
> What is the type of your FPGA device and what tools do you use?
> Regards,
> Jarek
>
> spyng@my-deja.com wrote:
>
> > hi,
> >
> > other than GCK0-3, is there anyway to have a clock signal without
> > using dedicate Pin?
> >
> > I need to input two external clock to my FPGA board, but
unfortunately
> > the board is design such that only one external clock is possible.
> > So, i am trying to inject the second external clock to a I/O, but
the
> > design refuse to map.
> >
> > skew of the second clock is not important to me, I just want a clock
> > in a normal I/O pin!
> >
> > thanks
> > spyng
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21623
Subject: [co-design] HW/SW co-design
From: "tasi" <tasi@emc.com.tw>
Date: 27 Mar 2000 01:47:24 GMT
Links: << >>  << T >>  << A >>
Dear All

I have questions about HW/SW co-design.
Could somebody tell me the experience about this topic? or
tell me how to get the related information?
Thanks!!

mail to tasi@mafia.ee.ccu.edu.tw



Article: 21624
Subject: Re: FPGA open source
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 26 Mar 2000 22:11:42 -0500
Links: << >>  << T >>  << A >>
Ben Franchuk wrote:
> 
> One advantage of open source information of the programming formats is
> that you can "clone" the chip. Second source-ing of FPGA's does not seem
> to be available except for the small PAL'S.
> Ben.
> --
> "We do not inherit our time on this planet from our parents...
>  We borrow it from our children."
> The Lagging edge of technology:
> http://www.jetnet.ab.ca/users/bfranchuk/woodelf/index.html

Actually that would likely never happen. Most of the important features
of a chip like this are patented, so that even if they tell you exactly
how it is made or even if they gave you the masks, you can't make a chip
using the same features or you will violate patent law. 

But don't think this is why the FPGA companies keep the bit formats a
secret. As most everyone in this thread is aware, any competitor worth
their salt will have reverse engineered the product (not to mention
reading your patents!) and already know nearly as much as the designers. 

Peter told you most of the reason that they don't release the info.
Because they don't want to have to deal with calls from people saying,
"I read you bitstream info and I can't get my chip to work!". Now you or
Greg might never want to call Xilinx about such issues, but that doesn't
mean that others (like the head in the mud hardware designers) won't
call them about this. 

To Peter, I will have to say that one good thing that has come out of
this thread is that I have a much better appreciation of what Xilinx
already has to deal with in support. I have always thought that support
was just a matter of training your people to use the tools, but now I
realize that there is much more to it than that. I guess even though you
have tried to limit the range of the levels of support you need to
provide, there are always users out there that come up with things you
could never have thought of. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com


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