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Messages from 11725

Article: 11725
Subject: WANTED: Characteristic models for JTAG (IEEE 1149.1) development
From: Bob Burk <robert.c.burk@tek.com>
Date: Thu, 03 Sep 1998 17:51:55 -0700
Links: << >>  << T >>  << A >>
I am looking for files to support my JTAG development project.
Does anyone know where to find a library of characteristic models
(char files) to describe non-JTAG parts around my JTAG chain?
For the time it takes to model each device, I would think someone,
somewhere has already done this work and share/sell their efforts.

If you know any sources, please e-mail robert.c.burk@tek.com.
Thanks.
Article: 11726
Subject: Xilinx CLPD
From: remy@provide.net
Date: Fri, 04 Sep 1998 03:20:53 GMT
Links: << >>  << T >>  << A >>
I am new to the programmable logic game and have recently purchased
the $95 Xilinx software. I am using one of the 9500 series CLPD's with
schematic entry. All I need for eternal peace is a 4-digit divide by N
counter to be programmed with 4 BCD thumbwheel switches to divide from
1 to 9,999. I would be GREATLY grateful for any help! Thank you very
Much....

Jim Remy

remy@provide.net

Article: 11727
Subject: Re: FIFO Design problem
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Sep 1998 00:30:50 -0400
Links: << >>  << T >>  << A >>
YongKook Kim wrote:
> 
> Hi, Everybody!
> 
> I'm trying to implement a FIFO that interfacing MASTER and SLAVE, which
> can do Burst accesses.
> 
> It is available for both MASTER and SLAVE to Write and Read
> simultaneoulsy, for example, Master is trying burst write to Slave and
> Wirting to FIFO, and after a clock  Slave is trying read from FIFO which
> master has written to it.(at the same time Master is writing to FIFO
> with another address!)
> 
> Any ideas will be appreciable, Thank you .

This is not hard. But there are some questions. Are the two interfaces
running from the same or different clocks? What is the speed of the
clocks? What is the duty cycle of the data in and out? How deep does the
FIFO need to be? You seem to describe a FIFO with a one clock latency.
Can you accept a longer latency?


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 11728
Subject: How to use fpga do a sync/async converter
From: lck@tainet.com.tw (richard lee)
Date: Fri, 04 Sep 1998 05:45:31 GMT
Links: << >>  << T >>  << A >>

How to use fpga do a sync/async converter.
One compont gen sync serial data stream to async interface(rs232)
without  move from CPU.data stream to converter to async interface.

best regard.
		9/4       richard lee
Article: 11729
Subject: Where to buy Atmel AT17C256 (i only needs a dozen)
From: THIEBOLT Francois <thiebolt@irit.fr>
Date: Fri, 04 Sep 1998 13:57:29 +0200
Links: << >>  << T >>  << A >>
Hi,

I'm trying to find a replacement for XILINX PROMs which ATMEL seems to
be quite a good competitor...till they sell 50 parts each time...i only
need a dozen parts...so what to do now ?

Thanks for your help.

-- 
-------------------------------------------------------------
THIEBOLT Francois \ You think your computer run too slow ?
UPS Toulouse III  \ - Check nobody's asked for tea !
thiebolt@irit.fr  \ "The Hitchikers Guide to the Galaxy" D.Adams
-------------------------------------------------------------
Article: 11730
Subject: Re: Digital PLL
From: z80@ds2.com (Peter)
Date: Fri, 04 Sep 1998 12:39:14 GMT
Links: << >>  << T >>  << A >>
Thank you for a very interesting post.

I have used the SCC to decode manchester data and for that it works
very well. OTOH as you say this is not hard to do anyway.

--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 11731
Subject: Re: FIFO Design problem
From: tom_schaal@my-dejanews.com
Date: Fri, 04 Sep 1998 13:52:15 GMT
Links: << >>  << T >>  << A >>
Look at the xilinx app notes on fifos.	They do a good job on this issue. 
The appnotes are distributed on CD-ROM quarterly and are also available on
the web.

Tom Schaal


In article <35EF6CFA.680DF088@yahoo.com>,
  Rickman <spamgoeshere4@yahoo.com> wrote:
> YongKook Kim wrote:
> >
> > Hi, Everybody!
> >
> > I'm trying to implement a FIFO that interfacing MASTER and SLAVE, which
> > can do Burst accesses.
> >
> > It is available for both MASTER and SLAVE to Write and Read
> > simultaneoulsy, for example, Master is trying burst write to Slave and
> > Wirting to FIFO, and after a clock  Slave is trying read from FIFO which
> > master has written to it.(at the same time Master is writing to FIFO
> > with another address!)
> >
> > Any ideas will be appreciable, Thank you .
>
> This is not hard. But there are some questions. Are the two interfaces
> running from the same or different clocks? What is the speed of the
> clocks? What is the duty cycle of the data in and out? How deep does the
> FIFO need to be? You seem to describe a FIFO with a one clock latency.
> Can you accept a longer latency?
>
> --
>
> Rick Collins
>
> redsp@XYusa.net
>
> remove the XY to email me.
>

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11732
Subject: Re: Wait statements and while loops
From: "David L. Pearson" <dpears01@harris.com>
Date: Fri, 04 Sep 1998 11:24:14 -0400
Links: << >>  << T >>  << A >>
Phillip Cook wrote:
> 
> I am writing a VHDL model to be synthesized and compiled using
> OrCAD Express. The model synthesizes but when I try to compile
> I get two errors that are going to cause me a lot of trouble.
> 
> 1) It says that it cant compile a while loop
> 
> 2) It says that it cant compile multiple wait statements in the
>    one process.
> 
> Are these standard VHDL restrictions or is it just an OrCAD
> restriction?  Is there any easy way to get around these probs?
> 
> TIA
> Phil.

There seem to be two distinct types of people in this news group: the old bit slingers (like myself) who understand gates and registers, and 
software types who like their VHDL to look like C. If you tackle real life synthesizable designs from the nuts and bolts standpoint, you will 
realize that


1) You could never buy a WAIT gate in the days of TTL. Delays inside FPGAs or ASICs need to be synchonous.
2) A WHILE simply involves using a flip-flop that sets or clears at particular events and enables or disables a process, i.e
	if(reset = '1') then
		while <= '0';
	elsif (clk'event and clk = '1') then -- rising edge trigger
		if (start_event = '1') then
			while <= '1';
		elsif( stop_event = '1') then 
			while <= '0';
		end if;
	end if;
	if (while = '1') then
		{ Body of WHILE loop }
	end if;

3) A FOR uses a down-counter that is preset on a start event, steps on a particular step event and ends when the counter hits zero, i.e.
	if(reset = '1') then
		for_count <= "0000";
		for	  <= '0';
	elsif (clk'event and clk = '1') then 
		if(start event = '1') then
			for_count <= preset_value; -- preset_value needs to be defined elsewhere
			for	  <= '1';
		if (for = '1') then
			if (for_count = "0000") then
				for <= '0';
			end if;
			if (step_event = '1') then
				for_count <= for_count - "0001"
			end if;
		end if;
	end if; 


Every synthesis tool understands if statements. Boolean equivalents of ifs also work well, i.e.
	while <= (start_event and (not while)) or (not (stop_event and while));


Dave P.
Article: 11733
Subject: Re: CPLD/FPGA software
From: "David L. Pearson" <dpears01@harris.com>
Date: Fri, 04 Sep 1998 11:33:08 -0400
Links: << >>  << T >>  << A >>
Depending on how much density you need, Vantis MACH parts may be the 
answer. They offer their basic tools as freeware and they program via a 
JTAG port after assembly.

Dave P.
Article: 11734
Subject: URGENT REQUIREMENT FOR ALTERA PART
From: simonot@chollian.dacom.co.kr (Hansen Hong)
Date: Fri, 04 Sep 1998 20:32:04 GMT
Links: << >>  << T >>  << A >>
Hi folks?

I have an urgent requirement for an Altera part. This is critical for
a project that I am currently undertaking. I'd appreciate very much if
anyone can provide me with any information regarding who might 
have this on stock for sale.

Model Number : epf10k100ari240-3	
Required Quantity : 26 pcs.

Thanks
Hansen
Article: 11735
Subject: Re: FPGA Manufacturer's gate counts
From: app01@aol.com (APP01)
Date: 5 Sep 1998 00:16:01 GMT
Links: << >>  << T >>  << A >>
For Lucent Orca family it is does as  follows. Assume 30% RAM, 70% logic, then
add 4 gates per RAM bit and sum it all up. That is how they calculate their
OR2C/T family.. Also, Lucent now shows a range of gates for each devices based
upon pure logic which is the lower number, upto 30% ram whicg is the hither
number (i.e. a 2T40A is 40k gates, but the ranmge advertised is 35kgates to 99k
gates)

There used to be a white paper on Altera's site describing how they did it, and
after it was puiblished, Xilinx, and Lucent started advertising in the same
manner.

I hope this helps 

Tony
Article: 11736
Subject: Architect Postions @ Lucent Technologies
From: ejob <people@ejob.com>
Date: Fri, 04 Sep 1998 21:27:44 -0700
Links: << >>  << T >>  << A >>

--------------803F6FDF7C94E5967ADE3DB8
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Location: Murray Hill,  New Jersey

For more information, please visit Lucent on ejob.

http://www.ejob.com/lucent3.htm

--------------803F6FDF7C94E5967ADE3DB8
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML>

<DL><B><FONT COLOR="#000099">Location: Murray Hill,&nbsp; New Jersey</FONT></B><B><FONT COLOR="#000099"></FONT></B>
<P><B><FONT COLOR="#000099">For more information, please visit Lucent on
ejob.</FONT></B><B><FONT COLOR="#000099"></FONT></B>
<P><B><FONT COLOR="#000099"><A HREF="http://www.ejob.com/lucent3.htm">http://www.ejob.com/lucent3.htm</A></FONT></B></DL>
</HTML>

--------------803F6FDF7C94E5967ADE3DB8--

Article: 11737
Subject: WE MASS E-MAIL YOUR EXCLUSIVE AD TO 900k - $99
From: massmail@aol.com
Date: 5 Sep 1998 05:28:41 GMT
Links: << >>  << T >>  << A >>

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Article: 11738
Subject: 22V10 programming
From: Raymond Chiu <chiu@gate.net>
Date: Sat, 05 Sep 1998 18:22:19 -0500
Links: << >>  << T >>  << A >>
Suggestions to my question are greatly appreciated.

I am interesting in learning to program simple PLDs (22V10s).  Is there
a low cost ($100) package that can program these quickly/easily?

Thanks,
Raymond Chiu

Article: 11739
Subject: Re: professional autorouters
From: Randy Yates <yates@shadow.net>
Date: Sat, 05 Sep 1998 22:28:41 -0400
Links: << >>  << T >>  << A >>
Seth Goodman wrote:
> 
> I find that the Specctra autorouter from CCT is excellent if you are willing
> to spend the time to tell it what is important.  However, rather than go
> with blind and buried vias, I would suggest adding more layers or tightening
> the design rules (if your fabricators allow you to).  These via types are
> wonderful in concept but are seldom used due to yield problems.  But if you
> must, there are board houses that can fabricate them and Specctra does
> support them.
> 
> Seth Goodman
> Goodman & Associates
> Verona, WI
> USA

I second both Seth's recommendation (the Spectra autorouter) and his caveats.
The Spectra router is available as an option with the Accel EDA design
tools. 

-- 
% Randy Yates                   % "Though you ride on the wheels of tomorrow,
%% DIGITAL SOUND LABS           %  you still wander the fields of your
%%% Digital Audio Sig. Proc.    %  sorrow."
%%%% <yates@shadow.net>         % '21st Century Man', *Time*, ELO
http://www.shadow.net/~yates  <yatesc@pcmail.systems.gec.com>
Article: 11740
Subject: Re: 22V10 programming
From: "Cheese ][" <yourmail@company.com>
Date: Sun, 6 Sep 1998 01:32:36 -0400
Links: << >>  << T >>  << A >>
I think AMD made PALASM freeware. It's pretty easy to learn.

Raymond Chiu wrote in message <35F1B99A.34874E83@gate.net>...
>Suggestions to my question are greatly appreciated.
>
>I am interesting in learning to program simple PLDs (22V10s).  Is there
>a low cost ($100) package that can program these quickly/easily?
>
>Thanks,
>Raymond Chiu
>


Article: 11741
Subject: Re: 22V10 programming
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Sun, 6 Sep 1998 01:15:08 -0700
Links: << >>  << T >>  << A >>
Cheese ][ wrote in message <6st6s8$b9i$1@usenet41.supernews.com>...
>I think AMD made PALASM freeware. It's pretty easy to learn.

They also spun their programmable logic division off into Vantis, who gives
away Synario's ABEL synthesis tool that's able to target simple PLDs
(including the 22V10) and Vantis' lower end CPLDs.  It's a pretty good
package, given the price (zip).

It also seems that Raymond may be interested in actually getting his PLDs
physically programmed.  I don't have a specific suggestion there, although I
have seen plenty of used legacy "universal programmers" for well under $100.
While no longer "universal," anything less than 10 years old will probably
have no problem programming a 22V10.

---Joel Kolstad




Article: 11742
Subject: Re: lookup table for mult/div
From: Nick Hartl <"nhartl[no_spam]"@earthlink.net>
Date: Sun, 06 Sep 1998 03:19:19 -0500
Links: << >>  << T >>  << A >>
Try this:
http://www.xilinx.com/appnotes/dspguide.pdf

Park Chan Ik wrote:

> Hi.
>
> I am looking for the lookup table method to accelerate the
> multiplication and division.
> How can I make effective tables for them?
> I will wait for precious advice.
> Thanks.



Article: 11743
Subject: Re: 22V10 programming
From: z80@ds2.com (Peter)
Date: Sun, 06 Sep 1998 21:58:10 GMT
Links: << >>  << T >>  << A >>

>It also seems that Raymond may be interested in actually getting his PLDs
>physically programmed.  I don't have a specific suggestion there, although I
>have seen plenty of used legacy "universal programmers" for well under $100.
>While no longer "universal," anything less than 10 years old will probably
>have no problem programming a 22V10.

Need to be careful here, since almost every vendor's 22V10 has a
different programming algorithm.

You need to make sure the programmer supports the *specific*
vendor/device you want to use. And get it in writing, in case the
algorithm is duff.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 11744
Subject: Altera 10K20 Register File Implementation??
From: b_rich2@my-dejanews.com
Date: Mon, 07 Sep 1998 01:12:45 GMT
Links: << >>  << T >>  << A >>
Hi,  I am a student and am currently designing a register file in Altera 7.21
to be used in a project I am undertaking (non-commercial).  I have a question
about whether there is a better way of implementing than what I am currently
doing. I have 16 X 16bit registers which I have constructed out of 16 X
LPM_FF (D type, 16 bits wide). So this takes up 256 LC's which is okay. But
here's the problem. I need 2 Output data buses from the register file.	I am
currently using 2 X LPM_MUX (16 lines X 16 bit) to select which registers to
put on the bus. I have tested and simulated this design and it works okay.
The problem is that the 2 MUX's take up 416 LC's!! My whole register file
takes up 688 LC's, which is 59% of the space on my device!! This doesn't
leave me with much room for the rest of my project. I haven't completed my
project yet, but it appears I will be really struggling for space, and I am
required to use the 10K20.  Surely there would have to be a better way of
designing a register file than what I have done, but I just can't seem to
think of a better way. I've been working on this problem now for several
weeks and am not making any progress. If there is anyone out there who would
be able to give me some advice I would be eternally grateful. Thanks in
advance. Bruce.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11745
Subject: Re: 22V10 programming
From: Raymond Chiu <chiu@gate.net>
Date: Sun, 06 Sep 1998 23:58:23 -0400
Links: << >>  << T >>  << A >>
The group assessment is correct: I am interested in having a PLD burned, which
means I need to make a decision a burner.  I am having difficulty finding a
burner within my budget ($2000 is a little too rich).

Any suggestions are welcome and appreciated.

Thank you,
Raymond

Peter wrote:

> >It also seems that Raymond may be interested in actually getting his PLDs
> >physically programmed.  I don't have a specific suggestion there, although I
> >have seen plenty of used legacy "universal programmers" for well under $100.
> >While no longer "universal," anything less than 10 years old will probably
> >have no problem programming a 22V10.
>
> Need to be careful here, since almost every vendor's 22V10 has a
> different programming algorithm.
>
> You need to make sure the programmer supports the *specific*
> vendor/device you want to use. And get it in writing, in case the
> algorithm is duff.
>
> --
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but
> remove the X and the Y.



Reply-To: <Ernest Chiu>
Article: 11746
Subject: Re: 22V10 programming
From: msimon@tefbbs.com
Date: Mon, 07 Sep 1998 05:21:26 GMT
Links: << >>  << T >>  << A >>
JDR Micro Devices - has a few burners. Reasonable prices good service.

Simon
============================================
Raymond Chiu <chiu@gate.net> wrote:

>The group assessment is correct: I am interested in having a PLD burned, which
>means I need to make a decision a burner.  I am having difficulty finding a
>burner within my budget ($2000 is a little too rich).
>
>Any suggestions are welcome and appreciated.
>
>Thank you,
>Raymond
>
>Peter wrote:
>
>> >It also seems that Raymond may be interested in actually getting his PLDs
>> >physically programmed.  I don't have a specific suggestion there, although I
>> >have seen plenty of used legacy "universal programmers" for well under $100.
>> >While no longer "universal," anything less than 10 years old will probably
>> >have no problem programming a 22V10.
>>
>> Need to be careful here, since almost every vendor's 22V10 has a
>> different programming algorithm.
>>
>> You need to make sure the programmer supports the *specific*
>> vendor/device you want to use. And get it in writing, in case the
>> algorithm is duff.
>>
>> --
>> Peter.
>>
>> Return address is invalid to help stop junk mail.
>> E-mail replies to zX80@digiYserve.com but
>> remove the X and the Y.
>
>
>

Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.
Article: 11747
Subject: Re: Altera 10K20 Register File Implementation??
From: "Matthew Morris" <mmorris@no_spam.carrieraccess.com>
Date: Mon, 7 Sep 1998 00:07:27 -0600
Links: << >>  << T >>  << A >>
the 10K family has embedded memory use LPM_RAM

b_rich2@my-dejanews.com wrote in message
<6svbud$7cf$1@nnrp1.dejanews.com>...
>Hi,  I am a student and am currently designing a register file in Altera
7.21
>to be used in a project I am undertaking (non-commercial).  I have a
question
>about whether there is a better way of implementing than what I am
currently
>doing. I have 16 X 16bit registers which I have constructed out of 16 X
>LPM_FF (D type, 16 bits wide). So this takes up 256 LC's which is okay. But
>here's the problem. I need 2 Output data buses from the register file. I am
>currently using 2 X LPM_MUX (16 lines X 16 bit) to select which registers
to
>put on the bus. I have tested and simulated this design and it works okay.
>The problem is that the 2 MUX's take up 416 LC's!! My whole register file
>takes up 688 LC's, which is 59% of the space on my device!! This doesn't
>leave me with much room for the rest of my project. I haven't completed my
>project yet, but it appears I will be really struggling for space, and I am
>required to use the 10K20.  Surely there would have to be a better way of
>designing a register file than what I have done, but I just can't seem to
>think of a better way. I've been working on this problem now for several
>weeks and am not making any progress. If there is anyone out there who
would
>be able to give me some advice I would be eternally grateful. Thanks in
>advance. Bruce.
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum


Article: 11748
Subject: Re: Altera 10K20 Register File Implementation??
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Sun, 6 Sep 1998 23:29:17 -0700
Links: << >>  << T >>  << A >>
b_rich2@my-dejanews.com wrote in message
<6svbud$7cf$1@nnrp1.dejanews.com>...
>Hi,  I am a student and am currently designing a register file in Altera
7.21
>to be used in a project I am undertaking (non-commercial).

Good for you!

>The problem is that the 2 MUX's take up 416 LC's!! My whole register file
>takes up 688 LC's, which is 59% of the space on my device!! This doesn't

It is indeed inefficient to build a substantial register file without resort
to embedded RAM of some kind.  For example, a single ported 32x32 register
file requires 32 CLBs, no horizontal interconnect, and one CLB gate delay in
an XC4000, versus ~1000 cells, much horizontal interconnect, and five cell
gate delays in an XC6200.


Here are three ideas for you.

1. Halve the area, double the latency: build only one 16-bit wide 16-to-1
mux and take two cycles to read the two operands.

2. 1/32 of the area, 32X the latency: build a 16-bit 16-word shift register.
She'll be coming around the mountain when she comes.

3. Use EABs.  Here are some old postings of mine on this subject:
http://x1.dejanews.com/getdoc.xp?AN=280290025
http://x1.dejanews.com/getdoc.xp?AN=336757776
Summary: in a 10K (not 10KE), a 2-read 1-write 16-bit-wide register file
should require 6 cycles (one 256x8 EAB) or 3 cycles (two 256x8 EABs).

Bonus marks: if you use EABs, you will now have an embarrassment of
riches -- registers, at least 128.  Consider a stack cache, register window,
or multi-context architecture.

Jan Gray



Article: 11749
Subject: Re: Altera 10K20 Register File Implementation??
From: b_rich2@my-dejanews.com
Date: Mon, 07 Sep 1998 10:53:10 GMT
Links: << >>  << T >>  << A >>
In article <35f3780f.0@news3.uswest.net>,
  <Ernest Chiu> wrote:
> the 10K family has embedded memory use LPM_RAM

I actually looked at the LPM_RAM_DQ but I need 2 read data ports and the
LPM_RAM only provided one. Also it's a bugger that it doesn't address the
read and write ports seperately. You can't read a seperate port at the same
time you are writing data. It would be perfect if it had 1 16 bit data input
bus, 4 bit write address bus, 2 X 16 bit data read busses. That's what my
design has at the moment but I would like a way that doesn't use as much real
estate on the chip. My design is 5 stage pipelined, so I really need single
clock cycle register file too.	Still thinking of alternatives. Thanks for
any help and also for the replies I've received so far, very much
appreciated. Cheers, Bruce

>
> b_rich2@my-dejanews.com wrote in message
> <6svbud$7cf$1@nnrp1.dejanews.com>...
> >Hi,  I am a student and am currently designing a register file in Altera
> 7.21
> >to be used in a project I am undertaking (non-commercial).  I have a
> question
> >about whether there is a better way of implementing than what I am
> currently
> >doing. I have 16 X 16bit registers which I have constructed out of 16 X
> >LPM_FF (D type, 16 bits wide). So this takes up 256 LC's which is okay. But
> >here's the problem. I need 2 Output data buses from the register file. I am
> >currently using 2 X LPM_MUX (16 lines X 16 bit) to select which registers
> to
> >put on the bus. I have tested and simulated this design and it works okay.
> >The problem is that the 2 MUX's take up 416 LC's!! My whole register file
> >takes up 688 LC's, which is 59% of the space on my device!! This doesn't
> >leave me with much room for the rest of my project. I haven't completed my
> >project yet, but it appears I will be really struggling for space, and I am
> >required to use the 10K20.  Surely there would have to be a better way of
> >designing a register file than what I have done, but I just can't seem to
> >think of a better way. I've been working on this problem now for several
> >weeks and am not making any progress. If there is anyone out there who
> would
> >be able to give me some advice I would be eternally grateful. Thanks in
> >advance. Bruce.
> >
> >-----== Posted via Deja News, The Leader in Internet Discussion ==-----
> >http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
>
>

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