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"Zhi" <zhiman@hotmail.com> wrote in message news:ce9c6dd6.0411291340.7eae607e@posting.google.com... > Hi, > > Without undermining Xilinx's achievements in the 10Gb/s space, I would > like to point out that using a 6.25Gb/s tranceiver is better than a > 10Gb/s transceiver for a 6.25Gb/s application. > > There are several reasons: > > 1. A PLL designed for 622Mb/s to 10Gb/s has a wider tuning range than > a PLL designed for up to 6.25Gb/s; hence, the performance (jitter) of > a PLL designed up to 6.25Gb/s is better. This *can* be true if the PLL is designed for ONLY a tight frequency range. A 6.25 Gb transceiver will have no better PLL performance if it still requires greater than 1 octave of tuning. The generalization isn't valid. > 2. Using a 10Gb/s transceiver to run at 6.25Gb/s wastes area, power, > and the customer has to pay a premium for a turbo-charged transceiver > that he/she will not use at full-speed. Do you get the point about performance margin? If I need to drive 70mph and lower, I can get an economy car. I own something with a bit more spunk because it gives me headroom in performance. If you can keep your eyes open enough at 10 Gb, you can keep your eyes wide open at 6.25 Gb. The inverse is not true. Is the area indeed greater? Can't the same SerDes functionality occupy the same space with good design? A 10 Gb channel run at 6.25 Gb will consume about 62.5% of the full speed power. If the solution cost for 10 Gb transceivers is significantly greater than the 6.25 Gb solutions, the overall development cost has to be considered for board spins and time to market, design support and production quality. The 6.25 Gb solution may be the best choice for many designs. > 3. Moreover, your choice should not only be based on the transceiver. > It is just part of the whole solution. FPGA core fabric should also be > taken into account. Does the core fabric have enough LEs to process > all the data coming in at 6.25Gb/s? A 10Gb/s transceiver may require > more LEs, and if not used, will be wasted. Again, running a 10 Gb transceiver at 6.25 Gb will use the same number of LEs as a 6.25 Gb transceiver running at 6.25 Gb. > These are just a few reasons to choose a 6.25Gb/s transceiver. > > BTW, there are 15+ FPGA/ASIC/IP/ASSP vendors who have 6.25Gb/s > transceivers. This enables industry interoperability at 6.25Gb/s. It > will be the sweet spot in the coming years. > > Aside from these comments, the RocketIO group at Xilinx did an > outstanding job on the 10Gb/s transceiver. However, the market crash > in 2001 has pushed the standarization of 10Gb/s for many many years. > Therefore, it is not unreasonable to say that it was over-engineered > and customers will have to pay for this innovation even though they > may not need it. > > ZhiArticle: 76276
"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message news:41ab91a2$0$66410$14726298@news.sunsite.dk... > Hi again! > >>>I just bought the Spartan3 starter board from the xilinx webshop (made by >>>digilent). >>> >>>I have now checked the datasheet of the Spartan3, but I don't seem to get >>>what clocks can be used? No information on duty-cycles or other info, is >>>this of no importance? >> >> >> You can use the Digital Clock Manager (DCM) to adjust duty-cycle, phase >> and >> frequency with the 50MHz GCLK0 input you have. > > Yeah, but doesn't this cause delays by routing this to an output-port for > driving the A/D? It depends on your timing budget. There is a thing called a DLL that phase locks the clock input to the destination synchronous clock input. It can also double the frequency. It has the ability to adjust the phase of the clock to null out the estimated first order delay of the IOB (note use of FDDRCPE) and PCB transport delay. If more precision is needed for temperature / voltage compensation, then maybe the feedback approach is better. > > >>>Rise-time/fall-time problems when attaching an A/D-converter to the same >>>clock? >> >> >> I like point to point routing where possible. You may be able to use a >> clock >> forwarding scheme (via an FDDRCPE instance) to achieve this. There are >> also board deskewing schemes via feedback that may be suitable. I think >> the feedback scheme necessitates a 'T' in the board routing. > > I'm stupid (or maybe I just haven't learned all this stuff yet) so please > explain all these terms like "point to point routing", "clock forwarding > scheme" and what do you mean by a "board deskewing schemes via feedback" > and what is a 'T'? I think my explanation was inadequate. What I meant by point to point is that there are only two component connection involved in routing the trace on the PCB (There may also be a series source termination resistor in the path). I believe that the feedback scheme wants a minimum of three component connections. One from the FPGA output pin to the destination, and an equal length path from the FPGA output pin to the FPGA feedback pin. I've never used the feedback method, but I suspect that I would research "Source Termination of Multiple Clock Lines" section 11.5 "High-Speed Digital Design A Handbook Of Black Magic" by Howard Johnson and Martin Graham where there is a short segment from the output clock pin to two series resistors (what I called the "T") to two lines of equal length and the loads at each end are balanced. Hope this helps, Newman P.S. I've seen this book at my local Barnes and Nobles. It may be available close to you too. > > > > Thanks, > PrebenArticle: 76277
Hi there, Could anybody please let me know what is the approximate price of the lowest-cost FPGA or CPLD with about 20K Lggic Cells, or even less? The quantum will be around 10K per year. We will start a very simple application, and I hope I can find some FPGA less than $5. Thanks in advance. JohnsonArticle: 76278
Hi, Does anybody know, were do I find a PS2 Controller (with interrupt) for the OPB Bus? Thanks MarcoArticle: 76279
Zhi, I beg to differ. See below, Austin Zhi wrote: > Hi, > > Without undermining Xilinx's achievements in the 10Gb/s space, I would > like to point out that using a 6.25Gb/s tranceiver is better than a > 10Gb/s transceiver for a 6.25Gb/s application. > > There are several reasons: > > 1. A PLL designed for 622Mb/s to 10Gb/s has a wider tuning range than > a PLL designed for up to 6.25Gb/s; hence, the performance (jitter) of > a PLL designed up to 6.25Gb/s is better. The PLL's are programmable. No way we could go from 622 Mbs to 10 Gbs with one PLL without changing something. The PLL is optimized for the bitrate you select. Jitter is also optimized for the bitrate. A receiver that has a 10 Gbs bandwidth will be more capable of discerning edges at lower rates. Also a fact. This will lead to a wider eye opening, and better jitter performance. > > 2. Using a 10Gb/s transceiver to run at 6.25Gb/s wastes area, power, > and the customer has to pay a premium for a turbo-charged transceiver > that he/she will not use at full-speed. It is true that running a 10 Gbs MGT at 10 GBs takes more power than at 6.25 Gbs, but it is not true that it takes more power than a competing 6.25 Gbs transceiver from other vendors. To find the power, one must examine the datasheets. Many vendors do not have the latest process technology available to them (they don't make that many chips). We have an advantage where we can use a newer process, and provide those advantages to our customers. > > 3. Moreover, your choice should not only be based on the transceiver. > It is just part of the whole solution. FPGA core fabric should also be > taken into account. Does the core fabric have enough LEs to process > all the data coming in at 6.25Gb/s? A 10Gb/s transceiver may require > more LEs, and if not used, will be wasted. Logic elements used are hardly used based on the MGT bit rate. The physical layer interface is hard coded in the FPGA, and ours has a multitude of features that saves logic element usage. Logic needed is what the customer needs to do their job. Bit rate is a separate issue from that altogether. > > These are just a few reasons to choose a 6.25Gb/s transceiver. All the wrong reasons. Here is my list of reasons: 1) is it proven silicon? 2) can I see it work? (can I get a sample? can I order it now?) 3) is there a characterization report available? 4) what cores are there to support it? 5) how much logic does the it take to support the MGT? 6) how is the factory support, training, and field support? > > BTW, there are 15+ FPGA/ASIC/IP/ASSP vendors who have 6.25Gb/s > transceivers. This enables industry interoperability at 6.25Gb/s. It > will be the sweet spot in the coming years. Anyone's guess, but I do not disagree. There is no accepted standard at this rate yet, however. And, I never count IP providers without seeing their silicon first. Right now, there is only one FPGA supplier with 6.25 Gbs capability: Xilinx. > > Aside from these comments, the RocketIO group at Xilinx did an > outstanding job on the 10Gb/s transceiver. Thanks. > However, the market crash > in 2001 has pushed the standarization of 10Gb/s for many many years. Hmmm. I know the meetings are still being held, and folks are still fighting over the standard for 10 Gbs....... > Therefore, it is not unreasonable to say that it was over-engineered > and customers will have to pay for this innovation even though they > may not need it. The cost of the engineering of the MGT, while not zero, is a very small part of the overall chip cost. The area used for the MGTs is also small compared to everything else. You seem to be arguing that there are no market forces to force competitive pricing? Of course we will price the part to match market forces. Why not take advantage of all that superior engineering? Sounds like a bargain to me.Article: 76280
Johnson, From the NuHorizons web page FAQ: "14. How much will Spartan-3 devices cost? Volume pricing at the end of 2004 will be under $2.95 for the XC3S50 and under $12 for the XC3S1000, and under $100 for the XCS4000 (based on 250K unit quantities)." I suggest you contact your local Xilinx rep for pricing on 10K per year qty. XC3S50 == 50K logic cells. Austin Johnson wrote: > Hi there, > > Could anybody please let me know what is the approximate price of the > lowest-cost FPGA or CPLD with about 20K Lggic Cells, or even less? The > quantum will be around 10K per year. We will start a very simple > application, and I hope I can find some FPGA less than $5. > > Thanks in advance. > > JohnsonArticle: 76281
I'm a total Verilog newbie, having just started yesterday but already
finding it far less intimidating than the VHDL I thought I was going to
have to deal with. I'm a systems software programmer with enough
hardware knowledge to be dangerous, and a few projects under my belt
(microcontroller based servo-style stuff). FWIW I'm not taking any
classes on this stuff (yet?), just screwing around on my own.
I'm playing with the design of a multi-channel analog capture system,
where I need an FPGA to take a number (4-16) of SPI inputs from stereo
audio ADCs, and multiplex them all into a 16-bit bus with a single write
strobe, to be connected to a Cypress EZ-USB FX2.
I'm pretty sure I've got almost all the logic in place, *except* for a
clocking issue. The PCM audio SPI port includes an LRCLK (left-right
clock) that goes high at the end of the left channel sample, then goes
low at the end of the right channel sample.
The problem is that even with a lot of googling, I haven't been able to
find (or recognize?) a way to create a pulse I can use to start the
parallel output sequence, on *both* edges of the LRCLK:
SCLK .. _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- ..
DATA .. xxxxxxRRRRRRRRRRRRxxxxLLLLLLLLLLLLxxxxRRRRRRRRRRRRxx ..
LRCLK .. __----------------________________----------------__ ..
goal .. __-_______________-_______________-_______________-_ ..
Once I have the LRCLK edge pulse, I can start up the FSM that will drive
each group of 16 bits to the output bus one at a time, based either on
SCLK or another clock (safer with SCLK, as it stays a basic synchronous
design AFAICT).
Any hints would be greatly appreciated, especially code fragments <g>
Also if anyone can suggest a good example-heavy, relatively theory-light
book on Verilog FPGA design (e.g. "Verilog FPGA Design by Example for
Dummies") that I might get...
TIA,
Omega
aka Erik Walthinsen
omega@temple-baptist.com
Article: 76282Hi. I'm looking for recent info/benchmarks that compare the results of physical synthesis for Stratix parts. I'd like to compare the physical synthesis built in to Quartus II to using Synplicity's Amplify program. I'd appreciate any comments and comparisons to help decide on a flow. Thanks much! DavidArticle: 76283
Erik Walthinsen wrote: (snip) > I'm pretty sure I've got almost all the logic in place, *except* for a > clocking issue. The PCM audio SPI port includes an LRCLK (left-right > clock) that goes high at the end of the left channel sample, then goes > low at the end of the right channel sample. > The problem is that even with a lot of googling, I haven't been able to > find (or recognize?) a way to create a pulse I can use to start the > parallel output sequence, on *both* edges of the LRCLK: > SCLK .. _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- .. > DATA .. xxxxxxRRRRRRRRRRRRxxxxLLLLLLLLLLLLxxxxRRRRRRRRRRRRxx .. > LRCLK .. __----------------________________----------------__ .. > goal .. __-_______________-_______________-_______________-_ .. While its name says CLK, I would consider LRCLK as an enable, which enables the left or right channel shift register as appropriate. You can then use it to enable a latch on the appropriate edge of SCLK. What is the timing relationship between SCLK and LRCLK? (snip) > Any hints would be greatly appreciated, especially code fragments <g> > Also if anyone can suggest a good example-heavy, relatively theory-light > book on Verilog FPGA design (e.g. "Verilog FPGA Design by Example for > Dummies") that I might get... Imagine you have a large box full of TTL chips and wire, and you want to build something. Now think of verilog as instructions to a robot on how to wire up those chips. If you think of it like software you will get confused easily. -- glenArticle: 76284
"Johnson" <gpsabove@yahoo.com> wrote in message news:b1ac2406.0411291426.2b7e0d4a@posting.google.com... > Hi there, > > Could anybody please let me know what is the approximate price of the > lowest-cost FPGA or CPLD with about 20K Lggic Cells, or even less? The > quantum will be around 10K per year. We will start a very simple > application, and I hope I can find some FPGA less than $5. > > Thanks in advance. > > Johnson For lowest cost, the Altera MAX II "CPLD" can give you good old fashioned FPGA functionality without the bells and whistles. The EPM1270 (smaller than the Xilinx XC3S50) is the first introduced with others scheduled for 2Q 2005. The single-piece pricing on Arrow is ugly now but the later, higher volume price might be a better fit for your timeframe. I know I can get the performance out of the Xilinx Spartan-3 but I also know some implementations can get a better overall solution with a different device. I don't have a good feel for the lowest cost FPGA from Lattice, but I'd look at them as well. Perhaps someone else can fill in this blank.Article: 76285
>Yes, I agree for a FIFO the simpler read port, write port block ram is >preferred and is all that is needed for a FIFO. But the OP was asking >for a way to infer a dual port block ram with write on both ports. He >was not asking about FIFOs. I think the FIFO was mentioned as a way to >interface a separately clocked interface to a single clock, dual port >block ram. > >I dug through all this a few weeks ago and both Xilinx and Altera say >that there are no means to infer true dual port, dual clock block rams >at this time. Seems a bit strange. Why is a 2 port RAM that can read and write on both ports that much more complicated to recognize than a 2 port RAM that can only read on one port and write on the other? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76286
glen herrmannsfeldt wrote:
> While its name says CLK, I would consider LRCLK as an enable, which
> enables the left or right channel shift register as appropriate.
> You can then use it to enable a latch on the appropriate
> edge of SCLK. What is the timing relationship between SCLK and LRCLK?
The chip I'm targetting atm is the PCM1804, with the datasheet at:
http://www-s.ti.com/sc/ds/pcm1804.pdf The waveform is at the very
bottom of page 21, and timings follow on the next page.
The first thing to do on receiving an LRCLK edge is to latch from the
shift registers, so I have a posedge LATCH wire to each input section.
If I have that, I can kick off the FSM shortly thereafter. Basically
what I'm trying to figure out is what the verilog looks like that causes
the LATCH to go high on both edges of LRCLK, and drop back down some
time before the next LRCLK edge (thus probably following an SCLK
transition).
> Imagine you have a large box full of TTL chips and wire, and you want
> to build something. Now think of verilog as instructions to a robot
> on how to wire up those chips. If you think of it like software
> you will get confused easily.
Problem is, my logic design skills are really rusty, being mostly
limited to what I learned almost a decade ago in the logic part of the
CS major in high school. But I've found that Verilog is almost excactly
the right mix of software and hardware design styles for me that I
cranked out the bulk of the necessary design in a couple of hours, the
same day as picking up Verilog for the first time.
Thanx,
Omega
aka Erik Walthinsen
omega@temple-baptist.com
Article: 76287
> See Jim Lewis's posting for the single
> process version. I have not tested this,
> but I will on Monday.
I tested it.
Leo/Xilinx can't handle the second write enable.
Quartus/Stratix runs a synthesis, but does
not infer dp_ram.
-- Mike Treseler
Article: 76288
On Mon, 29 Nov 2004 13:03:46 +0000, kubik <jackgroups@interfree.it> wrote:
>I was searching on the web a Xilinx virtex2 board for doing my first
>experience.
>I' ve found many boards on the xilinx on line store ( the
>HW-AFX family ) on the Avnet site ( ADS family ) and so on. But the prices
>of these boards are all more then one thousand of dollars.
>
>Are these prices so high because with them is sold the design software too ?
You should extend your search:
http://www.fpga-faq.com/FPGA_Boards.shtml
Philip Freidin
Fliptronics
Article: 76289Hi, I have a design where a Spartan XL was replaced by a Spartan 3. The FPGA is configured by an ATmega MCU which loads the configuration file into the FPGA. This procedure works fine with the old board and the Spartan XL, but with the Spartan 3 I have the trouble that I never get the DONE signal, after the configuration is done. I see data going over the DIN line into the Spartan 3 and an active clock signal. As I did not change anything on the ATmega software this should be fine. I generated the binary for the Spartan 3 and enabled the setting for "Drive DONE Pin High", to have the DONE signal being driven. As the ATmega uses 3.3V the Spartan is used in the 3.3V compatibility mode for configuration. I am just not sure about the VCCO_4 signal, as the data sheet is for my understanding a bit confusing. In the design that I am using it is tied to 3.3V. Is that correct or does it need to be connected to 2.5V during configuration? Is there anything else I need to consider with the serial slave mode when switching from Spartan XL to Spartan 3? Thanks for the help. GuenterArticle: 76290
Matthias Braeunig wrote: > Hello! > as I see there are people here using Altera Quartus II. > Has anyone succeeded installing Quartus on systems other than RedHat? > I'm looking for hints how to run the installer with csh on a Debian > Linux with kernel 2.6.8. Any help is greatly appreciated. > Mat Just a side question - do you have to pay to get Quartus II for Linux? I couldn't see it in download section. If so what do you get? Source code or rpm? - and how much if have to pay?Article: 76291
On 29 Nov 2004 12:56:51 -0800, gabor@alacron.com (Gabor Szakacs) wrote: >RobertP <r_p_u_d_l_i_k@poczta.onet.pl> wrote in message news:<coesj1$c50$1@news.onet.pl>... >> For Virtex II: >> >> Vbatt - in some places in the datasheet and user manual it is advised to >> leave it open if not used, in other it is advised to connect it to Vaux >> or to ground. Maybe someone knows what is the right way to go? >> (in previous project I left it open, no problems noticed). > >I've left these unconnected in multiple designs - no problems. Earlier versions of the datasheet indicated that Vbatt could be left open. The most recent version indicates that Vbatt should be connected to gnd or vccaux. Presumably this change was made to fix some problem. Regards, AllanArticle: 76292
Falk, You can do one thing, take a post-map verilog simulation file and pattern search for LUT instances with only one input ... these will the ones which are configured as route-thru Now, in the FPGA editor, you can search the component names for those LUTs. I had done somehting similar few months back, i found most instances when the LUT is used as route-thru to feed the dedicated XOR gate. the otehr input of XOR gate coming from BY/BX signal. What could be the reason for hte same !? ... my guess is some timing improvemnets. Though i have not yet seen myself the LUT route-thru mode used to feed the flip - flop but i think it is possible to do so, while using both Set and Reset signal in the Flip-flop. eg.FDSR instance of xilinx primitives. the issue with this is, how the tool at mapping stage estimate whether the preceeding logic to the flip flop be accomodated in the LUT or the LUT be configured in route-thru mode. probably some data like number of route-thru LUTs post-map and post-pnr can shed more light to it? --Varun.Article: 76293
Falk, You can do one thing, take a post-map verilog simulation file and pattern search for LUT instances with only one input ... these will the ones which are configured as route-thru Now, in the FPGA editor, you can search the component names for those LUTs. I had done somehting similar few months back, i found most instances when the LUT is used as route-thru to feed the dedicated XOR gate. the otehr input of XOR gate coming from BY/BX signal. What could be the reason for hte same !? ... my guess is some timing improvemnets. Though i have not yet seen myself the LUT route-thru mode used to feed the flip - flop but i think it is possible to do so, while using both Set and Reset signal in the Flip-flop. eg.FDSR instance of xilinx primitives. the issue with this is, how the tool at mapping stage estimate whether the preceeding logic to the flip flop be accomodated in the LUT or the LUT be configured in route-thru mode. probably some data like number of route-thru LUTs post-map and post-pnr can shed more light to it? --Varun.Article: 76294
On Mon, 29 Nov 2004 15:08:11 -0700, Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote: >I'm trying to figure out the best way to floorplan registered adder >trees, such as those used in FIR filters. The (Xilinx) placer seems to >have very little idea what to do with these. Even when I use an area >constraint around the whole tree, the individual adders are not >optimally placed, so the result is that my critical path is always >between adders, and not the adder carry chain itself. I always have to >manually place each adder in the tree to get good results. My questions >are: >1. Is there a way to get adder trees to work without manual placement? >2. Is the best placement for an adder tree a tree structure (wide at >one end and narrow at the other) or some more rectangular arrangement? >-Kevin I think there is a relatively smart way of adding the relatively placement primitives to your hdl code using vhdl generate command. If you separate the multi-input adder from the coefficient/input multipliers, you can code a reusable macro for this purpose. I think this might even possible with verilog-2001 but I haven't tried yet.Article: 76295
On Tue, 30 Nov 2004 05:59:42 GMT, mk<kal@delete.dspia.com> wrote: >On Mon, 29 Nov 2004 15:08:11 -0700, Kevin Neilson ><kevin_neilson@removethiscomcast.net> wrote: > >>I'm trying to figure out the best way to floorplan registered adder >>trees, such as those used in FIR filters. The (Xilinx) placer seems to >>have very little idea what to do with these. Even when I use an area >>constraint around the whole tree, the individual adders are not >>optimally placed, so the result is that my critical path is always >>between adders, and not the adder carry chain itself. I always have to >>manually place each adder in the tree to get good results. My questions >>are: >>1. Is there a way to get adder trees to work without manual placement? >>2. Is the best placement for an adder tree a tree structure (wide at >>one end and narrow at the other) or some more rectangular arrangement? >>-Kevin > >I think there is a relatively smart way of adding the relatively >placement primitives to your hdl code using vhdl generate command. If >you separate the multi-input adder from the coefficient/input >multipliers, you can code a reusable macro for this purpose. I think >this might even possible with verilog-2001 but I haven't tried yet. It's still difficult, even if your tool supports Verilog-2001. VHDL is still the better language if you are 'calculating' your placement. http://groups.google.com/groups?threadm=mB7gb.12033%24dH7.6968%40newssvr25.news.prodigy.com Regards, AllanArticle: 76296
I am working on a vhdl core that will permit for data transmitted from an A/D converter card into the FPGA board to be sent directly to a hardrive using the PCI bus of the computer to which the board is connected and the bus architecture of the VIRTEX II PRO FPGA... I am looking for help, or hints in order to complete this project. I am aware that there is PCI cores, is this a good place to start? Any help would be appreciated. Thank YouArticle: 76297
"Austin Lesea" <austin@xilinx.com> wrote > XC3S50 == 50K logic cells. You presumably misspoke, here 50K = 50,000 system gates (a.k.a. marketing gates, dog gates, what have you). An XC3S50 contains 768 slices, or 1536 4-LUTs and FFs, or 1728 logic cells by that curious derating understood and beloved (and believed) only by Xilinx marketing. The rest of us just giggle. See also http://www.fpgacpu.org/#021129 and its links. The smallest 3S device with ~20K LCs is an XC3S1500 (26,624 LUTs+FFs, 29952 "LC"s). The 3S1000 is close (15360 LUTs+FFs, 17280 "LC"s). To my knowledge, nothing has been announced that provides 20 KLUTs for $5 in any quantity. (Not to mention the configuration memory.) I think the closest announced EasyPath device is something like ~$13(?) for an XCE3S1500 in quantity with ~$75K(?) NRE. But Moore's Law will take us there ere long. Make it your ASIC, indeed! Jan GrayArticle: 76298
Truth in posting: >Path: path!border1.nntp.dca.giganews.com!nntp.giganews.com!news.glorb.com!postnews.google.com!not-for-mail >From: zhiman@hotmail.com (Zhi) >Newsgroups: comp.arch.fpga >Subject: Re: RocketIO success? >Date: 29 Nov 2004 11:19:02 -0800 >Organization: http://groups.google.com >Lines: 46 >Message-ID: <ce9c6dd6.0411291119.6cff39c0@posting.google.com> >References: <cnl7em$9q3$1@hood.uits.indiana.edu> >NNTP-Posting-Host: 66.35.226.228 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< >Content-Type: text/plain; charset=ISO-8859-1 >Content-Transfer-Encoding: 8bit >X-Trace: posting.google.com 1101755942 24698 127.0.0.1 (29 Nov 2004 19:19:02 GMT) >X-Complaints-To: groups-abuse@google.com >NNTP-Posting-Date: Mon, 29 Nov 2004 19:19:02 +0000 (UTC) >Xref: newsmst01a.news.prodigy.com comp.arch.fpga:78930 nslookup 66.35.226.228 Name: ip66-35-226-228.altera.com Address: 66.35.226.228 >Paul Smith <ptsmith@nospam.indiana.edu> wrote in message news:<cnl7em$9q3$1@hood.uits.indiana.edu>... >> I'm considering the V2pro series for several projects. V2PRO High Speed serial is called RocketIO. I have a tee shirt to prove it. Maximum baud is 3.125 GBaud. This is what the original poster is asking about. V2PRO-X High Speed serial is called RocketIO. Maximum baud is 10.3125 GBaud. Virtex 4 High Speed serial is called RocketIO. Maximum baud is 11.1 GBaud. On 29 Nov 2004 11:19:02 -0800, zhiman@hotmail.com (Zhi) wrote: >Hi, > >Although I don't dispute some of the success stories of RocketIO, I >would like to point out of the following: > >1. The reference clock requirement for RocketIO is very tight >(=expensive). Xilinx has been recommending an oscillator from EPSON >with very low jitter. > >2. If your application is less than or equal to 6.5Gb/s, do not use >RocketIO. You will be paying a premium for a 10Gb/s transceiver. >Altera and Lattice have better alternatives. Which is wrong. The OP asked about V2PRO, max rate is 3.125 GBaud. When comparing features, make sure you evaluate what IP is included in one vendor's SerDes, which other vendors require you to use logic resources to achieve. >3. Lastly, just to make it clear: >V2Pro uses an "old" transceiver, which has poor performance with >jitter tolerance and transfer, although it has very good jitter >generation >V2ProX uses RocketIO Not according to Xilinx. >10Gb/s technology for backplanes is here, but there are a lot of >challenges. One must utilize new backplane (PCB) material, new >connectors, new test/measurement equipment, and be extermely careful >with the board design since every little discontinuity will contribute >to eye closure. Obviously reference backplanes/boards for 10Gb/s exist >today, but the question is whether they are feasible and >cost-effective for production. None of which is relevant, given the OP's question. >Just my two cents, >Zhi I wouldn't give you one cent. Philip Freidin, Particpant in the definition, design, and verification of 3 generations of RocketIO (and all round good guy consultant). Philip Freidin FliptronicsArticle: 76299
Erik Walthinsen wrote:
> The problem is that even with a lot of googling, I haven't been able to
> find (or recognize?) a way to create a pulse I can use to start the
> parallel output sequence, on *both* edges of the LRCLK:
>
> SCLK .. _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_- ..
> DATA .. xxxxxxRRRRRRRRRRRRxxxxLLLLLLLLLLLLxxxxRRRRRRRRRRRRxx ..
> LRCLK .. __----------------________________----------------__ ..
> goal .. __-_______________-_______________-_______________-_ ..
Well, with a lot of screwing around, I managed to get what I needed.
Veteran developers, please observe the barf bag located in the seat-back
in front of you:
module edgeclock(clk, lrclk, strobe);
input clk, lrclk;
output strobe;
wire strobe;
reg int_strobe;
reg prev_lrclk;
always @(posedge clk) begin
if (prev_lrclk != lrclk)
int_strobe = 1'b1;
else
int_strobe = 1'b0;
prev_lrclk = lrclk;
end
assign strobe = int_strobe;
endmodule
In Quartus II Web Edition simulation, this yields a strobe pulse that
spans a complete clk cycle, starting at the rising clk edge immediately
following a lrclk transition:
clk .. __--__--__--__--__--__--__--__-- ..
lrclk .. ____----------------____________ ..
strobe .. ______----____________----______ ..
Once that was in place, the state machine (hardly even that) for
blasting the various registers out was a piece of cake, and the whole
design is functional to a first approximation.
All this in less than 36 hours from first trying my hand at Verilog.
Very cool.
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