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Messages from 19475

Article: 19475
Subject: Re: Dumb question springing from a discussion about chess on a chip...
From: ahuramazda@my-deja.com
Date: Thu, 23 Dec 1999 18:37:17 GMT
Links: << >>  << T >>  << A >>
A regular expression recognition engine would satisfy most demands,I
guess. How big would a RegExp engine capable of recognizing eight-bit
tokens in a sixtyfour token string. I suppose it depends on how many
clock cycles a RegExp lookup was allowed to take. Say 100 cycles per
lookup, on a 50 MHz FPGA. And how much bigger would it have to be to
handle recursive descent parsing. Say 100 cycles per lookup and maximum
recursion depth of 1,2,4,8 respectively, on a 50 MHz FPGA.

Regards Dan Andersson


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19476
Subject: Re: Dumb question springing from a discussion about chess on a chip...
From: Ray Andraka <randraka@ids.net>
Date: Thu, 23 Dec 1999 16:11:04 -0500
Links: << >>  << T >>  << A >>
How many tokens are there?

Presumably, you have a relatively small number of tokens (say 16 for
example)  you are looking for at a given time, and when you do find a
token, you need to know which one you found.  You can do this in a Xilinx
FPGA (you need the ability to use the look up tables as small RAMs) so that
you check each position in the token string for all the token keys in
parallel in a single clock cycle, and that can happen at 50 MHz or better.
The logic to do that is pretty small too.

For example, if you have a set of 16 8 bit keys you need to search for in a
64 token string, this can be done in 64 clocks (one per token in the
string)  with perhaps plus a few extra clocks for the pipeline latency.  It
will take you 16 clocks per key to program the search keys before you do
the search.  The 16 key search only occupies about 50 CLBs in an XC4000 or
Spartan part.  The programming takes 16 clocks per search key, but by
adding hardware you can parallel those to program all n keys in n+15
clocks.  The output of the search is a set of signals indicating which of
the 16 keys, if any, match the token in the string.  You can even get fancy
and allow wildcards on one or more bits with very little additional
hardware (all in the programming logic).  You are also not limited to a
particular string length, as this circuit will accept streaming data.

I'm a bit fuzzy on the recursive part.  Can you be a little more
descriptive.


ahuramazda@my-deja.com wrote:

> A regular expression recognition engine would satisfy most demands,I
> guess. How big would a RegExp engine capable of recognizing eight-bit
> tokens in a sixtyfour token string. I suppose it depends on how many
> clock cycles a RegExp lookup was allowed to take. Say 100 cycles per
> lookup, on a 50 MHz FPGA. And how much bigger would it have to be to
> handle recursive descent parsing. Say 100 cycles per lookup and maximum
> recursion depth of 1,2,4,8 respectively, on a 50 MHz FPGA.
>
> Regards Dan Andersson
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19477
Subject: Re: Global buffer insertion (Synplify/Flex10K)
From: ying@soda.CSUA.Berkeley.EDU (Ying C.)
Date: 23 Dec 1999 22:34:27 GMT
Links: << >>  << T >>  << A >>


I haven't used Synplify for a while so I am not sure if there is any way to get it to
automatically insert global buffers on internal clocks.

However, the easiest workaround for you is to insert a "global" primitive on your internal
clock manually. I believe Synplify's help file has a section on Altera primitives/black
box. There should also be an Altera.v or Altera.vhd in the lib directory. These files
include the necessary declaration to black box the global primitive. All you need to do is
to insert the "global" buffer.

Ying
ying@csua.berkeley.edu




 In article <385A786C.DC9A5523@collins.rockwell.com>,
Matt Gavin  <mtgavin@collins.rockwell.com> wrote:
>Gurus,
>
>I am encountering some difficulties with inserting global buffers
>on internal clocks in my FPGA design. My current flow is Synplify
>for synthesis, then Altera MaxPlusII to target a Flex10K FPGA.
>
>It appears that Synplify will NOT automatically insert a global
>buffer onto an internal clock, for my Flex10K, even if it finds
>the internal clock. (IT DOES seem to do this for Xilinx FPGA's,
>though! The Xilinx global buffer gets embedded right into the output
>EDIF. Not so for Flex10K.)  Is there a way to make Synplify do this
>automatically for all target devices?  (A Flex10K has 4 global buffers
>that may be used for internal signals.)
>
>Of course, this global buffer insertion can be done manually in
>MaxPlusII, but it is quite cumbersome, for a couple reasons.
>First, the (MaxPlusII internal) name of the net is not known
>until you get through the fitter, and the .rpt file is output, stating
>the (names of the) inferred clocks. Only then can you insert a statement
>
>in the <design>.acf file, inserting a global buffer onto some
>oddly-named
>net like "core~239~7."  Then, you have to re-run maxPlusII just so it
>recognizes your global buffer!
>
>Secondly, of course this MaxPlusII name will change if you go back
>through the flow and resynthesize. Then you have to repeat the process
>to find the *new* MaxPlusII name for your internal clock!  Then
>modify your .acf file, and re-run again!
>
>Any ideas? Can I get Synplify to insert the buffer manually, for
>Flex10K?
>And if not, is there a way to refer to my internal clock by the same
>name every time through the flow, in MaxPlusII.
>
>Thanks for any ideas.
>
>Matt Gavin
>
>


Article: 19478
Subject: viewlogic problem
From: James Yeh <jiahau@uclink4.berkeley.edu>
Date: Thu, 23 Dec 1999 18:03:29 -0800
Links: << >>  << T >>  << A >>
We just swapped computers around in my office, and now my Workview
Office cannot open the file vllib.vmb,
even though its there,
any help?

Article: 19479
Subject: Re: Dumb question springing from a discussion about chess on a chip...
From: ahuramazda@my-deja.com
Date: Fri, 24 Dec 1999 10:44:56 GMT
Links: << >>  << T >>  << A >>

>
> I'm a bit fuzzy on the recursive part.  Can you be a little more
> descriptive.
>

Wildcards and logic (and, or,) should be present, and yes recursivemeans
that one token is the regExp pattern itself. This makes the engine
a parser that can also parse if the syntax is correct exactly as a
compiler checks aprograms compliance to a programming  language. Even
more desirable is if anumber of tokens are different regExp patterns
thus making the FPGA run'software' runtime programming. Maybe that is
to costly? I dont know, but that  would make it ultimately configurable.

Regards Dan Andersson



Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19480
Subject: Re: Dumb question springing from a discussion about chess on a chip...
From: Ray Andraka <randraka@ids.net>
Date: Fri, 24 Dec 1999 09:55:05 -0500
Links: << >>  << T >>  << A >>
I'm not sure of your terminology, specifically the RegExp pattern.  The
matching circuit I mentioned gets programmed with a set of tokens that you
are searching for, including any masking which would do the wildcarding.
The match logic has an output for each search key, so that when there is a
match (subject to the wildcards and masks) the output corresponding the the
matched key goes active.  Those one-hot outputs can then be encoded into a
more compact key identifier code if desired.

If I understand you correctly, you want to take the recogized tokens and put
them into a string to run through another layer of token recognition?  If
that is the case, it can be done either with an additional instance of the
token search I described yesterday, or by scheduling the string to go
through the first again after reprogramming the search keys.

If layered, it would be relatively easy to program the second layer's search
string using the first layer's results.

The And-or logic comes at very little extra cost, as it is incorporated in
the programming logic rather than the match logic.

ahuramazda@my-deja.com wrote:

> >
> > I'm a bit fuzzy on the recursive part.  Can you be a little more
> > descriptive.
> >
>
> Wildcards and logic (and, or,) should be present, and yes recursivemeans
> that one token is the regExp pattern itself. This makes the engine
> a parser that can also parse if the syntax is correct exactly as a
> compiler checks aprograms compliance to a programming  language. Even
> more desirable is if anumber of tokens are different regExp patterns
> thus making the FPGA run'software' runtime programming. Maybe that is
> to costly? I dont know, but that  would make it ultimately configurable.
>
> Regards Dan Andersson
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19481
Subject: Re: viewlogic problem
From: Ray Andraka <randraka@ids.net>
Date: Fri, 24 Dec 1999 09:56:48 -0500
Links: << >>  << T >>  << A >>
Did you set up the workview en

James Yeh wrote:

We just swapped computers around in my office, and now my Workview
(WDIR) environment variables and path?

> Office cannot open the file vllib.vmb,
> even though its there,
> any help?



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19482
Subject: Re: PCI slot 3.3V pins.
From: "peter dudley" <padudle@worldnet.att.net>
Date: Fri, 24 Dec 1999 08:27:21 -0700
Links: << >>  << T >>  << A >>
You got my curiosity going on this one.

The situation is that most computer add-in card makers design their cards to
be universal. That is their edge connectors have two notches in them so they
can plug into 5V or 3.3V slots. The problem is that 3.3V slots are required
to provide the 5V supply but 5V slots are not required to provide the 3.3V
supply. To make sure that their cards work in any slot, these card makers
only use the 5V supply and use a linear regulator to get the 3.3Volts that
they need.

Modern FPGA's like Xilinx Virtex are compliant with the 5V and 3.3V
signalling standards even though their I/O are powered by 3.3V.

Someone please correct me if I'm wrong on this.

    Pete


Peter Dudley
Arroyo Grande Systems Incorporated


   Signal Processing in Hardware and Software

Mahboob Ahmed <m.ahmed@ieee.org> wrote in message
news:83s975$pt2$1@nnrp1.deja.com...
> Most of the PCI slot in PCs, and SUN workstations I have checked, do not
> provide 3.3V in the PCI slot, except the new Intel boards, which do
> have 3.3V supply. Why the common PCs and workstations do not provide
> 3.3V supply in PCI slot as specified in PCI Rev? and why is it
> disabled? If a PCI card needs 3.3V in 5V 32-bit slot then what
> should be done to enable the dedicated 3.3V supply pins.
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 19483
Subject: regular expression matching and parsing in FPGAs (was chess...)
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Fri, 24 Dec 1999 20:33:01 GMT
Links: << >>  << T >>  << A >>
I'm not sure how regular expression matching and parsing relates to chess,
but these can of course be done at tremendous speeds in an FPGA.  Here are
some ideas.

REGULAR EXPRESSIONS

A regular expression (including compositions of simpler REs) can be
implemented in hardware through these transformations:

1. convert the RE to an NFA (non-deterministic finite-state automaton)
2. convert the NFA to a DFA (deterministic FA) using the subset construction
3. implement the DFA as a one-hot FSM (finite state machine).

Here each state is a flip-flop.  Transitions between states are
combinatorial expressions of the states and the input.  If the input is
encoded, e.g. as 8-bit characters, there would probably be additional logic
to decode characters ('.') or character classes ([0123456789]).

This could consume one character per clock at 100-200 MHz.


LR PARSING

A parser for a context-free grammar can be implemented in hardware through
these transformations.

1. derive LR-parser shift-reduce tables (actions, goto, etc.) from the CFG
productions.
2. implement the shift-reduce parsing algorithm approximately as:

  // types
  enum Token { term1, ..., nTerminals, nonterm1, ..., nTNT};
  enum State { s0, s1, ..., nStates };
  enum Prods { ..., nProds };
  enum Action { accept, error, shift, reduce1, reduce2, ... };

  // tables
  Action actions[nStates][nTNT];
  State goto[nStates][nTNT];
  Token lhs[nProds]; // token on lhs of production, e.g. X for X ::= Y1 ...
Yn
  int rhs_len[nProds]; // length of rhs of production, e.g. n for above

  // shift-reduce parser
  State stack[]; // a stack of states
  int depth= 0; // index of top-of-stack
  State s = s0;
  stack[depth] = s;
  Token input = first token;
  repeat {
      Action a = actions[s][input];
      if (a == accept)
          stop, accept;
      else if (a == error)
          stop, error;
      else if (a == shift) {
          s = stack[++depth] = goto[s][input];
          input = next token;
      }
      else if (a == reduce p) {
          s = stack[depth -= rhs_len[p]];
          s = stack[++depth] = goto[s][lhs[p]];
      }
  }

3. implement *that* in an FPGA:

For example, for parsing C, from off the top of my head,
  nStates < 256,
  nTNT < 128,
  nProds < 100,
  Stack depth <128.

So implement 'input' in a 7-bit-wide FIFO; 'stack' in a 128x8 SRAM; 'lhs' in
a 100x7 SRAM; 'rhs_len' in a 100x4 SRAM, and 'actions' and 'goto' in
external SSRAM (for C, they won't fit in a few block rams).  'Stack' is
indexed by depth; 'actions' by s and input; 'goto' by s and mux(input,
lhs[p]).  Implement depth in an accumulator (a 7-bit register + an adder of
+1 or - prod_size[p]).

Perhaps you could clock this parser at 100 MHz.  A pity that it is not easy
to pipeline the action and goto lookups.

So here's a sketch of an FCCM to syntax check a preprocessed C program.
Characters come in at 200 MHz to the lexical analyzer, which uses the RE
recognizer described above to deposit tokens into a FIFO.  The C parser
drains the FIFO, consuming a token approximately every few cycles at 100
MHz.  Overall the machine gobbles C code at 200 MB/s, or about 5 million
lines per second, and then either the green Accept LED or the red Error LED
lights up. :-)

(Interesting gedanken experiment but I'd rather do it in software, thanks.)

(I would be surprised if this (shift-reduce parsing in hardware) has not
been studied already.  Also, I wonder if there are alternative
implementations of the LR parser algorithm that can better use 1-hot
encodings.  The problem is the current state gets pushed and popped, and a
stack of 1-hot states is not very storage efficient; thus you'd have to
encode them into a binary representation and decode them back to a 1-hot
encoding.)

(I suppose there might be real-world applications of work like this in areas
like text classification and DNA sequencing.)

Ref: see e.g. Compilers: Principles, Techniques, and Tools, Aho Sethi and
Ullman, or Crafting a Compiler, Fischer and LeBlanc.

Jan Gray



Article: 19484
Subject: Re: viewlogic problem
From: James Yeh <jiahau@pacbell.net>
Date: Fri, 24 Dec 1999 14:10:20 -0800
Links: << >>  << T >>  << A >>
That could be it.....
however since it is the holiday time, I suppose, I'll just wait to do
it.

Ray Andraka wrote:
> 
> Did you set up the workview en
> 
> James Yeh wrote:
> 
> We just swapped computers around in my office, and now my Workview
> (WDIR) environment variables and path?
> 
> > Office cannot open the file vllib.vmb,
> > even though its there,
> > any help?
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
Article: 19485
Subject: Re: Dumb question springing from a discussion about chess on a chip...
From: ahuramazda@my-deja.com
Date: Sat, 25 Dec 1999 00:01:57 GMT
Links: << >>  << T >>  << A >>
Thanks for the explanations. I will purchase some FPGA development
system and try to master the basics. Can anyone recommend a good
beginners system, price is not such a big deal.

Regards Dan Andersson


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19486
Subject: Re: regular expression matching and parsing in FPGAs (was chess...)
From: ahuramazda@my-deja.com
Date: Sat, 25 Dec 1999 00:22:50 GMT
Links: << >>  << T >>  << A >>
Thanks for the hardware transformation hints. If there are any good
books about algorithm to hardware translation/implementation you know
of I would really appreciate if you gave some titles or authors to
guide my search. As to the RegExp to chess connection, humans seem to
get great use of patterns in chess evaluation. A hardware evaluator w
pattern and expression matching should have some interesting properties
worth testing.

Regards Dan Andersson


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19487
Subject: * * * M E R R Y C H R I S T M A S * * *
From: Santa@TheNorthPole.Org
Date: 25 Dec 1999 00:29:28 GMT
Links: << >>  << T >>  << A >>
Merry Christmas to all and to all a good night !!!!!!!!


Sleep tight,

Santa

Article: 19488
Subject: Re: Dumb question springing from a discussion about chess on a chip...
From: Dave Vanden Bout <devb@xess.com>
Date: Fri, 24 Dec 1999 20:59:12 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------74FD3C04141C266E9EC74CC3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Dan:

You can look at www.xess.com.  We make a variety of tutorial systems for Xilinx FPGAs which include both the hardware, software, and a tutorial text that shows how to design logic systems with FPGAs.

You should also check www.optimagic.com for other vendors of systems.



ahuramazda@my-deja.com wrote:

> Thanks for the explanations. I will purchase some FPGA development
> system and try to master the basics. Can anyone recommend a good
> beginners system, price is not such a big deal.
>
> Regards Dan Andersson
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

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n:Vanden Bout;David
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org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------74FD3C04141C266E9EC74CC3--

Article: 19489
Subject: Re: Dumb question springing from a discussion about chess on a ch
From: Dave Vanden Bout <devb@xess.com>
Date: Fri, 24 Dec 1999 20:59:12 -0500
Links: << >>  << T >>  << A >>
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------ =_NextPart_000_01BF4EE0.F0AD362E
Content-Type: text/plain

Dan:

You can look at www.xess.com.  We make a variety of tutorial systems for
Xilinx FPGAs which include both the hardware, software, and a tutorial
text that shows how to design logic systems with FPGAs.

You should also check www.optimagic.com for other vendors of systems.



ahuramazda@my-deja.com wrote:

> Thanks for the explanations. I will purchase some FPGA development
> system and try to master the basics. Can anyone recommend a good
> beginners system, price is not such a big deal.
>
> Regards Dan Andersson
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


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Content-Disposition: attachment;
	filename="devb.vcf"
Content-Description: Card for Dave Vanden Bout

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n:Vanden Bout;David
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email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

------ =_NextPart_000_01BF4EE0.F0AD362E--

Article: 19490
Subject: Re: EDIF and VITAL
From: krishnam@nital.stpp.soft.net
Date: 25 Dec 1999 07:45:40 GMT
Links: << >>  << T >>  << A >>
Your VITAL template thold_CLR_C does not match with the SDF entry
(HOLD CLR (posedge C) (0.200:0.200:0.200))
Try changing either the template or the sdf entry to avoid the error.
change the template name to thold_CLR_C_noedge_posedge or
change the sdf entry to (HOLD CLR C (0.200:0.200:0.200))
Hope this helps.

Krishna

In a previous article,  Walter Soto Encinas Jr  <soto@icmc.sc.usp.br>
writes:
>Hi
>
>	I am doing the backannotation in a VHDL design to do the accurate
>gate-level simulation with Synopsys VSS. I got some error messages, in the
>flip-flops instances:
>
>**Error: vhdlsim,260: 
>    (SDF File: addr.sdf Line: 1820) generic
>    /ADDR/COUNT_LIN/COUNT_3_MID_1_FF/THOLD_CLR_C_noedge_posedge is not
>    declared.
>
>	I suppose these messages are about some VITAL timing parameter not
present
>in the VITAL libraries of the ff. Loking into the VHDL VITAL model of FF,
I
>couldn't find the parameter exactly as it appears above, but very similar:
>
>entity FDC is
>   generic(
>      TimingChecksOn: Boolean := True;
>      InstancePath: STRING := "*";
>      Xon: Boolean := False;
>      MsgOn: Boolean := True;
>      tpd_CLR_Q                  :  VitalDelayType01 := (0.718 ns, 0.659
>ns);
>      tpd_C_Q                    :  VitalDelayType01 := (0.718 ns, 0.658
>ns);
>      tsetup_D_C                 :  VitalDelayType := 1.300 ns;
>      thold_D_C                  :  VitalDelayType := 0.200 ns;
>      trecovery_CLR_C            :  VitalDelayType := 2.325 ns;
> ---> thold_CLR_C                :  VitalDelayType := 0.000 ns;
>      tpw_C_posedge              :  VitalDelayType := 4.000 ns;
>      tpw_CLR_posedge            :  VitalDelayType := 4.000 ns;
>      tpw_C_negedge              :  VitalDelayType := 4.000 ns;
>      tpw_CLR_negedge            :  VitalDelayType := 4.000 ns;
>      tipd_D                     :  VitalDelayType01 := (0.000 ns, 0.000
>ns);
>      tipd_C                     :  VitalDelayType01 := (0.000 ns, 0.000
>ns);
>      tipd_CLR                   :  VitalDelayType01 := (0.000 ns, 0.000
>ns));
>
>	May someone advice me how to correct this error? Should I change the SDF
>file? How? I guess SDF is in EDIF format. A typical FF in SDF is:
>
>	
>(CELL
>        (CELLTYPE "FDC")
>        (INSTANCE COUNT_LIN/COUNT_8_FIM_1_FF)
>        (TIMINGCHECK
>                (SETUP D (posedge C) (1.338:1.338:1.338))
>                (HOLD D (posedge C) (0.200:0.200:0.200))
>                (WIDTH (posedge C) (1.658:1.658:1.658))
>                (WIDTH (negedge C) (1.479:1.479:1.479))
>                (RECOVERY (negedge CLR) (posedge C) (1.300:1.300:1.300))
>                (HOLD CLR (posedge C) (0.200:0.200:0.200))
>                (WIDTH (posedge CLR) (0.863:0.863:0.863))
>                (WIDTH (negedge CLR) (0.001:0.001:0.001))
>        )
>        (DELAY
>                (ABSOLUTE
>                        (DEVICE Q (0.215:0.215:0.215) (0.298:0.298:0.298))
>                )
>        )
>)
>
>	Thanks is advance!
>
>-- 
>|                                       Walter Soto Encinas Jr          |
>|                                            PhD  Student               |
>|                                             IFSC / USP                |
>|                                               Brazil                  |




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Article: 19491
Subject: Is Actel antifuse FPGA realy secure ?
From: "Luc Nantel" <luc_nantel@videotron.ca>
Date: Sat, 25 Dec 1999 13:25:28 -0500
Links: << >>  << T >>  << A >>
Hi,

Some peoples say the antifuse FPGA is the best technology to have your design
secure from getting duplicated (not reversed engineered). Some other people are
saying it take very little effort (with the right tools) to look at the die and
figure out the bit stream for any kind of ROM base devices or antifuse FPGA. I
was also told there are even some people out there offering that kind of service
for a small fee.

The same concern applies to reverse engineer a bit stream into a source file.

Can someone help me figure that one out?

Luc


Article: 19492
Subject: FIFO design
From: Jamil Khaib <Khatib@ieee.org>
Date: Sun, 26 Dec 1999 11:23:11 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------BD2E06C30308A6F42E5EBEFD
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi
The attached files are a VHDL code for FIFO core and the other is the
timing siumlation for this FIFO.

I have a problem with the output data (or the write operation) It comes
with one clock delay. Could you please help why do I have this problem
and how can I solve it?

Thanks
Jamil Khatib
OpenIP Organization http://www.openip.org
OpenIPCore Project http://www.openip.org/oc
OpenCores Project http://www.opencores.org

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-------------------------------------------------------------------------------
-- 
-- Copyright Jamil Khatib 1999
-- 
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it under the terms of the Openip General Public
-- License as it is going to be published by the OpenIP Organization and any
-- coming versions of this license.
-- You can check the draft license at
-- http://www.openip.org/oc/license.html
--
--
-- Creator : Jamil Khatib
-- Date 10/10/99
--
-- version 0.19991224
--
-- This file was tested on the ModelSim 5.2EE
-- The test vecors for model sim is included in vectors.do file
-- This VHDL design file is proved through simulation but not verified on Silicon
-- 
--

-------------------------------------------------------------------------------


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_signed.ALL;



-- Dual port Memory core



ENTITY dpmem IS
generic ( ADD_WIDTH: integer := 8 ;
		 WIDTH : integer := 8);
  PORT (
    clk      : IN  std_logic;                                -- write clock
    reset    : IN  std_logic;                                -- System Reset
    W_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Write Address
    R_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Read Address
    Data_In  : IN  std_logic_vector(WIDTH - 1  DOWNTO 0);    -- input data
    Data_Out : OUT std_logic_vector(WIDTH -1   DOWNTO 0);    -- output Data
    WR       : IN  std_logic;                                -- Write Enable
    RE       : IN  std_logic);                               -- Read Enable
END dpmem;


-------------------------------------------------------------------------------

ARCHITECTURE dpmem_v1 OF dpmem IS


  TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1  DOWNTO 0);
                                        -- Memory Type
  SIGNAL data : data_array(0 to (2** add_width) );  -- Local data



  procedure init_mem(signal memory_cell : inout data_array ) is
  begin

    for i in 0 to (2** add_width) loop
      memory_cell(i) <= (others => '0');
    end loop;

  end init_mem;


BEGIN  -- dpmem_v1

  PROCESS (clk, reset)

  BEGIN  -- PROCESS


    -- activities triggered by asynchronous reset (active low)
    IF reset = '0' THEN
      data_out <= (OTHERS => 'Z');
      init_mem ( data);

      -- activities triggered by rising edge of clock
    ELSIF clk'event AND clk = '1' THEN
      IF RE = '1' THEN
        data_out <= data(conv_integer(R_add));
      else
        data_out <= (OTHERS => 'Z');    -- Defualt value
      END IF;

      IF WR = '1' THEN
        data(conv_integeR(W_add)) <= Data_In;
      END IF;
    END IF;



  END PROCESS;


END dpmem_v1;



-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_arith.ALL;


entity FIFO is
    
    generic (WIDTH : integer := 8;  	-- FIFO word width
	     ADD_WIDTH : integer := 8); -- Address Width

    port (Data_in : in std_logic_vector(WIDTH - 1 downto 0);  -- Input data
	  Data_out : out std_logic_vector(WIDTH - 1 downto 0);  -- Out put data
	  clk : in std_logic;  		-- System Clock
	  Reset : in std_logic;  	-- System global Reset
	  RE : in std_logic;  		-- Read Enable
	  WE : in std_logic;  		-- Write Enable
	  Full : buffer std_logic;  	-- Full Flag
	  Half_full : out std_logic;  	-- Half Full Flag
	  Empty : buffer std_logic); 	-- Empty Flag

end FIFO;

-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--USE ieee.std_logic_signed.ALL;
--USE ieee.std_logic_arith.ALL;

-------------------------------------------------------------------------------
-- purpose: FIFO Architecture
architecture FIFO_v1 of FIFO is

-- constant values
	constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
	constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
	constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="01111111";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1');
 
	signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0);  -- delayed Data in


    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
	signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address

    signal REN_INT : std_logic;  		-- Internal Read Enable
    signal WEN_INT : std_logic;  		-- Internal Write Enable

	component dpmem
	    generic (ADD_WIDTH : integer := 8;
	   			 WIDTH : integer := 8 );

    	port (clk : in std_logic;
	    reset : in std_logic;
	  	w_add : in std_logic_vector(ADD_WIDTH downto 0 );
	    r_add : in std_logic_vector(ADD_WIDTH downto 0 );
	    data_in : in std_logic_vector(WIDTH - 1 downto 0);
	    data_out : out std_logic_vector(WIDTH - 1 downto 0 );
	    WR  : in std_logic;
	    RE  : in std_logic);
	end component;

	
    
begin  -- FIFO_v1

----------        
memcore: dpmem 
generic map (WIDTH => 8,
				ADD_WIDTH =>8)
	port map (clk => clk,
			 reset => reset,
			 w_add => w_add,
			 r_add => r_add,
			 Data_in => data_in_del,
			 data_out => data_out,
			 wr => wen_int,
			 re => ren_int);

-----------
Sync_data: process(clk,reset)
	begin -- process Sync_data
		if reset ='0' then
			data_in_del <= (others =>'0');

		elsif clk'event and clk = '1'  then
			data_in_del <= data_in;
		else 
			data_in_del <= data_in_del;
		end if;


	end process Sync_data;

-----------

wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';

ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';


-----------


Add_gen: process(clk,reset)    
	variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
	variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state
	variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Counter state

   begin  -- process ADD_gen

       -- activities triggered by asynchronous reset (active low)
       if reset = '0' then
	   		q1 := (others =>'0');
	   		q2 := (others =>'0');
	   		q3 := (others =>'0');
       -- activities triggered by rising edge of clock
       elsif clk'event and clk = '1'  then
		
		if WE = '1' and ( FULL = '0') then
	   		q1 := q1 + 1;
			q3 := q3 +1;

        else
	   		q1 := q1;
			q3 := q3;


	    end if;

		if RE = '1' and ( EMPTY = '0') then
	   		q2 := q2 + 1;
			q3 := q3 -1;

        else
	   		q2 := q2;
			q3 := q3;
	    end if;
			
       end if;
		
	    R_ADD  <= q2;
		W_ADD  <= q1;
		D_ADD  <= q3;

   end process ADD_gen;

	FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
	EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
	HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';

-- FULL is set to '1' when Both addresses are equal
		 --	 '1' when W_ADD = R_ADD else


-------------------------------------------------------------------------------

    
    
end FIFO_v1;


-------------------------------------------------------------------------------

configuration fifo_conf of fifo is
	for fifo_v1
		for memcore:dpmem
  			use entity work.dpmem(dpmem_v1);
		end for;
	end for;

end fifo_conf;

--------------BD2E06C30308A6F42E5EBEFD--

Article: 19493
Subject: status during ISP
From: "David Geng" <david_geng@yahoo.com>
Date: Mon, 27 Dec 1999 12:26:27 +0800
Links: << >>  << T >>  << A >>
Hi, there,

can any one tell me what's the status(high, low or float) of the I/O pins
when a EPLD or FPGA in ISP procedure?

Thanks a lot

David


Article: 19494
Subject: How can I preset /prereset some Latches
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Mon, 27 Dec 1999 07:57:15 -0800
Links: << >>  << T >>  << A >>
Hi friends,
I need that after downloading of my program in FPGA some latches will
be preseted and some prereseted (without any external reset).
I know it is possible but can you say me how?

My tools : VHDL, Leonardo, Xilinx Alliance 2.1i, Virtex.




* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!

Article: 19495
Subject: Re: FIFO design
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 27 Dec 1999 10:07:59 -0700
Links: << >>  << T >>  << A >>
Jamil Khaib wrote in message <3865DE7E.6B9DFC8B@ieee.org>...
>Hi
>The attached files are a VHDL code for FIFO core and the other is the
>timing siumlation for this FIFO.
>
>I have a problem with the output data (or the write operation) It comes
>with one clock delay. Could you please help why do I have this problem
>and how can I solve it?

Both the memory read and memory write operations are synchronous, which is
good.  But there will always be a one-tick delay.  You'll have to make sure
the data is ready at the right time.


-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

The secret of Slurm is on a need-to-know basis.



Article: 19496
Subject: Schematics for ISP
From: Legista <lkostov@yahoo.com>
Date: Mon, 27 Dec 1999 21:33:51 +0200
Links: << >>  << T >>  << A >>
I search to see a design example of ISP of Xilinx's FPGA using EEPROM.
Can someone tell me if I can see a schematics of that and where.

Thank you!

Latchezar

Article: 19497
Subject: xilinx help *desperately* needed
From: jonathan@canuck.com (Susan Deike)
Date: 28 Dec 1999 01:58:54 GMT
Links: << >>  << T >>  << A >>
I'm working on a design of moderate complexity in 5V Spartan using
Foundation 2.1i sp3 (yeah, I know.  just let me get over this problem,
lord, and I'll move to the HP...).

The problem is that I can't get a D register in the device to latch data 
off of my microprocessor's (68HC11) data bus.  My original target is an 
XCS40, but I've built a proto using an XCS10 to try to isolate this problem.

Both protos exhibit exactly the same behaviour:  The combinatorial logic 
(address decoders) work just fine.  When I probe the clock enable signal 
(flashreg) out it's exactly what and where it should be, valid 50nS before 
and after the system (e) clock, the falling edge of which should latch the 
data off of the bus.  Scope shows the data to be good as well, just never 
appears on the register output

This one's serious, folks.  If it were just me being stupid it wouldn't be
so bad, but it's also baffling the local FAE and rep.  Major inspiration
needed from major smart person.

Thanks much.

Jonathan Levine



----- details below -----



Attached is the vhdl source and the ucf file, verbatim.  Device is 5V XCS10
in PLCC84.  Each pair of power supply pins is decoupled.  MODE pin is pulled
up and INIT pin is pulled down (I'm using JTAG for programming via the 
parallel cable).  All other pins not listed in the ucf are NC (floating).



----- vhdl source -----



-- stripped-down test to see if data can be latched offa the bus
-- Last revised Dec 27/99

library ieee;
use ieee.std_logic_1164.all;

entity hc11_dec is
    port (
        hc11_a: in std_logic_vector(15 downto 8);
        hc11_d: in std_logic_vector(1 downto 0);
	hc11_e: in std_logic;
	hc11_rw: in std_logic;
	hc11_as: in std_logic;
	hc11_reset: in std_logic;

	hc11_fa: out std_logic_vector(1 downto 0);

        hc11_romcs: out std_logic;
	hc11_memoe: out std_logic;

	hc11_dpramcs: out std_logic;
	hc11_duartcs: out std_logic;
	hc11_ramcs: out std_logic
    );

end hc11_dec;

architecture rtl of hc11_dec is

signal flashreg: std_logic;

begin

	hc11_dpramcs <= '1';
	hc11_duartcs  <= '1';
	hc11_ramcs <= '1';
	
-- eprom

	hc11_romcs <= '0' when (((hc11_a >= x"e0") and (hc11_a <= x"ff")) 
			and (hc11_as = '0') and (hc11_rw = '1')) else '1';

	hc11_memoe <= '0' when (((hc11_a >= x"e0") and (hc11_a <= x"ff")) 
			and (hc11_as = '0') and (hc11_rw = '1')) else '1';

-- flashreg 

	flashreg <= '1' when ((hc11_a = x"b4") and (hc11_as = '0') 
			and (hc11_rw = '0')) else '0';

process (flashreg, hc11_d, hc11_e, hc11_reset)

begin

-- latch data lsb into flash address lsb

	if rising_edge(hc11_e) then
		if (flashreg = '1') then
			hc11_fa(0) <= hc11_d(0);
		end if;
	end if;

end process;

end rtl;



----- ucf file -----



##############################################
#      BASIC UCF SYNTAX EXAMPLES V2.1.6      #
##############################################
#
# The "#" symbol is a comment character.   To use this sample file, find the
# specification necessary, remove the comment character (#) from the beginning
# of the line, and modify the line (if necessary) to fit your design.
#
#              TIMING SPECIFICATIONS
#
# Timing specifications can be applied to the entire device (global) or to
# specific groups in your design (called "time groups'). The time groups are
# declared in two basic ways.
#
# Method 1: Based on a net name, where 'my_net' is a net that touches all the
#           logic to be grouped in to 'logic_grp'. Example:
#NET my_net TNM_NET = logic_grp ;
#
# Method 2: Group using the key word 'TIMEGRP' and declare using the names of
#           logic in your design. Example:
#TIMEGRP group_name = FFS ("U1/*");
#           creates a group called 'group_name' for all flip-flops within
#           the hierarchical block called U1. Wildcards are valid.
#
# Grouping is very important because it lets you tell the software which parts
# of a design run at which speeds.  For the majority of the designs with only
# one clock, use simple global constraints.
#
# The type of grouping constraint you use can vary depending on the synthesis
# tools you are using.  Foundation Express does better with Method 2.
#
#
############################################################
# Internal to the device clock speed specifications - Tsys #
############################################################
#
# data      _________      /^^^^^\       _________   out
# ----------| D   Q |-----{ LOGIC } -----| D   Q |------
#           |       |      \vvvvv/       |       |
#        ---|> CLK  |                 ---|> CLK  |
# clock  |  ---------                 |  ---------
# ------------------------------------
#
# ---------------
# Single Clock
# ---------------
#
# ----------------
# PERIOD TIME-SPEC
# ----------------
# The PERIOD spec. covers all timing paths that start or end at a
# register, latch, or synchronous RAM which are clocked by the reference
# net (excluding pad destinations).  Also covered is the setup
# requirement of the synchronous element relative to other elements
# (ex. flip flops, pads, etc...).
# NOTE:  The default unit for time is nanoseconds.
#
#NET clock PERIOD = 50ns ;
#
#       -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
# FROM:TO style timespecs can be used to constrain paths between time
# groups.  NOTE:  Keywords:  RAMS, FFS, PADS, and LATCHES are predefined
# time groups used to specify all elements of each type in a design.
#TIMEGRP RFFS = RISING FFS ("*");  // creates a rising group called RFFS
#TIMEGRP FFFS = FALLING FFS ("*");  // creates a falling group called FFFS
#TIMESPEC TSF2F  = FROM : FFS   : TO : FFS   : 50 ns; // Flip-flips with the same edge
#TIMESPEC TSR2F  = FROM : RFFS  : TO : FFFS  : 25 ns; // rising edge to falling edge
#TIMESPEC TSF2R  = FROM : FFFS  : TO : RFFS  : 25 ns; // falling edge to rising edge
#
# ---------------
# Multiple Clocks
# ---------------
# Requires a combination of the 'Period' and 'FROM:TO' type time specifications
#NET clock1 TNM_NET = clk1_grp ;
#NET clock2 TNM_NET = clk2_grp ;
#
#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ;
#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ;
#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ;
#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ;
#
#
############################################################
# CLOCK TO OUT specifications - Tco                        #
############################################################
#
# from      _________      /^^^^^\       --------\
# ----------| D   Q |-----{ LOGIC } -----| Pad    >
# PLD       |       |      \vvvvv/       --------/
#        ---|> CLK  |
# clock  |  ---------
# --------
#
# ----------------
# OFFSET TIME-SPEC
# ----------------
# To automatically include clock buffer/routing delay in your
# clock-to-out timing specifications, use OFFSET constraints .
# For an output where the maximum clock-to-out (Tco) is 25 ns:
#
#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ;
#
#      -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSF2P  = FROM : FFS   : TO : PADS  : 25 ns;
# Note that FROM: FFS : TO: PADS constraints start the delay analysis
# at the flip flop itself, and not the clock input pin.  The recommended
# method to create a clock-to-out constraint is to use an OFFSET constraint.
#
#
############################################################
# Pad to Flip-Flop speed specifications - Tsu              #
############################################################
#
# ------\         /^^^^^\       _________   into PLD
# |pad   >-------{ LOGIC } -----| D   Q |------
# ------/         \vvvvv/       |       |
#                            ---|> CLK  |
# clock                      |  ---------
# ----------------------------
#
# ----------------
# OFFSET TIME-SPEC
# ----------------
# To automatically account for clock delay in your input setup timing
# specifications, use OFFSET constraints.
# For an input where the maximum setup time is 25 ns:
#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ;
#
#      -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSP2F  = FROM : PADS  : TO : FFS   : 25 ns;
# Note that FROM: PADS : TO: FFS constraints do not take into account any
# delay for the clock path.  The recommended method to create an input
# setup time constraint is to use an OFFSET constraint.
#
#
############################################################
# Pad to Pad speed specifications - Tpd                    #
############################################################
#
# ------\         /^^^^^\       -------\
# |pad   >-------{ LOGIC } -----| pad   >
# ------/         \vvvvv/       -------/
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSP2P  = FROM : PADS  : TO : PADS  : 125 ns;
#
#
############################################################
# Other timing specifications                              #
############################################################
#
# -------------
# TIMING IGNORE
# -------------
# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The
# "*" character is a wild card, which can be used for bus names.  A "?"
# character can be used to wild-card one character.
# Ignore timing of net reset_n:
#NET : reset_n : TIG ;
#
# Ignore data_reg(7:0) net in instance mux_mem:
#NET : mux_mem/data_reg* : TIG ;
#
# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC
# named TS01 only:
#NET : mux_mem/data_reg* : TIG = TS01 ;
#
# Ignore data1_sig and data2_sig nets:
#NET : data?_sig : TIG ;
#
# ---------------
# PATH EXCEPTIONS
# ---------------
# If your design has outputs that can be slower than others, you can
# create specific timespecs similar to this example for output nets
# named out_data(7:0) and irq_n:
#TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;
#
# If you have multi-cycle FF to FF paths, you can create a time group
# using either the TIMEGRP or TNM statements.
#
# WARNING:  Many VHDL/Verilog synthesizers do not predictably name flip
# flop Q output nets.  Most synthesizers do assign predictable instance
# names to flip flops, however.
#
# TIMEGRP example:
#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
#inst_path/ff_q_output_net2*);
#
# TNM attached to instance example:
#INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
#INST inst_path/ff_instance_name2_reg* TNM = slowffs ;
#
# If a FF clock-enable is used on all flip flops of a multi-cycle path,
# you can attach TNM to the clock enable net.  NOTE:  TNM attached to a
# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the
# net.
#NET ff_clock_enable_net TNM = slowffs ;
#
# Example of using "slowffs" timegroup, in a FROM:TO timespec, with
# either of the three timegroup methods shown above:
#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;
#
# Constrain the skew or delay associate with a net.
#NET any_net_name MAXSKEW = 7 ;
#NET any_net_name MAXDELAY = 20 ns;
#
#
# Constraint priority in your .ucf file is as follows:
#
#    highest 1.  Timing Ignore (TIG)
#            2.  FROM : THRU : TO specs
#            3.  FROM : TO specs
#    lowest  4.  PERIOD specs
#
# See the on-line "Library Reference Guide" document for
# additional timespec features and more information.
#
#
############################################################
#                                                                                                                    #
#         LOCATION and ATTRIBUTE SPECIFICATIONS            #
#                                                                                                                    #
############################################################
# Pin and CLB location locking constraints                 #
############################################################
#
# -----------------------
# Assign an IO pin number
# -----------------------
#INST io_buf_instance_name  LOC = P110 ;
#NET io_net_name  LOC = P111 ;
#
# -----------------------
# Assign a signal to a range of I/O pins
# -----------------------
#NET "signal_name" LOC=P32, P33, P34;
#
# -----------------------
# Place a logic element(called a BEL) in a specific CLB location.
# BEL = FF, LUT, RAM, etc...
# -----------------------
#INST instance_path/BEL_inst_name  LOC = CLB_R17C36 ;
#
# -----------------------
# Place CLB in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7;
#
# -----------------------
# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1* LOC=clb_r1c1:clb_r5c7;
#
# -----------------------
# Prohibit IO pin P26 or CLBR5C3 from being used:
# -----------------------
#CONFIG PROHIBIT = P26 ;
#CONFIG PROHIBIT = CLB_R5C3 ;
# Config Prohibit is very important for forcing the software to not use critical
# configuration pins like INIT or DOUT on the FPGA.  The Mode pins and JTAG
# Pins require a special pad so they will not be available to this constraint
# prohibit all of the config-related pins for now.
# -----------------------
# Assign an OBUF to be FAST or SLOW:
# -----------------------
#INST obuf_instance_name FAST ;
#INST obuf_instance_name SLOW ;
#
# -----------------------
# FPGAs only:  IOB input Flip-flop delay specification
# -----------------------
# Declare an IOB input FF delay (default = MAXDELAY).
# NOTE:  MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
# into an IOB by the "map -pr i" option.
#INST input_ff_instance_name MEDDELAY ;
#INST input_ff_instance_name NODELAY ;
#
# -----------------------
# Assign Global Clock Buffers Lower Left Right Side
# -----------------------
# INST gbuf1 LOC=SSW
#PINLOCK_BEGIN
#Sat Oct 30 10:50:38 1999
NET "hc11_memoe" LOC = "P39";
NET "hc11_romcs" LOC = "P38";
#NET "hc11_fa<1>" LOC = "P46";
NET "hc11_d<0>" LOC = "P40";
#NET "hc11_d<1>" LOC = "P44";
NET "hc11_fa<0>" LOC = "P45";
NET "hc11_e" LOC = "P10";
NET "hc11_a<9>" LOC = "P25";
NET "hc11_a<12>" LOC = "P20";
NET "hc11_rw" LOC = "P27";
NET "hc11_as" LOC = "P28";
NET "hc11_a<15>" LOC = "P14";
NET "hc11_a<8>" LOC = "P26";
NET "hc11_a<10>" LOC = "P24";
NET "hc11_a<11>" LOC = "P23";
NET "hc11_a<14>" LOC = "P18";
NET "hc11_a<13>" LOC = "P19";
#NET "hc11_reset" LOC = "P9";
#PINLOCK_END
Article: 19498
Subject: Re: How can I preset /prereset some Latches
From: Dave Vanden Bout <devb@xess.com>
Date: Mon, 27 Dec 1999 22:40:36 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------79C3D19E8CD4B187BE88D61B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Have you tried placing the register initialization into the user constraints file?  This is what I put in my .UCF file if I have a register called X in my VHDL that I have to initialize:

INST X_reg INIT=S;    # this sets the X register to a logic 1
INST X_reg INIT=R;    # this sets the X register to a logic 0



Bonio Lopez wrote:

> Hi friends,
> I need that after downloading of my program in FPGA some latches will
> be preseted and some prereseted (without any external reset).
> I know it is possible but can you say me how?
>
> My tools : VHDL, Leonardo, Xilinx Alliance 2.1i, Virtex.
>
> * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
> The fastest and easiest way to search and participate in Usenet - Free!

--------------79C3D19E8CD4B187BE88D61B
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begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
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url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------79C3D19E8CD4B187BE88D61B--

Article: 19499
Subject: Re: xilinx help *desperately* needed
From: jonathan@canuck.com (Susan Deike)
Date: 28 Dec 1999 03:55:02 GMT
Links: << >>  << T >>  << A >>

Oops - booboo in posting.  "if rising_edge(hc11_e) then" should have
read "if falling_edge(hc11_e)", of course.  Typo in this listing only;
help still desperately needed.

Jonathan



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