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Messages from 87750

Article: 87750
Subject: Re: ISE webpack doesnt support Spartan xcs10, solution??
From: "Guenter" <dannoritzer@web.de>
Date: 30 Jul 2005 07:59:20 -0700
Links: << >>  << T >>  << A >>
Dave,

googlinggoogler@hotmail.com schrieb:

> Hiya,
>
> Foolishly I developed a board for a spartan 3 xcs10, without finding
> suitable development enviroment, assuming that the free ISE Webpack
> would be suitable - just found out now i've gone to fire my board up
> and program it that I can't...
>

The smallest Spartan 3 available that I know of is a xc3s50 and that
one is supported with Webpack. From your part description it sounds
like you are using a Spartan.


> Can anyone suggest a free solution to this?

...

Xilinx has a tool called ISE Classic, you find it here:

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=dr_dt_iseclassics_index&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools

That one still supports the Spartan, however, at that time the
Synthesis tool came from a different Company and is not part of that
package. So unlike with the current Webpack that you download and do
the whole implementation process, with the ISE Classic you need an
extra Sythesis tool that supports the Spartan.

Regards,

Guenter


Article: 87751
Subject: Re: ISE webpack doesnt support Spartan xcs10, solution??
From: googlinggoogler@hotmail.com
Date: 30 Jul 2005 08:01:23 -0700
Links: << >>  << T >>  << A >>
Ohh yea, I really really want to use VHDL.

could I use hdlmaker? what do I need to produce from my VHDL? and then
I suppose I could just use impact from the ISE webpack?

cheers for your help, im a complete newbie,

Dave


Article: 87752
Subject: Altera Avalon Address format between Master & SDRAM controller?
From: pinod01@sympatico.ca
Date: 30 Jul 2005 08:15:55 -0700
Links: << >>  << T >>  << A >>
Hi there group,

    I'm implementing a user defined Master interface to the Avalon Bus
using Altera's Stratix FPGA and read through the documentation on the
Avalon Bus requirements and the SDRAM controller as a slave, and I'm
still not quite getting how the SDRAM controller interprets an address
supplied by a Master peripheral?  The SDRAM has a total of 22 bits (12
bits row, 8 bits column, & 2 bits bank).  I am provisioning the address
width on my master to be 32 bits wide of which the top 10 bits are
stuffed with 0's and the remaining bits are column-row-bank
respectively.   Is this a correct understanding on how to provide the
address to the slave peripheral sdram controller?  If not, I'm
definitely missing something here.

    Also I suspect this provided address is also de-correlated from the
address assigned in the SOPC builder configuration wizard?   That if i
have a Master peripheral talking to multiple slaves at different clock
cycles within my state machine, how do I specify which slave peripheral
I am targetting and guarantee that I'm talking to the right one?

Help would be appreciated
Pino


Article: 87753
Subject: Re: ISE webpack doesnt support Spartan xcs10, solution??
From: googlinggoogler@hotmail.com
Date: 30 Jul 2005 09:05:38 -0700
Links: << >>  << T >>  << A >>
Yea sorry for not giving the part no. its XCS10-3PC84C.

(at least i'll of made it correctly becuase I followed that datasheet!)

I'll investigate the ISE classic,

Cheers

Dave


Article: 87754
Subject: struggling with general digital design
From: "Telenochek" <interpasha@hotmail.com>
Date: 30 Jul 2005 09:26:13 -0700
Links: << >>  << T >>  << A >>
Hi everyone! I am new to digital design and need some general advice on
it.

I have experience with microcontrollers and other chips, but when it
comes to designing with FPGAs, I am having difficulty starting
moderately complex projects. I am comfortable enough with VHDL that I
think I should be able to start solving more advanced problems. VHDL is
not the problem.

I think the problem is that I don't know how to design a complex
digital system. I tried thinking in software, but it doesn't seem like
a good idea, too much time is spent on simple things. The elementary
digital design course I took some time ago doesn't seem to help much:
knowing basic logic gates/theorems and minimizing equations with K-maps
doesn't do me any good.

Currently I am trying to design a system with ADC -> ISSI RAM ->
FFTcore -> ISSI RAM -> DAC.

ADC obtains data, stores it in external SRAM, then FFT core takes this
data from RAM and stores its results in another block of RAM. Then the
results are output from RAM to DAC.

I need general advice on how to approach the design of this system.
Should I start with a block diagram, and try to work out simple blocks
of my system?

I already have working code where ADC loads data to FGPA and this data
is immediately sent to DAC. I also can read/write from external RAM (as
a separate block). But I don't know how to connect the two blocks
together. I don't feel like I am spending my time productively at the
moment.

Any advice would be highly appreciated. Thanks in advance, Pavel


Article: 87755
Subject: Re: Best Practices to Manage Complexity in Hardward/Software Design?
From: "Peter K." <p.kootsookos@iolfree.ie>
Date: 30 Jul 2005 10:37:24 -0700
Links: << >>  << T >>  << A >>
Randy Yates wrote:

> Because part of the implementation usually includes "unit" testing, or
> testing of the pieces,

I agree with that.

> and you must begin such testing with the
> smallest pieces possible.

I don't necessarily agree with that (the "must" part).  It depends on
where the complexity / newness / risk is.  If the newness is in the
"glue" binding the smallest peices together, then it's sometimes
possible to emulate/simulate the smallest posces pissible (as typed)
and concentrate on getting the glue right.

> Then, when the "foundation" is implemented,
> you can begin assembling the foundational pieces into small
> subsystems, test those, then piece those together, test those, etc.,
> until you have the entire system.

I think this is just one valid approach (bottom-up implementation).
It's not the only valid one.

Where an existing product-line is being replaced with the newly
designed product, it's possible to use the existing, working product as
"the complete system" and replace components of it as those components
get re-designed and re-implemented.

In software, you can start off implementation at a high-level of
abstraction and just "stub-out" the detail until you're ready to deal
with it.  When I start implementing software, I don't (necessarily)
start implementing a function... I first figure out what modules /
classes / components need to be there  and instantiate them.  Then I
figure out what external interfaces those classes need to present to
each other. Etc. etc.

Ciao,

Peter K.


Article: 87756
Subject: Re: How to import a netlist in VHDL
From: "Gladiator" <maleche@gmail.com>
Date: 30 Jul 2005 23:00:14 -0700
Links: << >>  << T >>  << A >>
beeraka@gmail.com wrote:
> Hi everyone,
>              I have a VHDL file which I use it in EDK in one of my
> custom cores  ..I also have a netlist file which has been generated
> using JHDL . The netlist file is in EDIF format. So now i want to
> import this netlist file in my VHDL so that I can connect to the JHDL
> component .I dunno if this is actually feasible to do . In case anyone
> has done this sort of stuff ..Help me out guys!!
>
> Thanks in advance
>
> --
> Parag

I have never done it myself but I believe that if you go to
Tools->Create/Import Peripheral Wizard you can choose to import a
peripheral and a few windows later it will allow you to direct it to
the netlist files that compose your core.

To do this in ISE, I believe you can use the Core Generator. For more
info check this Xilinx Answer record
http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=4512&iLanguageID=1

Hope this helps

Robin


Article: 87757
Subject: Re: ChipScope Pro : how to set up trigger
From: "pasacco" <pasacco@gmail.com>
Date: 31 Jul 2005 03:34:32 -0700
Links: << >>  << T >>  << A >>
Hi

Now the 'counter' example is working. ChipScope Pro is very handy.

Umm....I never had used a logic analyzer. And the VHDL code (what I
implemented last 3 months) is not working well with ChipScope Pro --:
Most probably it should be design problems.

BTW, to better understand how ChipScope Pro works, let me ask some more
things.

* In manual (ug029), it is written "VIO can both monitor and drive
interval FPGA signals in real time".
  As far as I understand, we can 'drive' internal signal using
'async_out'.
  Questions are
 -  Can we 'drive' signals in real time in 'Analyzer' ? If yes, should
we use 'trigger' setup and 'match function' to do that?
 -  In my 'counter' example, I forced rst_tmp (reset signal) to '0'
using the code below. I wonder this is a right way to 'drive' internal
signal in ChipScope Pro.
-----------------------------------------------------------------------------
  process(async_out)
  begin
     rst_tmp <= async_out(0);
  end process;
  async_out(0) <= '0';  -- to force 'rst_tmp' signal to '0'
-------------------------------------------------------------------------------

Thankyou. Regards


Article: 87758
Subject: Re: Best Practices to Manage Complexity in Hardward/Software Design?
From: Jerry Avins <jya@ieee.org>
Date: Sun, 31 Jul 2005 10:27:40 -0400
Links: << >>  << T >>  << A >>
Peter K. wrote:
> Randy Yates wrote:
> 
> 
>>Because part of the implementation usually includes "unit" testing, or
>>testing of the pieces,
> 
> 
> I agree with that.
> 
> 
>>and you must begin such testing with the
>>smallest pieces possible.
> 
> 
> I don't necessarily agree with that (the "must" part).  It depends on
> where the complexity / newness / risk is.  If the newness is in the
> "glue" binding the smallest peices together, then it's sometimes
> possible to emulate/simulate the smallest posces pissible (as typed)
> and concentrate on getting the glue right.
> 
> 
>>Then, when the "foundation" is implemented,
>>you can begin assembling the foundational pieces into small
>>subsystems, test those, then piece those together, test those, etc.,
>>until you have the entire system.
> 
> 
> I think this is just one valid approach (bottom-up implementation).
> It's not the only valid one.
> 
> Where an existing product-line is being replaced with the newly
> designed product, it's possible to use the existing, working product as
> "the complete system" and replace components of it as those components
> get re-designed and re-implemented.
> 
> In software, you can start off implementation at a high-level of
> abstraction and just "stub-out" the detail until you're ready to deal
> with it.  When I start implementing software, I don't (necessarily)
> start implementing a function... I first figure out what modules /
> classes / components need to be there  and instantiate them.  Then I
> figure out what external interfaces those classes need to present to
> each other. Etc. etc.

Whatever works for you is good. Writing stubs may be worth the effort, 
bur not writing stubs is less effort.

I try to start with interfaces and data structures, and to write small 
testable pieces that instantiate or use them. Every piece incorporated 
into a larger structure has already been vetted, and unless I've made a 
false start, nothing is discarded.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ

Article: 87759
Subject: FPGA
From: ravindra28d@rediffmail-dot-com.no-spam.invalid (ravindra kalla)
Date: Sun, 31 Jul 2005 11:15:47 -0500
Links: << >>  << T >>  << A >>
HI CAN ANYBODY SUGGEST ME ABOUT READ ADDRESS GENERATOR FORLOGICAL TO
PHISICAL ADDRESS GENERATOR


Article: 87760
Subject: Re: ISE webpack doesnt support Spartan xcs10, solution??
From: David Tweed <dtweed@acm.org>
Date: Sun, 31 Jul 2005 16:33:12 GMT
Links: << >>  << T >>  << A >>
Dave <googlinggoogler@hotmail.com> wrote:
> Ohh yea, I really really want to use VHDL.
> 
> could I use hdlmaker? what do I need to produce from my VHDL? and
 > then I suppose I could just use impact from the ISE webpack?
> 
> cheers for your help, im a complete newbie,

Newbie or not, I'd recommend staying away from HDLmaker for VHDL.

The author, Josh Rosen, really prefers Verilog, and the VHDL support
in HDLmaker is very weak and actually broken in several areas.
I've tried to incorporate it into my VHDL projects, even to the
point of writing wrapper programs to work around some of the flaws,
but lately I've given up on it and gone back to working in straight
VHDL.

AFAIK, the Webpack only supports Spartan 3 devices up to XC3S400,
so if you're using the XC3S1000, you're out of luck.

-- Dave Tweed

Article: 87761
Subject: some virtexII clock pads are useless??
From: "lik" <like609@163.com>
Date: 31 Jul 2005 09:55:16 -0700
Links: << >>  << T >>  << A >>
For test my fpga clock, I input a clock throuth one of the dedicated
clock pad, and output it from a general I/O. From the oscillograph, I
found some clock pads can give the correct signal, and the same clock
input the other clock pads only have the '1' output.

p.s. I use the same vhdl code as follows: clkin-->ibufg-->clkout.
Just differences in assign clock pins.

Any comments would be appreciated! thank you in advance!


Article: 87762
Subject: Re: some virtexII clock pads are useless??
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 31 Jul 2005 18:01:41 GMT
Links: << >>  << T >>  << A >>
On 31 Jul 2005 09:55:16 -0700, "lik" <like609@163.com> wrote:
>For test my fpga clock, I input a clock throuth one of the dedicated
>clock pad, and output it from a general I/O. From the oscillograph, I
>found some clock pads can give the correct signal, and the same clock
>input the other clock pads only have the '1' output.
>
>p.s. I use the same vhdl code as follows: clkin-->ibufg-->clkout.
>Just differences in assign clock pins.
>
>Any comments would be appreciated! thank you in advance!

The probability that some clock pads work and others don't is
zero. Your problem is either a damaged FPGA, or something is wrong
with your setup, such as shorted pins, power to I/O banks, wrong
pin constraints (check with FPGA editor), or many more possibilities.

Philip



Philip Freidin
Fliptronics

Article: 87763
Subject: Re: struggling with general digital design
From: "MM" <mbmsv@yahoo.com>
Date: Sun, 31 Jul 2005 18:33:23 -0400
Links: << >>  << T >>  << A >>
Hi Pavel,

> Currently I am trying to design a system with ADC -> ISSI RAM ->
> FFTcore -> ISSI RAM -> DAC.

What does ISSI stands for?

> ADC obtains data, stores it in external SRAM, then FFT core takes this
> data from RAM and stores its results in another block of RAM. Then the
> results are output from RAM to DAC.
>
> I need general advice on how to approach the design of this system.
> Should I start with a block diagram, and try to work out simple blocks
> of my system?

Yes, you should start with a block diagram, but the dataflow you mentioned
is essentially the one. To help you more we would need to know more about
the system:
1. Does it have it run continiously or in bursts?
2. Are the ADC and DAC sampling rates the same?
3. What is the FFT core interface?

> I already have working code where ADC loads data to FGPA and this data
> is immediately sent to DAC. I also can read/write from external RAM (as
> a separate block). But I don't know how to connect the two blocks
> together.

You probably will need a simple state machine to control the data flow. It
will sit in the idle state waiting for a start condition. As soon as it
happens it will go into the fill_input_buffer state, in which it will be
incrementing the memory address. Then it will go into the do_fft state, etc.
However, this idea of a single sequential state machine might not work if
the data flow needs to be continious. In that case you will need to double
the buffers and organize the process of their swapping during each cycle:
while the ADC fills out one side of the input buffer, the FFT core reads
data from another side, and similarly at the output. Obviously, the FFT has
be fast enough to process the block before the next block is ready...

Hope this helps a little bit.

/Mikhail



Article: 87764
Subject: Re: About post synthesize
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 31 Jul 2005 22:06:44 -0700
Links: << >>  << T >>  << A >>
Butt now i am finding difficulties in simulating the netlist. Model sim
is reporting errors that a synthesized component XORCY is not in the
library.
I tried to import the unisims libray but it did not helped. what could
be the problem. Please help....
regrds Sumesh


Article: 87765
Subject: Re: struggling with general digital design
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 31 Jul 2005 22:07:13 -0700
Links: << >>  << T >>  << A >>
Hi Telenochek,
I am also new to this field. now have only 1 year exp. but still i can
tell you that the bock diagrtam level design is the best starting
point.
1. Draw all the necessary blocks.
2. Conect all those blocks with the signals you think is needed.
3. Think about the blocks then, find out what is needed in the blocks
to satisfy the signal conditions.
4. If necessary draw the timing digrams.
5. then start coding the thing.
all the best with your design.....
sumesh


Article: 87766
Subject: Re: Digilent's JTAG-USB cable with chipscope
From: "Antti Lukats" <antti@openchip.org>
Date: Mon, 1 Aug 2005 08:59:10 +0200
Links: << >>  << T >>  << A >>
<do_not_reply_to_this_addr@yahoo.com> schrieb im Newsbeitrag
news:1122585166.774633.123730@g43g2000cwa.googlegroups.com...
>
> Can one use the JTAG-USB cable from digilent with chipscope ?
>
> Sumit
>

ChipScope only works with officially supported Xilinx cable, and does not
work with 3rd party cable to it is not 100% compliant to fully supported
cable.

It could be possible to write 'ChipScope' server that would allow to use 3rd
party cable, but would require reverse engineering of the protocol used by
the ChipScope server.

Antti



Article: 87767
Subject: Re: question about use SRAM on annapolis wildstarII board
From: ALuPin@web.de
Date: 1 Aug 2005 00:18:01 -0700
Links: << >>  << T >>  << A >>
There is no DDR2 SRAM !
You mean SDRAM.

Rgds
Andr=E9


Article: 87768
Subject: problem with Xilinx OPB to OPB bridge
From: bazogec@hotmail.com
Date: 1 Aug 2005 01:33:34 -0700
Links: << >>  << T >>  << A >>
hello all,
I'm building a system with EDK 7.1 on a virtex4 using Xilinx IP and
soft processor Microblaze .i'm using 2 OPB bus in my design the first
one is my mb_opb and there is another one (opb_2) who is link with
mb_opb through an opb to opb bridge.
My problem is there is no communication from my microblaze to my opb_2
( no I/O from RS232 connect to opb_2).
thanks for your answers.


Article: 87769
Subject: Re: struggling with general digital design
From: "Jon Beniston" <jon@beniston.com>
Date: 1 Aug 2005 02:16:52 -0700
Links: << >>  << T >>  << A >>
> What does ISSI stands for?

Integrated Silicon Solution, Inc probably. An SRAM manufacturer.
http://www.issi.com/

Cheers,
Jon


Article: 87770
Subject: webcamera access with ML310
From: "VB" <venkiba81@gmail.com>
Date: 1 Aug 2005 02:43:42 -0700
Links: << >>  << T >>  << A >>
I am using ML310 in STANDALONE along with usb based Quickcam
expreess(Web camera) for my project on real time image processing.

I came to know that it is possible to access the usb port of the board
using the linux kernel.
I am interested in accessing the port to recieve the data(frames) from
my webcamera and transfer the contents into the Bram.

Any help in this regard would be of utmost help.


Article: 87771
Subject: Re: verilog to blif(lut)
From: "junaid" <k.najeeb@gmail.com>
Date: 1 Aug 2005 03:25:05 -0700
Links: << >>  << T >>  << A >>
Dear Sir,

Thanks a lot. I followed the  information given by you  and  converted
verilog to blif file. But while I am converting the same to the net
file one error is coming.
  Allow Unrelated Blocks to be Clustered: Yes
        Connection Driven Clustering:  No
        Timing Driven Clustering On
        Timing Analysis Done Every 32000 blocks
        Allow Early Exit:  No
        Tradeoff Parameter Alpha:   0.75
        Delay Through Blocks:   0.10
        Intra Cluster Net Delay:   0.10
        Inter Cluster Net Delay:   1.00


Error:  Net #35 (null) has no driver and will cause
memory corruption.
 I have sent one mail in your  mail address <vaughn@eecg.utoronto.ca>
kindly see the mail and  help me to solve the problem


Article: 87772
Subject: Re: question about use SRAM on annapolis wildstarII board
From: "Karl" <karlIGNORETHISPART@chello.nl>
Date: 1 Aug 2005 04:15:52 -0700
Links: << >>  << T >>  << A >>
ALuPin@web.de wrote:
> There is no DDR2 SRAM !
> You mean SDRAM.
>
> Rgds
> Andr=E9

This comes close :-)

http://www.samsung.com/Products/Semiconductor/SRAM/SyncSRAM/DDRII_CIO_SIO/1=
8Mbit/K7I163684B/K7I163684B.htm


Article: 87773
Subject: Re: question about use SRAM on annapolis wildstarII board
From: ALuPin@web.de
Date: 1 Aug 2005 04:44:05 -0700
Links: << >>  << T >>  << A >>
So there is DDR2 SDRAM

and DDRII SRAM.

OK.

Rgds
Andr=E9


Article: 87774
Subject: Re: struggling with general digital design
From: ALuPin@web.de
Date: 1 Aug 2005 04:51:54 -0700
Links: << >>  << T >>  << A >>
Are there any time restrictions for data getting from the ADC to the
DAC ?
What about system clock of your FPGA ? Any idea how fast you want your
design
working?

Try simulating your parts of your FPGA design. VHDL testbenches ...

Rgds
Andr=E9




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