Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
>I didn't work with ActiveHDL, but I know that with ActiveHDL you >cannot do post place and route simulation. This soft is only for >behavioral simulation. > Is that because it cannot read SDF files?Article: 128976
>Now will you finally listen to your tutors and understand >that THE MOST IMPORTANT THING IS A GOOD SPECIFICATION? Always true, usually ignored!Article: 128977
Dear I heard that there is a good "partial reconfiguration" reference design : Reconfigurable Audio Filter Demo. http://www.xilinx.com/univ/FPL06_Invited_Presentation_PLysaght.pdf I am searching in xilinx site with no luck. http://www.xilinx.com/support/prealounge/protected/index.htm If someone knows where I can find, please let me know. thank youArticle: 128978
Hi, I'm currently implementing a design with a fairly large amount of static configuration data. It would be good to be able to capture the values of the registers in the FPGA and verify that they are being setup correctly. I could do this with chipscope, but there are so many registers it wouldn't leave much space for debugging of dynamic signals. After a bit of research I've found that it is possible to capture the registers and (somehow) read them back and using the .ll file (somehow) figure out the value for each net. Is anyone aware of an existing tool that can do this, or has any advice? cheers RobArticle: 128979
On Feb 11, 10:55 am, chrisde...@gmail.com wrote: <snip> 1) rts on PC side will drive FPGA cts pin. If rts on PC side = 1, then transmission from FPGA to PC will be possible. otherwise, the FPGA cannot transmit anything back to PC. 2) cts on PC side is driven by FPGA rts pin. FPGA rts pin = 1 once the receiver buffer in UART peripheral attached to microblaze is full. this will disable PC from sending any more data to microblaze on the FPGA. <snip> to paraphrase: #1: RTS(PC) -> CTS(FPGA) 1 = FPGA transmits to PC #2: RTS(FPGA) -> CTS(PC) 1 = PC _does not_ transmit to FPGA Is this really what happens, or did you mistype? -Dave PollumArticle: 128980
On Feb 11, 9:58=A0am, jon <j...@pyramidemail.com> wrote: > Can anyone assist is supplying 50 pieces of a Xilinx > XC5VLX85-2FFG1153C? =A0I also need 100 pieces of a EP2S130F1508C3N? I > can not wait the factory lead time. > > Please call > Jon E. Hansen > (949)864-7745 direct Any partial quantity would be helpful. If you know of another part that would work in place of the Xilinx please advise. Regards, Jon E. HansenArticle: 128981
Hi all,
I am sorry if this problem has been answered but I cannot find much help
from the archive.
I am trying to write and read registers from a CMOS sensor via I2C. The
SCLK and SDATA pins are pulled by 3.3V and are connected to two I/O pins
on Spartan3 FPGA.
When the FPGA is reading from SDATA, would it be always high ('1' bit
instead of '0') as it's pulled up??
Thanks!
Nick
Article: 128982Hello, I want to design FPGA-based PC oscilloscope controlled by a user of the PC. I am not sure how to provide communication between PC based application (a main program on PC; this will be written either in C or Visual Basic) and FPGA-board. A port for communication will be RS232 and I want to get my scope working under Windows XP. What you think, is writing a driver necessary for such system? (Unfortunately, I have no experience with writing drivers.)Article: 128983
just to clarify, I'm talking here about using the JTAG readback capture feature on a Virtex-5 FPGA.Article: 128984
Hello all, You have a snapshot of the XiRisc softcore processor sources ? It seems that sources are not available to download now anywhere ... Best regards.Article: 128985
On 12 Feb., 18:10, "Jean-s=E9bastien LEROY" <jean.sebastien.le...@club- internet.fr> wrote: > Hello all, > > You have a snapshot of the XiRisc softcore processor sources ? > > It seems that sources are not available to download now anywhere ... > > Best regards. where was it supposedly been seen ?? AnttiArticle: 128986
On Feb 12, 7:10 pm, "Jean-s=E9bastien LEROY" <jean.sebastien.le...@club- internet.fr> wrote: > Hello all, > > You have a snapshot of the XiRisc softcore processor sources ? > > It seems that sources are not available to download now anywhere ... > > Best regards. Hi indeed the XiRisc website has been down for more than a year. I believe what you need would be: 1. The VHDL source code distro. I have two different versions of this, one with a few more features (caches and an AMBA interface) and another one. (<1MB) 2. I have 4 different versions of the Xirisc gcc-based toolchain. The toolchain includes some additional "profiling" tools as well. (~30-50MB) 3. A set of nice (and mostly self-contained) benchmark programs. (~4MB) Which ones are OK to you? Do you need a toolchain as well? I can have a look on some ol' archives since 2002-2004 around my home PC. Will be there in a few hours (now i'm in the office). Kind regards Nikolaos Kavvadias PS1: Xirisc is nice and rather complete soft-core. Have used this for a couple of research publications. It is probably a little large for a small FPGA (200k system gates). If stripped, i believe it can fit in a S3E500. PS2: Fabio Campi and most of the Xirisc people might be around. You could ask them as well, on the status of Xirisc, the level of support etc.Article: 128987
> > You have a snapshot of the XiRisc softcore processor sources ? > > where was it supposedly been seen ?? > > Antti Hi Antti it was distributed by the University of Bologna. It is overall a good work, yet unsupported for the last 2 or 3 years. The main page (there was a mirror at unibo too) are down for about a year or so. Kind regards Nikolaos KavvadiasArticle: 128988
The Xirisc forms the base of some ST commercial products. The Picoga 2D reconfigurable array, part of the products (i believe) is not distributed with the public VHDL source codes. I have used XiRisc (without Picoga) for a proof-of-concept architecture of a zero-overhead loop controller (ZOLC), embeddable to single-issue RISCs (like most soft-cores are). The ZOLC is placed in the instruction fetch stage of the processor, and totally removes the need for looping-related operations (index increment/decrement, comparison and branch) for static and quasi-static (known during run- time, but not compile-time) loop structures involving non-perfect nesting of loops. The work has been just published in the IEEE Trans. on Computers: N. Kavvadias and S. Nikolaidis Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors http://ieeexplore.ieee.org/iel5/12/4419570/04358242.pdf?isnumber=4419570&prod=JNL&arnumber=4358242&arSt=200&ared=214&arAuthor=Kavvadias%2C+Nikolaos%3B+Nikolaidis%2C+Spiridon Kind regards Nikolaos KavvadiasArticle: 128989
On Feb 12, 9:27=A0am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > Hello, > > I want to design FPGA-based PC oscilloscope controlled by a user of > the PC. I am not sure how to provide communication between PC based > application (a main program on PC; this will be written either in C or > Visual Basic) and FPGA-board. A port for communication will be RS232 > and I want to get my scope working under Windows XP. What you think, > is writing a driver necessary for such system? (Unfortunately, I have > no experience with writing drivers.) This is the problem with modern-day systems; it's software and hardware, both. If you want to give a bad customer interface, then sure - use the serial port and you can probably call up simple communication routines on the PC for the software devolopment you still need to do. To do it right, you really should consider USB (or even ethernet) and go through the hassle of developing a real driver. The speed and integration are so much better. - John_HArticle: 128990
On 12 =C6=C5=D7, 20:30, John_H <newsgr...@johnhandwork.com> wrote: > On Feb 12, 9:27=9Aam, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > > > Hello, > > > I want to design FPGA-based PC oscilloscope controlled by a user of > > the PC. I am not sure how to provide communication between PC based > > application (a main program on PC; this will be written either in C or > > Visual Basic) and FPGA-board. A port for communication will be RS232 > > and I want to get my scope working under Windows XP. What you think, > > is writing a driver necessary for such system? (Unfortunately, I have > > no experience with writing drivers.) > > This is the problem with modern-day systems; it's software and > hardware, both. > > If you want to give a bad customer interface, then sure - use the > serial port and you can probably call up simple communication routines > on the PC for the software devolopment you still need to do. > > To do it right, you really should consider USB (or even ethernet) and > go through the hassle of developing a real driver. =9AThe speed and > integration are so much better. > > - John_H I would like to use USB for communication but a USB interface of my board (Spartan3E-1600E Microblaze Development Kit) can be used only to download design, not for communication. So I might think about using Ethernet for my project, but I don't know even where to start with this. Would you recommend any source of information about using Ethernet with FPGA for a beginner?Article: 128991
On Feb 12, 9:27=A0pm, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > Hello, > > I want to design FPGA-based PC oscilloscope controlled by a user of > the PC. I am not sure how to provide communication between PC based > application (a main program on PC; this will be written either in C or > Visual Basic) and FPGA-board. A port for communication will be RS232 > and I want to get my scope working under Windows XP. What you think, > is writing a driver necessary for such system? (Unfortunately, I have > no experience with writing drivers.) In your case the driver is going to be a piece of C/VB code which will poll the RS232 port, and arrange the bits in bytes/words. I believe you would need it as to have a PC-oscilloscope work you need to read lot of data from FPGA and send commands which is not going to be easy using hyperterminal in XP.Article: 128992
On Feb 11, 6:52=A0pm, michel.ta...@gmail.com wrote: > Hi all, > > I've a problem.. :) > I have to divide a 48MHz clock to obtain a clock with differents > frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz. > First I used flips flops to make a frequency divider, I obtained the > good frequencies, but I had skew between my master clock (48MHz) and > my divided clock. > So, I tried to use a DCM to divide frequency and to deskew divided > clock using the CLKFB input. But, the problem is the lower limit of > the DCM output frequency (1MHz) .. > > So, if anyone have an idea ? > > Thanks by advance, > > Best regards, Michel. I believe Regional clock buffers in V5 have divider functionality available......so use DCM to generate Mhz clocks and then pass lowest mhz clock to a Regional clock buffer in divider mode and you have clocks with minimum skew. only thing you would need two regional clock buffers to avoid cumilative skew on 100khz clockArticle: 128993
On Feb 11, 2:32=A0am, kian.zar...@gmail.com wrote:
> Hellow,
> i try to test xilinx IP core and with modelsim but it give error
> regarding unisim library
> # Reading D:/Modeltech_pe_edu_6.3c/tcl/vsim/pref.tcl
> # do {testfft.fdo}
> # ** Warning: (vlib-34) Library already exists at "work".
> # Model Technology ModelSim PE Student Edition vcom 6.3c Compiler
> 2007.09 Sep 11 2007
> # -- Loading package standard
> # -- Loading package std_logic_1164
> # ** Error: fftk4.vhd(37): Library unisim not found.
> # ** Error: fftk4.vhd(38): (vcom-1136) Unknown identifier "unisim".
> # ** Error: fftk4.vhd(39): (vcom-1136) Unknown identifier "unisim".
> # ** Error: fftk4.vhd(41): VHDL Compiler exiting
> # ** Error: D:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed.
> # Error in macro ./testfft.fdo line 5
> # D:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed.
> # =A0 =A0 while executing
> # "vcom -explicit =A0-93 "fftk4.vhd""
>
> what should i do?
you need to compile the unisims library into work library.
In verilog "-y unisim_path +libext+.v" serves the purpose.
Look into "xilinx synthesis and simulation guide' (from google search)
it has the complete procedure
Article: 128994On Feb 11, 4:47=A0pm, Clemens <Clemen...@yahoo.com> wrote: > Hi > > I finally have successfully sythesised my design, unfortunately the > critical path seems to be quite long so that i have a low frequency. > Can anybody tell me whats the best way to identify the critical path? > I used the Xilinx toolsuite, and there is a timing analyser so probably > this one is the best bet? Not necessary that the critical path is long a possibility is wrong relative position of clock buffer and clock pin. Timing analyser in ISE is the easiest to use, so you can start with that.Article: 128995
On a Virtex4FX, if the Vccint was run at 2.5V instead of 1.2v, what problems would someone expect? And after what period of time? For example, if it was over-voltage for 2 minutes, the GT's would be waste but the PowerPC may be partially functional.Article: 128996
nezhate wrote: > I didn't work with ActiveHDL, but I know that with ActiveHDL you > cannot do post place and route simulation. This soft is only for > behavioral simulation. Well, I will have to admit that it has been several years since I have done post place and route simulation. I really don't see much need for that in FPGA design.Article: 128997
Ouch! It is likely that ALL the junctions and gate oxides might fry at 2.5 volts (massive short) on the 1.2 volt supply! If anything at all works, you are very very lucky. I would not ship this part to anyone if it still works, as it may subsequently fail at any moment due to the extreme stress you put it through. Ouch! AustinArticle: 128998
DJ Delorie wrote: > Not much compared to the "norm" around here, but... > > http://www.delorie.com/electronics/bin2seven/ Aughhh! Isn't there a better way to do the binary to BCD conversion? Not that there'd be any difference in performance or area, just that the brute-force enumeration of all possible states seems ugly. I'd hate to do this for a 12-bit or wider conversion. JonArticle: 128999
Look at the datasheet. There is usally a section with maximum and minimum voltages. There is also an absolute maximum and minimum voltage range. This section generally comes with a warning saying something like violating this will cause damage. You *may* get away with running the device up to the absolute maximum for short periods of time. This is highly risky and will probably destroy the device and the other active devices on the PCB. Why do you want to do this? orphiend wrote: > On a Virtex4FX, if the Vccint was run at 2.5V instead of 1.2v, what > problems would someone expect? And after what period of time? For > example, if it was over-voltage for 2 minutes, the GT's would be waste > but the PowerPC may be partially functional.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z