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Messages from 77175

Article: 77175
Subject: VHDL implementation of merge-sort
From: vizziee@yahoo.com
Date: 28 Dec 2004 04:00:05 -0800
Links: << >>  << T >>  << A >>
Hi all,

Can anyone provide me inputs and tips on how the merge-sort (i.e.
merging two pre-sorted arrays) can be implemented in VHDL. I am looking
for a parallel implementation (or otherwise also) wherein I want the
merged-sorted array in the next clock cycle itself.

Thanx in advance.


Article: 77176
Subject: Primers for Handel-C
From: vizziee@yahoo.com
Date: 28 Dec 2004 04:07:01 -0800
Links: << >>  << T >>  << A >>
Hi all,

I need some good primer books on Handel-C. Plz. send-in the titles.
Thanx in advance.


Article: 77177
Subject: (Q) interconnections between microblazes
From: "Hur" <jyhur@dutepp0.et.tudelft.nl>
Date: Tue, 28 Dec 2004 13:20:34 +0100
Links: << >>  << T >>  << A >>
hello

I am looking for the methods to set the interconnection between microblazes
(MB).

For example of MESH, Consider 4 MBs.

MB1 - MB2 - MB4,
MB1 - MB3 - MB4

Could anyone guide me to preset this interconnection ?

Thankyou in advance




Article: 77178
Subject: failed to write to SDRAM
From: qudhs <qudhs@yahoo.com>
Date: Tue, 28 Dec 2004 16:29:52 +0200
Links: << >>  << T >>  << A >>
Hi!
does anyone have some experience with the Xilinx EDK OPB_SDRAM
controller?
I am using it to control an 8Mx32 external SDRAM (from Micron). It
appears that not all the writing are done correctly. for some address
space, there is no data or wrong data written to the SDRAM. in fact, the
"wrong" writing happens periodically, as following,
1c, 1d, 1e,1f, 20,21,22,23,28,29,2a,2b (round 1)
5c, 5d, 5e,5f, 60,61,62,63,68,69,6a,6b (round 2, after 0x40 from round
1)
9c, 9d, 9e,9f, a0,a1,a2,a3,a8,a9,aa,ab (round 3, after 0x40 from round
2)
.....

for all other location, the data is writting correctly. could someone
point out what could be problem of those "wrong" writing? thank you!

BRs.
-yang



Article: 77179
Subject: Google is turning usenet into crap - was Primers for Handel-C
From: nospam <nospam@nospam.invalid>
Date: Tue, 28 Dec 2004 15:35:59 +0000
Links: << >>  << T >>  << A >>
vizziee@yahoo.com wrote:

>Hi all,
>
>I need some good primer books on Handel-C. Plz. send-in the titles.
>Thanx in advance.

A typical post originating from Google groups:- 

Hi
Solve my problem.
Thanx

Searching google reveals the poster has about a dozen posts, none of which
are outside threads he started and all bar one of which were started
asking 'usenet' to solve his problem. 

Why should I (or anyone) be inclined to solve the problem of someone who
almost certainly will not even read let alone solve my problems? 

Google provides a great usenet archive and search engine, their web based
posting facility is providing a bunch of information leeches which will
turn usenet into a wasteland of unanswered questions. 

I wish I could killfile anyone posting from google, I suggest everyone else
ignores them. 


Article: 77180
Subject: Re: MAP failes after inserting ILA and ICON cores to the design
From: Ray Andraka <ray@andraka.com>
Date: Tue, 28 Dec 2004 10:47:35 -0500
Links: << >>  << T >>  << A >>
ran wrote:

>ERROR:Place -
>Due to placement constraints, the following 2 components cannot be
>placed.
>The relative offsets of the components are shown in brackets next to
>the
>component names.
>LUT sdram_port/sdram_dest/sdram_ddr_lb/ba_1_tmp_d_array_0[0]
>(0, 0)
>FF sdram_port/sdram_dest/sdram_ddr_lb/ba_1_tmp_d_array_0[0] (0, 1)
>
>ERROR:Place:120 - There were not enough sites to place a
>****************************************************
>END HERE
>****************************************************
>
>  
>
It appears that something in your design is causing the LUT adjacent to 
flip-flop to be already occupied.  I suspect it may be a global reset 
that isn't quite global which is forcing the synthesis to insert a gate 
between the LUT and the FF.  Look carefully at the synthesized output to 
see if it is what you intended.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 77181
Subject: Re: CIC filter implementation using FPGA
From: Ray Andraka <ray@andraka.com>
Date: Tue, 28 Dec 2004 10:51:40 -0500
Links: << >>  << T >>  << A >>
Sam wrote:

>Hello to all,
>
>I've followed a Hogenauer architecture.
>Can anyone help me out that what clock frequency should be provided for
>a 3-ordered CIC decimator, I've used 3 combs and 2 integrator stages in
>my design alongwith a rate changer.  
>
>Thanks,
>Samia
>
>  
>
First, the CIC usually has the same number of integrator stages as comb 
stages.  The clock frequency, in the absence of clock enables should 
match the sample rate of the higher side of the CIC (input if it is a 
decimating CIC, output if it is an interpolating CIC).  The reduced rate 
side typically works on the same clock but using clock enables to 
control the effective frequency.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 77182
Subject: Re: recommendations for a FIFO..
From: Ray Andraka <ray@andraka.com>
Date: Tue, 28 Dec 2004 10:59:08 -0500
Links: << >>  << T >>  << A >>
Moti wrote:

>Hi all,
>
>I need to build a 120 cells FIFO (cell = 24 bits) and I wondered what
>is the best way of doing it..
>My FIFO should work like a shift register, i.e. - each write strobe it
>should load a new value to the 1'st cell and discard the 120'th value.
>
>I'm using the Xilinx Spartan 2e FPGA.
>The write strobe frequency is 1Hz - so frequency is not an issue.
>
>p.s. - I'm fimiliar with the CORE GENERATOR FIFO but I dont know if it
>is the best solution.
>
>Thanks in advance, Moti.
>
>  
>
Moti, This is more like a shift register than a classic FIFO.  You don't 
need the complexity of the coregen fifo for this.  There are two 
approaches you can use: the first would be to use SRL16 elements.  
You'll need 8 chained together (I recommend using flip-flops after each 
SRL16) for each bit, or a total of 192 SRL16's.  This is advantageous if 
you need the BRAMs or the layout is such that the BRAM concentrates the 
routing too much to meet timing.  The other solution is to use dual 
ported BRAMs, using one port for read and one for write.  You can use 
them as 256x16, and either use a single mod 120 counter with a register 
delay for the write address, or use a pair of counters with one 
initialized at -120 relative to the other.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 77183
Subject: Re: RAM programming by JTAG (i need some serious help)
From: "Subra" <subra2004s@yahoo.com>
Date: 28 Dec 2004 08:26:43 -0800
Links: << >>  << T >>  << A >>
We're using Eclipse from Intellitech for doing this.  It works with
Xilinx cables.
The software has models of SRAMs and
FLASH in a library for automatically performing uploads/downloads
to/from memories connected
to an FPGA.
http://www.intellitech.com/products/eclipseboundaryscan.asp
There's also a memory test feature to check the connections before
trying to program and it gives
really good diagnostics to find the open pins.
If speed is important you might also want a faster jtag controller.
we use http://www.intellitech.com/products/ultratestaccessport.asp
It's expensive though, compared to Xilinx, US$2K, but is faster and has
some digital inputs and outputs which
can speed up FLASH programming.

Subra


Article: 77184
Subject: Re: Programming flash connected to CPLD via JTAG
From: "Subra" <subra2004s@yahoo.com>
Date: 28 Dec 2004 08:35:14 -0800
Links: << >>  << T >>  << A >>
We're using Intellitech which was recommended by broadcom datasheet for
FLASH programming with their chip.  It was only US$875.00 and has
models for most FLASH devices.  I looked and the AM29F010 is in the
Intellitech library.
http://www.intellitech.com/products/eclipseboundaryscanflash.asp.   I
ordered it online.

Regards,
Subra


Article: 77185
Subject: Re: Google is turning usenet into crap - was Primers for Handel-C
From: "Peter Alfke" <peter@xilinx.com>
Date: 28 Dec 2004 10:52:33 -0800
Links: << >>  << T >>  << A >>
Let's not throw the baby out with the bathwater!
The " vizzie" anonymous poster claims to be a scientist associated with
the indian government. He seems to think that newsgroups can be treated
like search engines, and he must not have observed the normal style in
this newsgroup.
So let's give him the benefit of the doubt, and hope that he is young
enough to learn.

My advice: Don't just jump into a newsgroup with a barrage of
questions. Get a feel for the prevailing style, and be more humble. You
still have a lot to learn, but try to learn by observing, not by
bombarding us with endless questions...
Peter Alfke

nospam wrote:
> vizziee@yahoo.com wrote:
>
> >Hi all,
> >
> >I need some good primer books on Handel-C. Plz. send-in the titles.
> >Thanx in advance.
>
> A typical post originating from Google groups:-
>
> Hi
> Solve my problem.
> Thanx
>
> Searching google reveals the poster has about a dozen posts, none of
which
> are outside threads he started and all bar one of which were started
> asking 'usenet' to solve his problem.
>
> Why should I (or anyone) be inclined to solve the problem of someone
who
> almost certainly will not even read let alone solve my problems?
>
> Google provides a great usenet archive and search engine, their web
based
> posting facility is providing a bunch of information leeches which
will
> turn usenet into a wasteland of unanswered questions.
>
> I wish I could killfile anyone posting from google, I suggest
everyone else
> ignores them.


Article: 77186
Subject: Re: Primers for Handel-C
From: Jack Klein <jackklein@spamcop.net>
Date: Tue, 28 Dec 2004 13:13:30 -0600
Links: << >>  << T >>  << A >>
On 28 Dec 2004 04:07:01 -0800, vizziee@yahoo.com wrote in comp.lang.c:

> Hi all,
> 
> I need some good primer books on Handel-C. Plz. send-in the titles.
> Thanx in advance.

You already know where Google is on the web.  Try the search engine.
By the way, leave comp.lang.c out of this.  "Handel-C" is completely
off-topic here.

-- 
Jack Klein
Home: http://JK-Technology.Com
FAQs for
comp.lang.c http://www.eskimo.com/~scs/C-faq/top.html
comp.lang.c++ http://www.parashift.com/c++-faq-lite/
alt.comp.lang.learn.c-c++
http://www.contrib.andrew.cmu.edu/~ajo/docs/FAQ-acllc.html

Article: 77187
Subject: Re: Google is turning usenet into crap - was Primers for Handel-C
From: nospam <nospam@nospam.invalid>
Date: Tue, 28 Dec 2004 19:48:13 +0000
Links: << >>  << T >>  << A >>
"Peter Alfke" <peter@xilinx.com> wrote:

>My advice: Don't just jump into a newsgroup with a barrage of
>questions. Get a feel for the prevailing style, and be more humble. You
>still have a lot to learn, but try to learn by observing, not by
>bombarding us with endless questions...

Good advice which I suspect will be read by almost no one accessing usenet
via google groups. When I look at posts coming from google groups it is
rare to find one in a thread which was not started by the poster. 


Article: 77188
Subject: Re: USB JTAG programmers?
From: Hasan K. <hasankachal@hotmail.com>
Date: Tue, 28 Dec 2004 20:30:28 +0000
Links: << >>  << T >>  << A >>
HI Alan,
A freind of mine is working on a design to make a USB programmer for
Altera and Xilinx. I think he has the HW working well but working on
the SW side (that is the trickey one), but I will ask him if he is
interested in sharing his ideas here with others.

BR,
HK

On 26 Dec 2004 15:33:27 -0800, randomdude@gmail.com (Alan Randomdude)
wrote:

>Hi there.
>
>I've been programming using a parallel byteBlaster-type lead,
>attatched to an old 486, via a network connection to my laptop. This
>is because my laptop is devoid of parallel or serial ports (oh, the
>foresight). I hear I can't use USB to Parallel adaptors (arse!) and I
>can't imagine me finding a pcmcia parallel adaptor (though I could
>make one..?) and looking on alteras site reveals they want about
>150/$300usd for their USB baster. Nads to that - Anyone know of
>anywhere selling a usb programmer for sensible (hobbyist) amounts? Or
>a way out of my situation? Thanks.
>
>-Alan / randomdude


Article: 77189
Subject: Re: vvp problem
From: Peter Monta <pmonta@www.pmonta.com>
Date: Tue, 28 Dec 2004 20:40:41 GMT
Links: << >>  << T >>  << A >>
> the source file compiles properly with iverilog. but when i invoke the
> 'vvp', it dosn't output a 'vcd' file required for gtkwave.

The -vcd argument to vvp merely sets the default dump format; you
must enable VCD dumping in your HDL with something like

initial begin
  $dumpfile("foo.vcd");
  $dumpvars();
  #100000;
  $finish;
end

Cheers,
Peter Monta

Article: 77190
Subject: Re: Google is turning usenet into crap - was Primers for Handel-C
From: vizziee@yahoo.com
Date: 28 Dec 2004 20:56:15 -0800
Links: << >>  << T >>  << A >>
Hi All,

I am really sorry to annoy the members of the group with my posts. I
have recently started using Usenet groups and learning about their
usage.

Thank-you for the constructive suggestions of you all.


Article: 77191
Subject: Re: Google is turning usenet into crap - was Primers for Handel-C
From: vizziee@yahoo.com
Date: 28 Dec 2004 21:09:22 -0800
Links: << >>  << T >>  << A >>
Hi all,

I am really sorry to annoy the members with my post. I am new in using
Usenet groups and learning the styles of using them.
Thank-you so much for constructive suggestions of you all.


Article: 77192
Subject: Re: Google is turning usenet into crap - was Primers for Handel-C
From: "someone@example.com" <a@b.com>
Date: Tue, 28 Dec 2004 21:56:50 -0800
Links: << >>  << T >>  << A >>
me too

On Tue, 28 Dec 2004 15:35:59 +0000, nospam wrote:

> vizziee@yahoo.com wrote:
> 
>>Hi all,
>>
>>I need some good primer books on Handel-C. Plz. send-in the titles.
>>Thanx in advance.
> 
> A typical post originating from Google groups:- 
> 
> Hi
> Solve my problem.
> Thanx
> 
> Searching google reveals the poster has about a dozen posts, none of which
> are outside threads he started and all bar one of which were started
> asking 'usenet' to solve his problem. 
> 
> Why should I (or anyone) be inclined to solve the problem of someone who
> almost certainly will not even read let alone solve my problems? 
> 
> Google provides a great usenet archive and search engine, their web based
> posting facility is providing a bunch of information leeches which will
> turn usenet into a wasteland of unanswered questions. 
> 
> I wish I could killfile anyone posting from google, I suggest everyone else
> ignores them.

(sorry.  flashback.)

Article: 77193
Subject: Primers for Handel-C; Handel-C efficiency
From: "Shaping" <shaping1@bellsouth.net>
Date: Wed, 29 Dec 2004 01:10:01 -0500
Links: << >>  << T >>  << A >>
Can anyone report their experiences on how efficient Handel-C's FPGA designs 
are, compared to direct VHDL designs?  I prefer to use a programming 
language to specify my state machine, because I can think more efficiently 
about the problem that way.  However, I'm concerned about how clean the 
ultimate design will be.  I'm assuming that Handel-C when processed produces 
VHDL.  I have the impression that if you don't constrain your self correctly 
in your use of Handel-C, you can end up with bulky hardware.

Shaping 



Article: 77194
Subject: Re: Primers for Handel-C; Handel-C efficiency
From: Joona I Palaste <palaste@cc.helsinki.fi>
Date: 29 Dec 2004 06:28:36 GMT
Links: << >>  << T >>  << A >>
Shaping <shaping1@bellsouth.net> scribbled the following
on comp.lang.c:
> Can anyone report their experiences on how efficient Handel-C's FPGA designs 
> are, compared to direct VHDL designs?  I prefer to use a programming 
> language to specify my state machine, because I can think more efficiently 
> about the problem that way.  However, I'm concerned about how clean the 
> ultimate design will be.  I'm assuming that Handel-C when processed produces 
> VHDL.  I have the impression that if you don't constrain your self correctly 
> in your use of Handel-C, you can end up with bulky hardware.

Whatever Handel-C is, it's not topical on comp.lang.c.

-- 
/-- Joona Palaste (palaste@cc.helsinki.fi) ------------- Finland --------\
\-------------------------------------------------------- rules! --------/
"Outside of a dog, a book is a man's best friend. Inside a dog, it's too dark
to read anyway."
   - Groucho Marx

Article: 77195
Subject: BRAM timing problem
From: "John" <piddesigner@hotmail.com>
Date: 28 Dec 2004 23:30:57 -0800
Links: << >>  << T >>  << A >>
Hi,

I am using a C to RTL generator that creates memories (VHDL) that
result in inferred Block RAMS.  During PAR, I get hold time violations.
There seems to be an implicit 0ns hold time on the data out of the
BRAM. However, the output of the BRAM goes to a latch and the enable on
the latch is a function of my clock and an enable in the generated
code.  So, the latch enable is considered a clock, but appears to be a
large skew between it and my real clock.  The Xilinx timing wizard
suggests making sure the two clocks use the same type of routing
resources.

>From what I have seen on the Xilinx site, the generated code follows
the standard approach to creating a memory (and inferring a BRAM);
address is latched on the clock edge, data out is in an assignment
statement.

Are the timing problems I see typical? If so, how do I deal with it?
Or, do I need a different memory description where the data out is
explicitly a function of the input clock edge?

thanks for your advice!


Article: 77196
Subject: Does SPI from NIOS II work?
From: vboykov@yandex.ru (vladimir)
Date: 28 Dec 2004 23:37:42 -0800
Links: << >>  << T >>  << A >>
Hello to anyone!!!
I've made some NIOS design with SPI and wrote small source code
....
 while(1) {
  usleep(10);
  alt_avalon_spi_command(SD_BASE, 0, 
                         6, write_data,
                         1, read_data,
                         flags); 
  }
....

but when I saw SCLK on Proto2 by oscilloscope, the SCLK's pin was "0" always,
SS_n was changing, MOSI was "0" and MISO was changing too (it's very strange).
I checked pin assignment and there is OK.

Maybe someone knowns what kind of problem I had there?

Thx.

Article: 77197
Subject: Re: Google is turning usenet into crap - was Primers for Handel-C
From: "avrbasic" <avrbasic@hotmail.com>
Date: Wed, 29 Dec 2004 09:09:20 +0100
Links: << >>  << T >>  << A >>
Dear mr nospam,

I agree as well, unfortunatly the same goes with other online media too,
like the www.egroups.com was good until yahoo did buy them, now it (yahoo
groups) is total crap, similarly many unmoderated mailing lists have very
high noise of people asking help for homework, etc..

In order to have better communication media I have always dreamed to have my
own news server, which is now finally setup - its not open for public as I
have not yet managed to complete the news server authorisation setup and
some other admin tasks, but I plan to announce it ASAP, for anyone
interested or having good advice please respond either to usenet or to
antti@openchip.org specially if somebody can help setting up the
readers.conf file would be great help for me. The news server is running on
my root-server under suse 9.1, I think the latest INN is installed as news
server.

Antti Lukats

"nospam" <nospam@nospam.invalid> wrote in message
news:g0s2t05dqijpkfhm8co7ijcvcd9vt5mh02@4ax.com...
> vizziee@yahoo.com wrote:
>
> >Hi all,
> >
> >I need some good primer books on Handel-C. Plz. send-in the titles.
> >Thanx in advance.
>
> A typical post originating from Google groups:-
>
> Hi
> Solve my problem.
> Thanx
>
> Searching google reveals the poster has about a dozen posts, none of which
> are outside threads he started and all bar one of which were started
> asking 'usenet' to solve his problem.
>
> Why should I (or anyone) be inclined to solve the problem of someone who
> almost certainly will not even read let alone solve my problems?
>
> Google provides a great usenet archive and search engine, their web based
> posting facility is providing a bunch of information leeches which will
> turn usenet into a wasteland of unanswered questions.
>
> I wish I could killfile anyone posting from google, I suggest everyone
else
> ignores them.
>



Article: 77198
Subject: Re: BRAM timing problem
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 29 Dec 2004 11:08:07 +0100
Links: << >>  << T >>  << A >>

"John" <piddesigner@hotmail.com> schrieb im Newsbeitrag
news:1104305457.256043.119780@f14g2000cwb.googlegroups.com...
> Hi,
>
> I am using a C to RTL generator that creates memories (VHDL) that
> result in inferred Block RAMS.  During PAR, I get hold time violations.
> There seems to be an implicit 0ns hold time on the data out of the
> BRAM. However, the output of the BRAM goes to a latch and the enable on
> the latch is a function of my clock and an enable in the generated
> code.  So, the latch enable is considered a clock, but appears to be a
> large skew between it and my real clock.  The Xilinx timing wizard

Uhhhhh, no good. Forget about messing around with gated clocks and latches.
Use clock enable signals and FlipFlops (edge triggered latches).
Do it in a clean way. Latches and gated clocks are not the choice of the day
in FPGAs.

Regards
Falk




Article: 77199
Subject: Q, connecting multiple microblazes
From: "Hur" <jyhur@dutepp0.et.tudelft.nl>
Date: Wed, 29 Dec 2004 13:10:41 +0100
Links: << >>  << T >>  << A >>
hi all

i am looking for the methods to connect multiple microblazes (MB). Questions
are

- Can we preset the interconnection between multiple microblazes (for
example 8 MBs) ?
  For example of MESH interconnection below,

MB1 - MB5
 |     |
MB2 - MB6
 |     |
MB3 - MB7
 |     |
MB4 - MB8

- If yes, could you inform me how i can realize it ?
- If no, are there any other ways to connect multiple MBs ? (for example,
other bus organization)

- How about the Picoblazes? Can we construct the MESH connections of 8
picoblazes ? What about the bus ?

Thankyou very much for help









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2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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