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Messages from 4425

Article: 4425
Subject: Re: Altera FPGA's
From: Eric Holmberg <nsteider@vt.edu>
Date: Mon, 28 Oct 1996 00:44:02 -0500
Links: << >>  << T >>  << A >>
> It is actually just a cable that goes from the parallel port to a 20-pin
> JTAG header on your board.  It is called the Flashlogic Download Cable and can
> be obtained from Altera (or built, if you prefer).
> 
> Get Application Note 45 (Configuring Flashlogic Devices) from the Web site
> (www.altera.com).
> 
> Wayne


Thanks Wayne, I got the App. Note 45 and it helped somewhat.  I also got another file (dspghd03) 
which describes the basic programming of Altera's devices.  However, I'm still at loss as to how the 
programming cable is built.  Knowing Altera, the cable is probably too expensive for my blood which 
means I'll be resorting to making it myself.

Where can I get schematics of the "driver circuit" that is contained between the DB25 parallel port 
connection and the 20-pin JDEC connector??  From reading a little, I'm almost tempted to believe 
that the driver circuit isn't really needed.  Any ideas?

-Eric  ohms@vt.edu
Article: 4426
Subject: Re: Altera Configuration EPROM Equivalents
From: CoxJA@augustsl.demon.co.uk (Julian Cox)
Date: Mon, 28 Oct 1996 10:43:15 GMT
Links: << >>  << T >>  << A >>
Steve@s-dewey.demon.co.uk (Steve Dewey) wrote:


>Hi

>Is there any manufacturer that produced windowed serial configuration
>EPROMs for Altera FLEX 8000 and FLEX 10K parts ?

>The Altera selection guide calls their parts EPROMs but my rep says they 
>are windowless OTP devices. Yes, I know I can use the BitBlaster cable to
>get the configuration straight in, but that is inconvenient for my tests.
>Neither do I want to use a conventional parallel EPROM, as that will use up
>too many of my I/Os.

>Many thanks.

>-- 
>Steve Dewey
>Steve@s-dewey.demon.co.uk
>Too boring to have an interesting or witty .sig file.


Visit the Atmel site (www.atmel.com (surprise!)) & check out their
configurators (EEPROM).

TTFN


-- 
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk              error: smartass.sig not found
Hardware development eng.                          August Systems Ltd
---------------------------------------------------------------------
                                          


Article: 4427
Subject: Re: Info/opinions wanted for PCI interface in an FPGA
From: "Austin Franklin" <darkroom@ix.netcom.com>
Date: 28 Oct 1996 14:11:39 GMT
Links: << >>  << T >>  << A >>
Dan

> My impression of the Xilinx core is that it is not very flexible.  I am 
> working on a PCI design that needs 5 functions in one device.  The Xilinx
> core only supports a single function (1 set of configuration regs) and
> only two base address registers.  
> 

My understanding is you can only have 1 set of configuration registers in a
'slot', since there is only 1 IDSEL line... I can't find anything about
this in the PCI 2.1 spec.  There might be a way, and I would like to know
if you have found out how.  The only way I can think of doing this is to be
a PCI<->PCI bridge, and have your 5 functions behind the bridge.

You can have as many base address registers as you want...up to the
configuration space max of 6 (per PCI spec 2.1, p187).

Thanks,

Austin Franklin
darkroom@ix.netcom.com

Article: 4428
Subject: Free NT device driver (with sources)
From: Laurent Moll <Laurent.Moll@devinci.fr>
Date: Mon, 28 Oct 1996 19:45:39 +0100
Links: << >>  << T >>  << A >>
I have developed a Windows NT device driver for an FPGA-based
reconfigurable board called PCI Pamette (produced by Digital Equipment
Corporation). This board is fully programmable, including the PCI
interface. The device driver is thus very atypical: it has to be really
generic and allow user-mode applications to use directly the board for
PIOs and DMAs, interrupt handling, PCI configuration cycles...

This sources of this driver are now available on the web:

PCI Pamette Windows NT Device Driver:   
http://pam.devinci.fr/~moll/ntdriver/
PCI Pamette Home Page:                  
http://www.research.digital.com/SRC/pamette/
PAM Project Home Page:                   http://pam.devinci.fr/

--

Laurent Moll

Pole Universitaire Leonard de Vinci

Phone: +33 1 41 16 71 83
Fax:   +33 1 41 16 71 71
Article: 4429
Subject: Re: Has anyone ever used a C -> Xilinx netlister?
From: shand@src.dec.com (Mark Shand)
Date: 28 Oct 1996 20:57:44 GMT
Links: << >>  << T >>  << A >>
As Jan Gray and Austin Franklin both mentioned "Digital has one".

This is actually a by-product of the PAM project run at Digital's
Paris lab from 1988 to 1994 and now carried on at the Systems Research
Center in Palo Alto (not the networking folks though they are neighbours)
and at Pole Universitaire Leonard de Vinci in Paris.

We've presented an earlier version of our package at FCCM'94 under the name
Perle1DC.  The latest incarnation is called PamDC.  You'll find it
bundled with various support software for my PCI Pamette board
at http://www.research.digital.com/SRC/pamette/Download.html

PamDC is offered primarily in support of the PCI Pamette a reconfigurable
computing platform, but it is a general purpose programming frontend
for Xilinx 3000 and 4000 devices.  The download terms permit evaluation
and unlimited non-commercial use.

I haven't advertised the package too aggressively as yet because

 a) plenty of people seem to find it on their own
 b) the simulation facilities although working, don't work
    as advertised.  They need to be revamped and redocumented.
 c) I've had plenty to do moving PCI Pamette to the product people.

I'm not sure how many designs have been made with the tool.  I would
guess in the hundreds, but not yet the thousands.

Just so people don't get confused let me state that this tool does not
take a piece of C/C++ code and compile it into a Xilinx netlist.  It
is a library that helps the user write a C++ program, the execution of
which produces a xilinx netlist.

The download page lets you download doc, the package itself and examples
of its use.

Mark Shand
shand@pa.dec.com
Article: 4430
Subject: Re: Integer Multiplier
From: Brad Taylor <blt@emf.net>
Date: Mon, 28 Oct 1996 15:06:59 -0800
Links: << >>  << T >>  << A >>
tendy the wrote:
> 
> Dear all,
> 
> Could any one please advise me about the most compact and fastest
> implementation / algorithm of 16 bit-integer-multiplier. I intend to use
> the Xilinx XC4000 series or the Altera Flex10K. Many thanks !
> 
> Regards
> Tendy
> ERG Telecommunications, Australia
> tthe@aesprodata.com.au


I can't comment on the Altera FPGAs, but a multiplier we use performs
pretty well.  It is pipelined every two adder stages and runs at 50+mhz
in XC4000e FPGAs.

32 bit      product 40+ MHz = 168 CLBs
16 bit MSBs product 40+ MHz = 144 CLBs
16 Bit LSBs product 40+ MHz =  80 CLBs 

If you need only to multiply by loadable constants (a is constant for a
period of time) usage of 4 bit LUT based multipliers will reduce the
area by factor of 4 or so.

Just a point on the map.
-
Brad

--------------------------------------------------------------

It is implemented via the following equation:

mab0 = 0                // 1 16 bit register
     +(a0<< 0 * b0<0>)  // 1 16 bit adder
     +(a0<< 1 * b0<1>)  // 1 15 bit adder
     ;


mab1 = mab0             // 1 16 bit register
     +(a1<< 2 * b1<2>)  // 1 16 bit adder
     +(a1<< 3 * b1<3>)  // 1 13 bit adder
     ;

 
mab2 = mab1             // 1 16 bit register
     +(a2<< 4 * b2<4>)  // 1 12 bit adder
     +(a2<< 5 * b2<5>)  // 1 11 bit adder
     ;

mab3 = mab2             // 1 16 bit register
     +(a3<< 6 * b3<6>)  // 1 16 bit adder
     +(a3<< 7 * b3<7>)  // 1 16 bit adder
     ;

mab4 = mab3             // 1 16 bit register
     +(a4<< 8 * b4<8>)  // 1 16 bit adder
     +(a4<< 9 * b4<9>)  // 1 16 bit adder
     ;


mab5 = mab4             // 1 16 bit register
     +(a5<<10 * b5<10>) // 1 16 bit adder
     +(a5<<11 * b5<11>) // 1 16 bit adder
     ;

mab6 = mab5             // 1 16 bit register
     +(a6<<12 * b6<12>) // 1 16 bit adder
     +(a6<<13 * b6<13>) // 1 16 bit adder
     ;

mab7 = mab6            // 1 16 bit register
    +(a7<<14 * b7<14>) // 1 16 bit adder
    +(a7<<15 * b7<15>) // 1 16 bit adder
    ;
//  112 registers 
// +256 full adders
// + 16 carry outputs 


// pipeline the inputs 
a1=a0; // 1 16 bit register
a2=a1; // 1 16 bit register
a3=a2; // 1 16 bit register
a4=a3; // 1 16 bit register
a5=a4; // 1 16 bit register
a6=a5; // 1 16 bit register
a7=a6; // 1 16 bit register
//         112 bit register          

b1=b0; // 1 14 bit register
b2=b1; // 1 12 bit register
b3=b2; // 1 10 bit register
b4=b3; // 1  8 bit register
b5=b4; // 1  6 bit register
b6=b5; // 1  4 bit register
b7=b6; // 1  2 bit register
//          56 bit register 


// pipeline the lsbs of the outputs

mab1=mab0; //  1  2 bit register
mab2=mab1; //  1  4 bit register
mab3=mab2; //  1  6 bit register
mab4=mab3; //  1  8 bit register
mab5=mab4; //  1 10 bit register
mab6=mab6; //  1 12 bit register
mab7=mab8; //  1 14 bit register
//               56 bit register

to sum it up:


32 bit product:

adders:
256 full adders     = 128 CLBs
 16 carry out       =  16 CLBs
------------------------------------
                    = 144 CLBs

pipeline registers
 112 // result msbs
  56 // result lsbs
 112 // input a
  56 // input b
----------------------
 336 // registers   = 168 CLBs

most of the registers can be hidden in the adder calles.
The result is 168 CLBs which runs at 40 + Mhz 


16 bit product MSBs:

adders:
256 full adders     = 128 CLBs
 16 carry out       =  16 CLBs
------------------------------------
                    = 144 CLBs

pipeline registers
 112 // result msbs
 112 // input a
  56 // input b
----------------------
 336 // registers   = 140 CLBs

all of the registers can be hidden in the adder cells.
The result is 144 CLBs which run at 40 + Mhz 



16 bit product LSBs:

adders:
128 full adders     =  64 CLBs
 16 carry out       =  16 CLBs
------------------------------------
                    =  80 CLBs

pipeline registers
  56 // result msbs
  56 // result lsbs
  56 // input a
  56 // input b
----------------------
 224 // registers   = 112 CLBs

most of the registers can be hidden in the adder cells.
The result is 112 CLBs which run at 40 + Mhz 

Note each adder cell includes an and gate to implement the multiply by a
bit of b. This can be folded into the 4LUT supplied by the 4K FPGA

 -

Article: 4431
Subject: PCI Compliance in FPGAs
From: "Steven K. Knapp" <stevek@xilinx.com>
Date: Mon, 28 Oct 1996 16:43:08 -0800
Links: << >>  << T >>  << A >>
Shawn Lee wrote:
> 
> I want to use a FPGA to replace some PAL chips, and a PCI controller
> if I can. I heard that there are some PCI-compliant FPGAs. What does
> the "PCI-compliant" mean? Does it mean there are already some PCI
> controlling part integreted in it?

Full PCI compliance means that the device can meet the PCI
specification's AC and DC parametric values and that it behaves
according to all of the PCI bus protocol operating rules.  The Xilinx
LogiCore PCI interface has been tested for PCI compliance.  You can find
out more about the Xilinx LogiCore PCI Interface at

http://www.xilinx.com/products/logicore/lcmodule.htm#PCI

There is a PCI applications overview available at

http://www.xilinx.com/apps/pci.htm
> 
> Another question: Who knows the actual size of the XC3164A and XC4000E.
> I can not find them on the web.

If you are looking for gate capacity, then the XC3164A is about 4,000 to
5,000 usable gates while the XC4000E/EX family ranges from about 2,000
usable gates to over 50,000 gates. 

You can find out more on the XC3164A at

http://www.xilinx.com/products/fpgaspec.htm#XC3000

and more about the XC4000E/EX FPGA family at

http://www.xilinx.com/products/fpgaspec.htm#XC4000

Thank you for your interest in Xilinx programmable logic.
---------------------------------------------------------------
Steven K. Knapp                    Xilinx, Inc.
Vertical Applications Manager      2100 Logic Drive
(408) 879-5172 (voice)             San Jose, CA 95124
(408) 879-4442 (FAX)               U.S.A.
E-mail: stevek@xilinx.com          Web:  http://www.xilinx.com
Article: 4432
Subject: Re: Multipliers on Xilinx FPGAs
From: "Steven K. Knapp" <stevek@xilinx.com>
Date: Mon, 28 Oct 1996 16:58:43 -0800
Links: << >>  << T >>  << A >>
> Xilinx has a very good application note on this, using partial products.
> Chech www.xilinx.com.  I'm sure it's there somewhere.
> 
> -Matt

Well, actually the information is not yet available on the Xilinx web
site (but it is coming soon).  In the meantime, just send an E-mail to
logicore@xilinx.com indicating your interest in multipliers.  We'll send
out the information ASAP.
---------------------------------------------------------------
Steven K. Knapp                    Xilinx, Inc.
Vertical Applications Manager      2100 Logic Drive
(408) 879-5172 (voice)             San Jose, CA 95124
(408) 879-4442 (FAX)               U.S.A.
E-mail: stevek@xilinx.com          Web:  http://www.xilinx.com
Article: 4433
Subject: Question on Wavelet implementation
From: hajimow@unconfigured.xvnews.domain Sayed
Date: Tue, 29 Oct 1996 04:51:17 GMT
Links: << >>  << T >>  << A >>

Hi:

	Does anybody know any paper or reference on implementation of one and two
dimensional of wavelet transform on Xilinx FPGAs.I am very interested on the number
of resources (CLBs) needed for such implemetations.
Any help or comment is welcome.

Sayed


Article: 4434
Subject: Re: VHDL for Xilinx designs?
From: granville@decus.org.nz
Date: 29 Oct 96 22:21:48 +1300
Links: << >>  << T >>  << A >>
>>
>>I have some clients who I told them they would only have to pay me what I
>> >save them.  For one, I converted their VHDL to schematics, went down two
>> >part sizes, and two speed grades, saving $46 per board, and the volume is
>> >in the thousands!

 I'm not an accountant, but if they pay you what you take off the chip cost
aren't they no better off ? ;-)

>>
>> I bet, optimization of the VHDL to better VHDL had saved more than $46!

>Personally I belive that for many instances schematic is at least as good as
>a HDL.I tend to think that your above statement would loose you your money!
-snip-
> This is why the interlectual property (IP) market is taking off.
> It should however be noted with respect to this that many IP vendors
> provide different HDL model for
> a) different target technologies and b) different synthesis tools.  The
> reason?
> Because HDLs have to be written taking into account both these facts to
> produce optimal results.

 This is an interesting thread, so I thought I would add some info from
one in the IP market, and using HDL at the lower end ( PLD & CPLD ) rather
than FPGA.
 The higher end CPLD's are similar to the FPGA's, with limited OR term
macrocells, and generally fewer of them!.

 We prefer HDL because of the reasons already discussed, but also because of

 a) You can view the SOURCE, SimulationIP, and Simulation results all at
 the same time, and with focus on a small section of the design.

 b) Schematic conversion involves another step

 c) Version control. Not mentioned yet, but this is critical to testing,
 and for future design edits, often what was tried, and rejected is more
 important that what was used !
 ALL of this info is contained in the HDL file. Not so easy on Schematics.

 d) Changes are simpler in HDL format -eg JK to D or T, or Clk,CE
 designs, or even a MIX of D & T, adding test loading, reset control etc....

 We have been experimenting with state engines, and non binary counters
 with interesting results. Where the 'peak term usage' is critical
 for Macrocell usage in EPLDS ( and speed in FPGA ), a mixture of T and
 D ff's is often best, rather than all T or All D.

> I usually find it easier to visulise things in schematic rather than text
> but I'd rather design large state large state machines in a HDL. >John

 Agreed. See d above.

This thread is rather like the .ASM vs C discussions :).
We stress that users should study and understand what the compiler outputs,
for a given input expression.

 Often the results are smaller ( fewer terms ) than what would be on
a schematic.


There are also optimise switches that can affect both the compile speed,
and finished result drastically. These can be commented in the source
code as well.

 - jim granville.

===== Mandeno Granville FAX +64 9 6301 720, 128 Grange Rd Auckland 3 NZ ======
* Developers and suppliers of HDL PLD/EPLD applications libraries            *
* for Microcontroller expansion and interface.           		     *
* x51 C, Pascal & Modula-2 Compilers, Simulators, Emulators & FLASH Pgmrs    *
* Contact : Jim Granville . Email above.                                     *

Article: 4435
Subject: Novice: Flex 8000 ?
From: Chris Herron <ncah@dcs.ed.ac.uk>
Date: Tue, 29 Oct 1996 12:32:00 GMT
Links: << >>  << T >>  << A >>
Can anybody tell me what the fastest Flex 8000 model is?
I'd also appreciate any pointers to beginner's AHDL stuff.

Cheers,
Chris H. (ncah@dcs.ed.ac.uk)

Article: 4436
Subject: Re: VHDL for Xilinx designs?
From: "Austin Franklin" <darkroom@ix.netcom.com>
Date: 29 Oct 1996 15:58:47 GMT
Links: << >>  << T >>  << A >>

>  a) You can view the SOURCE, SimulationIP, and Simulation results all at
>  the same time, and with focus on a small section of the design.

You can do the same thing with schematics....

>  b) Schematic conversion involves another step

In my environment, VHDL requires three additional steps.  Since most people
run the tools in a script (for 'casual' changes, not for the first time
through the tools though...) this isn't a real problem.
 
>  c) Version control. Not mentioned yet, but this is critical to testing,
>  and for future design edits, often what was tried, and rejected is more
>  important that what was used !
>  ALL of this info is contained in the HDL file. Not so easy on
Schematics.

I agree you would end up with very messy schematics if you annotated every
change.  Since we do backups regularly, revision control has not been a
problem.  It is nice to see what changes have been made in the code though.
 I do like that feature of text based designs.

>  d) Changes are simpler in HDL format -eg JK to D or T, or Clk,CE
>  designs, or even a MIX of D & T, adding test loading, reset control
etc....

In some instances, yes, in some no.  It's all what you like better, reading
through thousands of lines of text, or looking through pages of schematics.
 I believe schematics are clearer for data path than an HDL, and HDLs are
clearer for some logic and definately for state machines.


> This thread is rather like the .ASM vs C discussions :).
> We stress that users should study and understand what the compiler
outputs,
> for a given input expression.

With schematics you don't need this understanding.

>  Often the results are smaller ( fewer terms ) than what would be on
> a schematic.

This is only true if the schematic designer doesn't know how to do logic
optimization well.  I have never seen any HDL that can better a well done
schematic.  At best it can equal it.  Also, timing can be compromised by
having fewer terms...you may want them separated out because they are used
in different sections of the chip.

Sometimes in FPGAs you want to duplicate logic, or control the timing in a
particular path, and you can do that explicitly with schematics.  HDLs, it
is harder to control.  It seems not very practical (not my first choice of
words) to have to 'know' what the compiler is going to do with every
instance of your HDL code.  For slow designs, there is nothing wrong with
VHDL because you really don't care if it is implemented optimally.

For designs where you are really pushing the limits of the technology,
either for speed or density, only schematics will give you the optimization
and control necessary to successfully implement the design.  With either
technology, floorplanning is really the key to both timing and routing
efficiency.  My experience is that HDLs are much harder to control the
floorplanning with.  This is an easy fix for the EDA mfgs of HDL compilers.
 They just need to use intelligent, consistent naming of instances, like
TBUFs and DFFs.


Austin Franklin
darkroom@ix.netcom.com

Article: 4437
Subject: Re: Question on Wavelet implementation
From: peck@cs.ucla.edu (John C. Peck, Jr.)
Date: Tue, 29 Oct 1996 19:26:12 GMT
Links: << >>  << T >>  << A >>
Here's one:

J. Villasenor, B. Belzer, and J. Liao, Wavelet Filter Evaluation for
Efficient Image Compression, IEEE Transactions on Image Processing,
August  1995. 

Document is available here:

http://www.janet.ucla.edu/DMSR/research.highlights.html#scalable

hajimow@unconfigured.xvnews.domain Sayed wrote:

>
>Hi:
>
>	Does anybody know any paper or reference on implementation of one and two
>dimensional of wavelet transform on Xilinx FPGAs.I am very interested on the number
>of resources (CLBs) needed for such implemetations.
>Any help or comment is welcome.
>
>Sayed
>
>

Article: 4438
Subject: Need fast/small SRAMS
From: Richard Schwarz <aaps@erols.com>
Date: Tue, 29 Oct 1996 14:27:01 -0500
Links: << >>  << T >>  << A >>
I am looking for fast and small package SRAMS <15ns and pref. 16x64K.
Please email aaps@erols.com



Richard


Article: 4439
Subject: Re: Info/opinions wanted for PCI interface in an FPGA
From: dan.bartram@gtri.gatech.edu (Dan Bartram)
Date: Tue, 29 Oct 96 19:47:05 GMT
Links: << >>  << T >>  << A >>
In article <01bbc4d9$da188d10$42c220cc@drt1>, "Austin Franklin" <darkroom@ix.netcom.com> wrote:

>My understanding is you can only have 1 set of configuration registers in a
>'slot', since there is only 1 IDSEL line... I can't find anything about
>this in the PCI 2.1 spec.  There might be a way, and I would like to know
>if you have found out how.  The only way I can think of doing this is to be
>a PCI<->PCI bridge, and have your 5 functions behind the bridge.
>
>You can have as many base address registers as you want...up to the
>configuration space max of 6 (per PCI spec 2.1, p187).
>

My interpretation of the spec (Rev 2.1) is as follows:

There may be some confusion with the terminology.  I refer to a "device"
as a physical slot on the bus.  There are two types of devices - 
single-function and multi-function.  A single-function device seems to be
the most common, and it only has 1 256-byte configuration space.

In the first configuration header, the Header Type field contains a bit (#7) 
that is used to identify a multi-function device.  Refer to pages 187-189 of 
the spec.  

There are two types of configuration accesses - Type 0 (local) and Type 1 
(another bus across a bridge.)  Refer to pages 84-88 of the spec - it 
describes the interpretation of the two access types.  Bits 10:8 allow 
selection of 8 functions on a multi-function device.  Bits 7:2 allow selection 
of 64 double-word locations.  If you use these bits (10:2) and the 
required control signals, you can locate any of 64 double-words in 8 different 
spaces.  

On page 88, it says that multi-function devices must decode bits 10:8 and only 
respond if that function is implemented.  This is done by asserting the DEVSEL 
line.  Function 0 must always be implemented, but the others (1 through 7) can 
be implemented in any order, even skipping some.  

Referring to page 185 of the spec, it says that multi-function devices must
provide a Configuration Space for each function implemented.

I feel that the spec is rather vague on the implementation of multi-function 
devices.  I have also referenced the book titled "PCI Hardware and Software, 
Architecture and Design" by Edward Solari and George Willse.  I checked my 
interpretation with this book and it seemed to line up.

I have not implemented my design yet, as I am still coming up to speed on the 
spec and requirements to be met.  I am sure I will run into some obstacles at 
some point.  Perhaps if someone reading this thread has implemented a 
multi-function device they could offer some further insight.

Any comments on the above are welcome.

Thanks,

Dan

****************************************************************************
Dan Bartram, Jr.
Internet:  dan.bartram@.gtri.gatech.edu
****************************************************************************
Article: 4440
Subject: Re: PCI-compliant VHDL module
From: sdube@highend.com (Shawn Joel Dube)
Date: Tue, 29 Oct 1996 20:29:43 GMT
Links: << >>  << T >>  << A >>

>1, PCI-compliant VHDL module.

Altera has a free design kit for doing PCI interfacing with their
chips.  They include several different designs in AHDL.  Check their
web-page at //www.altera.com.


___________________________________________________________

   Shawn Joel Dube                 High End Systems
   sdube@highend.com               Austin, Texas, USA
___________________________________________________________

Article: 4441
Subject: Re: Altera Configuration EPROM Equivalents
From: pss1@hopper.unh.edu (Paul S Secinaro)
Date: 29 Oct 1996 21:41:59 GMT
Links: << >>  << T >>  << A >>
fliptron@netcom.com (Philip Freidin) writes:

>In article <846359819snz@s-dewey.demon.co.uk> Steve@s-dewey.demon.co.uk writes:
>>
>>Hi
>>Is there any manufacturer that produced windowed serial configuration
>>EPROMs for Altera FLEX 8000 and FLEX 10K parts ?
>>The Altera selection guide calls their parts EPROMs but my rep says they 
>>are windowless OTP devices.

>Atmel manufactures an EEPROM device which for your needs is probably just 
>as good. It is an electrically programmed/Re-programmed device, so it does
>not require a window or a sun-tanning lamp. Part numbers are AT17C65,
>AT17C128, and AT17C256.  Make sure you have a device programmer that
>knows SPECIFICALLY about the Atmel parts !!! A programmer that knows
>about the xx17Cxx parts from other vendors will not be able to program
>the Atmel parts. Note that these parts are programmed at 5 Volts only, so 
>building your own programmer is not too hard, and could be even done 
>in-circuit, if enough of your system is working without your FPGA being 
>loaded.

Just a note/warning: According to the FAQ on the Atmel web site
(www.atmel.com), the only package that's compatible with Altera is the
8-pin DIP.  Apparently Altera's PLCC20 package has a wierd pinout
(thanks a lot, Altera).

-Paul



-- 
Paul Secinaro (pss1@christa.unh.edu)
Synthetic Vision and Pattern Analysis Laboratory
UNH Dept. of Electrical and Computer Engineering
Article: 4442
Subject: Altera EPX880
From: Eric Holmberg <nsteider@vt.edu>
Date: Tue, 29 Oct 1996 21:39:45 -0500
Links: << >>  << T >>  << A >>
Needed!!  I'm now in need of an EPX880 pronto!  My 
professor wants a demo on November 4 instead of 
December 13!!!

I'm looking for the PLCC 84-pin version.  If 
anybody has a few to sell or knows of a 
distributor (I'm currently contacting Altera) let 
me know!

Please e-mail me directly.

thanx

--Eric ohms@vt.edu
Article: 4443
Subject: Re: Synplicity vs. FPGA Express
From: ecla@world.std.com (alain arnaud)
Date: Wed, 30 Oct 1996 14:45:07 GMT
Links: << >>  << T >>  << A >>
Brad Hutchings (hutch@ee.byu.edu) wrote:
: waynet@goodnet.com (Wayne Turner) writes:


: > >: Synopsys FPGAExpress synthesis tools.  
: > >
: > >        I have used both. Obviously if you need Altera support Synplicity is
: > >        the way to go until Synopsys comes out with an Altera library.

: What kind of a library?  We have been using Synopsys with Altera on
: and off now for about 2-3 years. The results were good enough for what
: we did. Although there are some interfacing problems between Synopsys
: and Altera we never noticed a big problem. We are currently using
: Synopsys FPGA compiler to map some Altera 10K designs.

	I am referring to FPGA Express which is new synthesis tools for PCs.
	FPGA Express currently has support for Xilinx only.
	The workstation tools (DC and FPGA Compiler) have Altera libraries.
Article: 4444
Subject: Re: VHDL for Xilinx designs?
From: garyk@svpal.svpal.org (George Noten)
Date: 30 Oct 1996 16:57:12 GMT
Links: << >>  << T >>  << A >>
Austin Franklin (darkroom@ix.netcom.com) wrote:


: This is only true if the schematic designer doesn't know how to do logic
: optimization well.  I have never seen any HDL that can better a well done
: schematic.  At best it can equal it.  Also, timing can be compromised by
: having fewer terms...you may want them separated out because they are used
: in different sections of the chip.

: Sometimes in FPGAs you want to duplicate logic, or control the timing in a
: particular path, and you can do that explicitly with schematics.  HDLs, it
: is harder to control.  It seems not very practical (not my first choice of
: words) to have to 'know' what the compiler is going to do with every
: instance of your HDL code.  For slow designs, there is nothing wrong with
: VHDL because you really don't care if it is implemented optimally.

: For designs where you are really pushing the limits of the technology,
: either for speed or density, only schematics will give you the optimization
: and control necessary to successfully implement the design.  With either
: technology, floorplanning is really the key to both timing and routing
: efficiency.  My experience is that HDLs are much harder to control the
: floorplanning with.  This is an easy fix for the EDA mfgs of HDL compilers.
:  They just need to use intelligent, consistent naming of instances, like
: TBUFs and DFFs.

 You can write an HDL that is absolutely equivalent to schematics.  I did
 it several times for Xilinx designs using library primitives as components.
 It gives you an option to use a higher level description for non-critical
 parts and a netlist-level description for all the rest.  Another reason
 for doing it is bad quality of the synthesizer.  The one I am using (View- 
 Logic PROsynthesis ) is just terrible.

	George.

Article: 4445
Subject: Re: VHDL for Xilinx designs?
From: husby@fnal.gov (Don Husby)
Date: 30 Oct 1996 18:48:54 GMT
Links: << >>  << T >>  << A >>
Austin Franklin  darkroom@ix.netcom.com wrote:
> In some instances, yes, in some no.  It's all what you like better, reading
> through thousands of lines of text, or looking through pages of schematics.
>  I believe schematics are clearer for data path than an HDL, and HDLs are
> clearer for some logic and definately for state machines.

I'd like to vote too:
  I use schematics (Viewlogic), but have a tool that lets me put
logic equations right on the schematic page.  For me, this is the
best of both worlds since I can see data paths and textual
representation of my random logic all together.  It also gives me
good control of mapping and signal naming.  My hope is that eventually
this will be a standard.

  Strangely enough, I sometimes use the logic equations instead of
a schematic symbol to specify a data path.

Article: 4446
Subject: Re: Multipliers on Xilinx FPGAs
From: waynet@goodnet.com (Wayne Turner)
Date: Wed, 30 Oct 96 19:40:22 GMT
Links: << >>  << T >>  << A >>
In article <327556C3.3464@xilinx.com>, stevek@xilinx.com wrote:
>> Xilinx has a very good application note on this, using partial products.
>> Chech www.xilinx.com.  I'm sure it's there somewhere.
>> 
>> -Matt
>
>Well, actually the information is not yet available on the Xilinx web
>site (but it is coming soon).  In the meantime, just send an E-mail to
>logicore@xilinx.com indicating your interest in multipliers.  We'll send
>out the information ASAP.
>---------------------------------------------------------------
>Steven K. Knapp                    Xilinx, Inc.
>Vertical Applications Manager      2100 Logic Drive
>(408) 879-5172 (voice)             San Jose, CA 95124
>(408) 879-4442 (FAX)               U.S.A.
>E-mail: stevek@xilinx.com          Web:  http://www.xilinx.com

Or if you would rather not wait for Xilinx, then get App Note 53 from the 
Altera web site (www.altera.com) "Implementing Multipliers in FLEX 10K 
Devices".  It details how to use the Embedded Array Block (EAB) to implement 
multipliers as lookup tables rather than having to do the actual 
multiplication.  If you want to do the multiply in the actual logic cells of 
the device (in case you wanted to save the EAB to use as RAM, for example), 
then get App Notes 132, 133 and 134 that detail different ways to implement 
multipliers in Flex8000, which would be essentially the same method used to 
implement it in the LOGIC (non-RAM) portion of the Flex 10K device.  All 
design files for these examples are on the FTP site as well and are named in 
the App Notes. Keep in mind that there are faster speed grade parts out now 
then were available at the time the App Notes were written, so the performance 
will probably be better than that listed if you use the fastest speed grade 
device.

Good Luck!

Wayne
Article: 4447
Subject: Re: Synplicity vs. FPGA Express
From: waynet@goodnet.com (Wayne Turner)
Date: Wed, 30 Oct 96 19:43:56 GMT
Links: << >>  << T >>  << A >>
In article <uktlocunbuj.fsf@kaboom.ee.byu.edu>, Brad Hutchings <hutch@ee.byu.edu>
        <Dzu2v6.Hu8@world.std.com> <54qphk$1jdq@news.goodnet.com> wrote:
>waynet@goodnet.com (Wayne Turner) writes:
>
>> 
>> In article <Dzu2v6.Hu8@world.std.com>, ecla@world.std.com (alain arnaud)
> wrote:
>> >Dennis Morel (dmorel@flir.com) wrote:
>> >
>> >
>> >: I was just wondering if anyone has benchmarked the Synplicity and/or
>> >: Synopsys FPGAExpress synthesis tools.  
>> >
>> >        I have used both. Obviously if you need Altera support Synplicity is
>> >        the way to go until Synopsys comes out with an Altera library.
>
>What kind of a library?  We have been using Synopsys with Altera on
>and off now for about 2-3 years. The results were good enough for what
>we did. Although there are some interfacing problems between Synopsys
>and Altera we never noticed a big problem. We are currently using
>Synopsys FPGA compiler to map some Altera 10K designs.

The original thread referred to FPGA Express (as shown in the heading), which 
is Synopsys' new PC-based tool.  They will have Altera support in FPGA Express 
in early 1997.  Currently they do not.

Wayne
Article: 4448
Subject: Configuring FPGA before PCI accesses config regs
From: sdube@highend.com (Shawn Joel Dube)
Date: Wed, 30 Oct 1996 19:46:21 GMT
Links: << >>  << T >>  << A >>

On a PCI bus, does anyone know how long after the RST# line goes high
that IDSEL is asserted for accessing the configuration registers?  In
other words, how much time do I have to configure my FPGA.  

I've checked the PCI spec and couldn't find this anywhere.  Is there a
spec on this or does anyone know the typical time between the two
signals?


___________________________________________________________

   Shawn Joel Dube                 High End Systems
   sdube@highend.com               Austin, Texas, USA
___________________________________________________________

Article: 4449
Subject: Re: Altera Configuration EPROM Equivalents
From: John McDougall <johnm@newbridge.com>
Date: Wed, 30 Oct 1996 14:55:29 -0500
Links: << >>  << T >>  << A >>
Steve Dewey wrote:
> 
> Hi
> 
> Is there any manufacturer that produced windowed serial configuration
> EPROMs for Altera FLEX 8000 and FLEX 10K parts ?
> 
> The Altera selection guide calls their parts EPROMs but my rep says they
> are windowless OTP devices. Yes, I know I can use the BitBlaster cable to
> get the configuration straight in, but that is inconvenient for my tests.
> Neither do I want to use a conventional parallel EPROM, as that will use up
> too many of my I/Os.
> 
> Many thanks.
> 
> --
> Steve Dewey
> Steve@s-dewey.demon.co.uk
> Too boring to have an interesting or witty .sig file.

I remember a while ago I think it was Xicor who had a serial EEPROM
which you could use on a Xilinx.


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