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Messages from 31350

Article: 31350
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Sun, 20 May 2001 03:10:38 -0600
Links: << >>  << T >>  << A >>
Neil Franklin wrote:
> 
> Speed is not the problem. TS-10 emulator on its authors PIII-800 runs
> roughly twice the speed of an KL-10 (the fastest PDP-10 model). Any
> faster will be detrimental to the experience.

Look if speed is a problem I have a P150. I am sure for a small fee
I will take your PIII and give you my computer so the emulator
will run at the right speed. Why a even have a old "Archive" tape
cartridge ( 150 meg ) that can give real tape I/O. 

> Not to mention the missing blinkenlights (drawing them in an GUI is
> not exactly the same thing). Light bulbs (no LEDs those days!) just
> are different to look at.

You can still get the bulbs!

> My present simple straight forward FPGA design (one clock per memory
> or register file access plus a bit of waste) is already with 24MHz at
> the same speed level as TS-10.

I still think small anti-fuse FPGA's are the way to go,
as for the BIG computer look - it needs to go into a rack! -.
With the smaller FPGA's (84 pin plcc's) you can 
put the cpu on two boards (custom bit slice) and have the front panel logic.


> A fully pipelined FPGA (think 486 level pipelining) should be over 10
> times original speed. Assuming that is the aim.

The PDP-10 other than the floating point looks to memory bound rather than
CPU bound. Pipelining may not help much.
 
> Actually an extended-addressing (30bit instead of 18bit) processor,
> running at 486 speed, with some form of graphical output, could be
> interesting for someone wanting to use an PDP-10 OS for daily work,
> just for the insanity of it.

From what little I have seen of the PDP-10 the addressing is
still only 18 bit segments (256kw). You would have a worse
mess than intel's 8088. I think PDP-10 flavored cpu could be designed
with 30+ bit addressing, but the you would have to write you own software!

Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk

Article: 31351
Subject: Re: Nasty "register ordering" in map
From: hamish@cloud.net.au
Date: Sun, 20 May 2001 10:52:32 GMT
Links: << >>  << T >>  << A >>
John_H <johnhandwork@mail.com> wrote:
> Although it doesn't look like the dsgnmgr user interface allows me to access the feature, I remembered seeing the register ordering issue in the tools.

> If you try the command line form of the map utility, "map -h virtexe" will give you the options applicable to the Virtex-E family.  The -r option disables register ordering.

I don't want to disable it globally; for real data buses, it saves area
and improves timing dramatically if you have a long pipeline with a
wide bus. I want a way to disable it (or enable it) signal by signal.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 31352
Subject: Re: Xilinx Service Pack 8 Now Available
From: hamish@cloud.net.au
Date: Sun, 20 May 2001 10:59:50 GMT
Links: << >>  << T >>  << A >>
Chris G. Schneider <chris@cgschneider.com> wrote:
> They corrected the speed files! 

Tbcko (block RAM clock to out) for the -8 speed grade increased by over 100%
(~1.1ns to ~2.4ns). 

Good luck!


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 31353
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Neil Franklin <neil@franklin.ch.remove>
Date: 20 May 2001 16:53:18 +0200
Links: << >>  << T >>  << A >>
Rick Collins <spamgoeshere4@yahoo.com> writes:

> Neil Franklin wrote:
> >
> > gah@ugcs.caltech.edu (glen herrmannsfeldt) writes:
> >
> > > There is now a software emulator that runs under most unix
> > > systems.  The remaining bugs are rapidly being worked out.
> >
> > Actually multiple of them: TS-10, E-10 and simh2.6
> >
> > But emulators are not quite the same thing as real hardware. :-)
>
> Depends on the hardware. I would be willing to bet that an emulator on a
> current desktop will run faster than the original machine from when, the
> late 70's, early 80's?

Speed is not the problem. TS-10 emulator on its authors PIII-800 runs
roughly twice the speed of an KL-10 (the fastest PDP-10 model). Any
faster will be detrimental to the experience.

It is more the "look and feel" thing. A program in an window on an PC
desktop just does not look or feel like on an VT05 connected to real
hardware. Just not primitive enough for that gut feeling.

Not to mention the missing blinkenlights (drawing them in an GUI is
not exactly the same thing). Light bulbs (no LEDs those days!) just
are different to look at.


> Even if you clone the hardware in an FPGA, I bet
> an emulator can keep up unless you do a lot of opimizations such as

My present simple straight forward FPGA design (one clock per memory
or register file access plus a bit of waste) is already with 24MHz at
the same speed level as TS-10.


> pipelining, etc which the original machine likely used sparingly.

AFAIK, pipelined instruction fetch was used from the KI-10 onwards,
nothing more.

A fully pipelined FPGA (think 486 level pipelining) should be over 10
times original speed. Assuming that is the aim.

Actually an extended-addressing (30bit instead of 18bit) processor,
running at 486 speed, with some form of graphical output, could be
interesting for someone wanting to use an PDP-10 OS for daily work,
just for the insanity of it.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 31354
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Sun, 20 May 2001 09:41:49 -0600
Links: << >>  << T >>  << A >>
Neil Franklin wrote:
> Ehm, that is the TS-10 authors (Timothy Stark) PIII-800.

My offer applies to anybody, who wants a slower computer. <grin>
 
> I have an AMD K6/2-350. It manages to compile my PDP-10 design in its
> present state in less than 1 minute (many thanks to JBits being fast).
> BoardScope tends to page a bit heavy while startup because of only 64M
> RAM.

That is one thing I don't like about ram based FPGA's and small
CPU's. Our 16 bit <insert favorite class> machine access 64kb of memory
but the FPGA rom is 512 KB.

> But not drive them from any emulator I know of. And changing that
> would be a _major_ speed killer. Developing an FPGA is more fun.

That is a simple timer interrupt say every 1/2 a second.But your right
the FPGA is more fun.
 
> Try an competing design! We have 3 emulators. So far there are only 2
> FPGA projects (my one-hot state machine and Heinz Wolters microcoded,
> both using SRAM based FPGAs).

Only after I get the 500 lbs of paper documents.
The 10 was a DO ALL processor with all the features.
 
> Erm, you say here anti-fuse and in your post just before that you use
> Altera and Quicklogic. All Altera I know are SRAM based and Quicklogic
> is AFAIK[1] Flash. What chip series are you using?

The Quicklogic data is on CD rom only. ( Free  mind you ).
I am using a Altera 10K10 ( 84 plcc ) chip but I also have
designed for the Quicklogic PASIC 2 series ( Anti-fuse )
QL2007 chip ( 480 logic blocks ). The quick logic block is
some simple gates feeding the input of a 4 input multiplexer
block followed by a Flip/Flop. 
One nice feature of Altera is they have a large library of TTL macros useful for
converting old TTL designs. 
 
> [1] when I was selecting architecture I failled to find an data sheet
> on their web site, only sales presentations. Dito Gatefield. Not to
> mention not even getting into Actels site (needs Macromedia Flash
> plugin) and Lattices site (wants tons of privacy invading questions
> answered). Altera, Atmel, Lucent and Xilinx gave me their data sheets
> without problems. From them I selected Xilinx Virtex/Spartan-II.

At the time I got my FPGA board the Altera chip was the only
one that would fit my design and still be a usable chip and have free
software. I refuse to use chips that need FANCY PCB manufacturing.
 

> I have no space to put one of them. Single room 4.5x3.5m and so.
OK a very thin RACK. ( smile )

> I also suspect caching to be worth more, particularle separate I and D
> caches. OTOH writing accumulators may be doable pipelined. Add to
> that parallel read and pipelining instruction fetch.

Mind you for a PDP-10 FPGA running at the same speed as
a real machine the cache module could be a
dummy module as main memory would be at cache speeds already.
Ben.
PS. I still have finish my FPGA 24 bit cpu before I corner the
36 bit market.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk

Article: 31355
Subject: Re: Can anyone comment on the difference between modelsim PE and XE
From: cantsay@here.com (Marko)
Date: Sun, 20 May 2001 17:14:51 GMT
Links: << >>  << T >>  << A >>
ModelSim XE is built from version 5.3d of the standard ModelSim
product.  ModelSim PE is currently at version 5.5a.  There are some
differences, but the two products are quite similar.

When I used XE, I ran into the size limitation well before 5000 lines.
I think it occurred at about 300 lines.  I think this limit is
actually more complicated and not just a simple function of the number
of lines.  When you hit the limit, you definitely know it.  The
simulator actually stops running for several seconds.  Even simple
simulations like an 8-bit counter may take minutes to run.

One advantage of XE is that it will simulate both Verilog and VHDL.  

Also, XE is supported only by Xilinx - not by Model Technology.


mchampion@Xbigfoot.com (remove the X to send me email)

Article: 31356
Subject: Re: Counter problem in Altera AHDL...
From: John_H <johnhandwork@mail.com>
Date: Sun, 20 May 2001 13:15:24 -0700
Links: << >>  << T >>  << A >>
If the outputs aren't lined up in time nicely, perhaps the registers aren't placed in the output blocks. The I/O pins have a single register adjacent to the pin. If the register is in an internal Logic Element, the routing path could be much different for one or two bits compared to the rest. 17.5MHz isn't very fast, but if the glitches you're getting are on the order of 1ns, the wiring on the PCBoard could even contribute to the skew. 

 Maybe it's time to step up to Synchronous RAMs so you can register the address lines at the SRAM input rather than expecting the asynchronous RAM to maintain good skew throughout the path.

Article: 31357
Subject: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
From: Neil Franklin <neil@franklin.ch.remove>
Date: 20 May 2001 23:48:53 +0200
Links: << >>  << T >>  << A >>
Ben Franchuk <bfranchuk@jetnet.ab.ca> writes:

> Neil Franklin wrote:
> >
> > Speed is not the problem. TS-10 emulator on its authors PIII-800 runs
> > roughly twice the speed of an KL-10 (the fastest PDP-10 model). Any
> > faster will be detrimental to the experience.
>
> Look if speed is a problem I have a P150. I am sure for a small fee
> I will take your PIII and give you my computer so the emulator
> will run at the right speed.

Ehm, that is the TS-10 authors (Timothy Stark) PIII-800.

I have an AMD K6/2-350. It manages to compile my PDP-10 design in its
present state in less than 1 minute (many thanks to JBits being fast).
BoardScope tends to page a bit heavy while startup because of only 64M
RAM.


> > Not to mention the missing blinkenlights (drawing them in an GUI is
> > not exactly the same thing). Light bulbs (no LEDs those days!) just
> > are different to look at.
>
> You can still get the bulbs!

But not drive them from any emulator I know of. And changing that
would be a _major_ speed killer. Developing an FPGA is more fun.


> > My present simple straight forward FPGA design (one clock per memory
> > or register file access plus a bit of waste) is already with 24MHz at
> > the same speed level as TS-10.
>
> I still think small anti-fuse FPGA's are the way to go,

Try an competing design! We have 3 emulators. So far there are only 2
FPGA projects (my one-hot state machine and Heinz Wolters microcoded,
both using SRAM based FPGAs).

Erm, you say here anti-fuse and in your post just before that you use
Altera and Quicklogic. All Altera I know are SRAM based and Quicklogic
is AFAIK[1] Flash. What chip series are you using?

[1] when I was selecting architecture I failled to find an data sheet
on their web site, only sales presentations. Dito Gatefield. Not to
mention not even getting into Actels site (needs Macromedia Flash
plugin) and Lattices site (wants tons of privacy invading questions
answered). Altera, Atmel, Lucent and Xilinx gave me their data sheets
without problems. From them I selected Xilinx Virtex/Spartan-II.


> as for the BIG computer look - it needs to go into a rack! -.

I have no space to put one of them. Single room 4.5x3.5m and so.


> > A fully pipelined FPGA (think 486 level pipelining) should be over 10
> > times original speed. Assuming that is the aim.
>
> The PDP-10 other than the floating point looks to memory bound rather than
> CPU bound. Pipelining may not help much.

I also suspect caching to be worth more, particularle separate I and D
caches. OTOH writing accumulators may be doable pipelined. Add to
that parallel read and pipelining instruction fetch.


> > Actually an extended-addressing (30bit instead of 18bit) processor,
> > running at 486 speed, with some form of graphical output, could be
> > interesting for someone wanting to use an PDP-10 OS for daily work,
> > just for the insanity of it.
>
> From what little I have seen of the PDP-10 the addressing is
> still only 18 bit segments (256kw).

P-166, KA-10 and KI-10 models were 18bit address. KL-10 was designed
for 30bit but with only somewhere 24..26 implemented. KS-10 was 18,
XKL/Toad-1 implemented the full 30bit.

Presently I am aiming for 18bit, but I am keeping 30bit open as an option.


> mess than intel's 8088. I think PDP-10 flavored cpu could be designed
> with 30+ bit addressing, but the you would have to write you own software!

TOPS-10 7.someversion ran the kernel in 30bit, TOPS-20 was fully 30bit
right into the user level.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 31358
Subject: Spambot Fodder - Dont Bother To Read - Thanks
From: iam@deathsdoor.fsworld.co.uk
Date: 21 May 2001 00:37:35 GMT
Links: << >>  << T >>  << A >>



Article: 31359
Subject: Re: FPGA consultant needed
From: Eric <erv_nospam@sympatico.ca>
Date: Mon, 21 May 2001 00:16:28 -0400
Links: << >>  << T >>  << A >>
Here is the text for this patent :

http://www.delphion.com/details?pn=US05260610__

Problem is, Altera own this "catch-all and innovation stifling" patent
as you call it. What they search in here is someone who will be paid to
pretend this is a real invention. Maybe that's the reason why Altera
themselves could not find an "expert" to defend this patent and had
to go fishing in here.

May I leave the word "grossly" from my previous post ?

Eric.


Rick Filipkiewicz wrote:

> Eric wrote:
> >
> > Am I the only one who think this is grossly inappropriate ?
> >
> > Eric.
>
> I thought the same at first but after reading what appear to be the
> catch-all and innovation stifling nature of the ``patents'' I at least
> partly changed my mind & removed the ``grossly''. Its still
> inappropriate but if the patents are as bad as the abstracts make out
> then who better to shoot them down than readers of this NG ?
>
> Of course the patents may be being presented in the worst possible
> light, I'll check up. If so then normal service vis-a-vis all things
> lawyer will be resumed.


Article: 31360
Subject: Re: FPGA consultant needed
From: Eric <erv_nospam@sympatico.ca>
Date: Mon, 21 May 2001 00:37:54 -0400
Links: << >>  << T >>  << A >>
Well, as long as you don't work for that company they call "XilinK",
go ahead with this lawyer joke ...

Eric.

--------------------------------------------------

Eric Crabill wrote:

> No.
>
> I am, however, available for such consulting.  Where do I sign up?
>
> Eric
>
> Some other Eric wrote:
> >
> > Am I the only one who think this is grossly inappropriate ?
> >
> > Eric.


Article: 31361
Subject: Need A little prog?
From: "Frederic Darre" <darre@irit.fr>
Date: Mon, 21 May 2001 10:20:23 +0200
Links: << >>  << T >>  << A >>
Hello everybody

I have a virtexE and i want to found a programme (java,vhdl,jbits ...) which
i can communicate with the serial port of my pc.

Thanks for any help
(Excuse my english i am a poor french student)



Article: 31362
Subject: Re: Need A little prog?
From: "frederik" <ffrederiksen@hotmail.com>
Date: Mon, 21 May 2001 11:14:11 +0200
Links: << >>  << T >>  << A >>
Why not use the HyperTerminal program that comes with Windows?





Article: 31363
Subject: Xilinx tools
From: "Vivian" <vivian.bessler@ucd.ie>
Date: Mon, 21 May 2001 10:52:59 +0100
Links: << >>  << T >>  << A >>
Hi,
What are the differences between Alliance, Foundation and Foundation-ISE ?
Are they all available for pc,solaris and hp?

Thanks,
Viv



Article: 31364
Subject: Re: Need A little prog?
From: "Frederic Darre" <darre@irit.fr>
Date: Mon, 21 May 2001 11:54:10 +0200
Links: << >>  << T >>  << A >>
To communicate with the FPGA, i have a program coded in java, but i want to
write a program inside the FPGA for communication.

"frederik" <ffrederiksen@hotmail.com> a écrit dans le message news:
9eam01$laa$1@news.net.uni-c.dk...
> Why not use the HyperTerminal program that comes with Windows?
>
>
>
>



Article: 31365
Subject: Interfacing with serial port
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 21 May 2001 12:08:38 +0200
Links: << >>  << T >>  << A >>
this should help you, otherwise you should find plenty of 
reference if you look over the net

http://www.beyondlogic.org/serial/serial1.htm
http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1999_w/RS232/

try something like +RS232 +vhdl +fpga in your search engine



Steven

Article: 31366
Subject: Re: Xilinx Coolrunner 100% routable - but the tools aren't
From: Alan Glynne Jones <alan.glynne-jones@philips.com>
Date: Mon, 21 May 2001 11:19:24 +0100
Links: << >>  << T >>  << A >>
Thanks for the advise on this matter.  using a value of 10 for both
Pterm limit and Input limit got it to work.
I'll know what to do in future now.

Thanks

Alan

Alan Glynne Jones wrote:
> 
> Thankyou for taking an interest in my problem.
> 
> I have now developed my design further - and it seems to fit with the
> full 'memory' array using the default process options.
> 
> I still have my code which would not fit, so I've tried those
> suggestions on it - I set the Pterm limit to 16, Input limit to 16 and
> block input limit to 38, the design still wouldn't fit.
> 
> I have recieved an email from Jennifer Jenkins, an Applications Engineer
> at Xilinx, who I have now sent my code to look at.  I also copied it to
> you Mark.
> 
> Alan
> 
> Mark Ng wrote:
> >
> > Hello Alan,
> >
> > Since I do not have your design file, I cannot tell you exactly why your design
> > is not fitting.
> > But, by looking at the fitter report you attached, it seems as though you are
> > using a decent amount of P-terms and registers.  I would guess that your design
> > is not fitting because of fan-in limitations.  A certain node/equation probably
> > requires a bunch of P-terms.  However, we can tweak this --
> >
> > By default , the WebPack software does not allow the user to utilize all
> > available resources.  This gives the designer some fan-in to spare, should he
> > need it later.  i.e.  It allows the designer to add more logic late in the game
> > without going having to go to a higher density part.
> >
> > With that said, I would suggest that you try changing your design implementation
> > options to:
> >
> >     Collapsing Pterm Limit = 16    (default 28)
> >     Collapsing Input Limit  = 16     (default 32)
> >     Block Input Limit         = 38    (default 36)
> >
> > (Just in case, you can acces these options by right clicking on Implmentation,
> > then left clicking on Properties.  Then go to the Optimization tab.)
> >
> > Try those options, and let me know how they work.  If it still doesn't work, I
> > would be happy to look into it further.
> >
> > Regards,
> >
> > Mark
> >
> > Alan Glynne Jones wrote:
> >
> > > I'm using the XCR3256XL from the Coolrunner XPLA3 family.  One of the
> > > features of this family is that it should be 100% routable.  I'm using
> > > WebPack Project Navigator with the WebPack XPLA fitter to implement my
> > > design.  In order to test parts of my design I have defined an array of
> > > 8, 8 bit wide standard logic vectors to act as memory locations.  When I
> > > try to implement this design I get the messages below.
> > >
> > > Parsing...
> > >
> > > Parsing file test_epp_int.blx ...
> > >
> > > Synthesizing and Optimizing...
> > >
> > > Fitting...
> > > > WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> > > > WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> > > > WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> > > > Cannot preassign signals.
> > > > ERROR 4060 Cannot fit the design into the chip. You may want to try
> > >        a larger device or split the design into sub-designs.
> > >
> > > %% ERROR count: 1  WARNING count: 3
> > >
> > > By setting the Use Design Location Constraints option to "try" the
> > > implementation process will complete successfully but is unable to
> > > assign the above signals to the required pins, it generates the resource
> > > summery below.
> > >
> > > $DEVICES        XCR3256XL-10TQ144       fit (9 sec)
> > >
> > > ---------------------------------------------------
> > > |          Total Device Resource Summary          |
> > > ---------------------------------------------------
> > > | RESOURCE     AVAIL.     USED     UTILIZATION    |
> > > ---------------------------------------------------
> > > | Clock Inputs     4         1        25.00%      |
> > > | Global C-Terms   4         3        75.00%      |
> > > | Func Blocks     16        10        62.50%      |
> > > | I/O Pins       116        29        25.00%      |
> > > | Macro Cells    256       139        54.30%      |
> > > | PLA P-Terms    768       322        41.93%      |
> > > | PLA S-Terms    256       137        53.52%      |
> > > | Block C-Terms  128        14        10.94%      |
> > > | Fbk Nands        0         0         0.00%      |
> > > ---------------------------------------------------
> > >
> > > If I halve the size of my 'memory' array it passes through the
> > > implementation process successfully, I assume this means that the fitter
> > > tool is unable to utilise the 100% routable feature of the taget.
> > >
> > > My question is, can I get around this?  I have tried fiddling with the
> > > process options for systhesis and implementation but have had no luck.
> > >
> > > Alan

Article: 31367
Subject: <no subject>
From: floreq10@hotmail.com ("elvira catherina")
Date: Mon, 21 May 2001 12:03:36 +0000 (UTC)
Links: << >>  << T >>  << A >>
hello,

till now i am using a schematic entry.
whenver i design a state machine with  a non consecutives output values(if 
we can say this, i mean not a simple counter, say [8,5,3,10,15,2]).

To implement this state machine, i use my digital desigin notes, and it's 
working fine. but i wonder can a VHDl code performs the same task optimally 
by just using if else constructors.

Moreover, sometimes i want at a certain cycle the state machine to be in a 
certain state , how could i program automatically this in VHDL

thanks

_________________________________________________________________________
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Article: 31368
Subject: JTAG and Debugging
From: "C.Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Mon, 21 May 2001 14:20:00 +0200
Links: << >>  << T >>  << A >>
Hi,
AFAIK the JTAG Interface could be used to read the actual status
(low or high) of any I/O Pin of the ALTERA FPGA and even to apply
different signals to these Pins.
Could this JTAG Interface be used to get somewhat of a PC-software
scope function of one or more pins?
I'm afraid this could be a timing problem, but it should be possible
for 'quasistatic' signals, shouldn't it?
Unfortunately I never found any software for the PC to do this
job. I hoped, that perhaps ALTERA itself would offer an option
to use the Byteblaster for this, but they seem to support only
programming by JTAG.
Any information regarding the debug capabilities of JTAG and
especially software would be appreciated,
Carlhermann Schlehaus



Article: 31369
Subject: Re: Interfacing with serial port
From: "Frederic Darre" <darre@irit.fr>
Date: Mon, 21 May 2001 14:25:54 +0200
Links: << >>  << T >>  << A >>
Thanks i don't know if this mail is for me but he can help me.

Fred

"Steven Derrien" <sderrien@irisa.fr> a écrit dans le message news:
3B08E926.DE5BE9C6@irisa.fr...
> this should help you, otherwise you should find plenty of
> reference if you look over the net
>
> http://www.beyondlogic.org/serial/serial1.htm
> http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1999_w/RS232/
>
> try something like +RS232 +vhdl +fpga in your search engine
>
>
>
> Steven



Article: 31370
Subject: Re: free simulator
From: Ray Andraka <ray@andraka.com>
Date: Mon, 21 May 2001 12:25:58 GMT
Links: << >>  << T >>  << A >>
plus it comes with a fisrt class HDL editor, tutorials and probably the best
on-line help in the industry.  If you are learning VHDL, Aldec would be THE tool
to get.

Tom Dillon wrote:
> 
> It's not free but Aldec's Active HDL is much cheaper than Modeltech and
> does an excellent job.
> 
> Regards,
> 
> Tom Dillon
> Dillon Engineering, Inc.
> http://www.dilloneng.com
> 
> >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
> 
> On 5/14/2001, 4:59:49 AM, "Meelis Kuris" <matiku@hot.ee> wrote regarding
> free simulator:
> 
> > Hi!
> 
> > I've been using Modeltech XE which comes with WebPack
> > and I'm getting really tired of this design size limitation and
> > it's generally quite slow and the DCM phase shift problem I wrote about,
> > etc.
> 
> > So, what other free/shareware simulator can I use for simulation
> > where I can also use Virtex2 specific things like DCM?
> 
> > Can I use Veribest simulator coming with Actel Desktop
> > software? Is it possible to use unisim library with it?
> > How? Tried linking the same unisim library which was meant
> > for Modelsim, no success.
> 
> > Or any other suggestions?
> 
> > Thanks,
> 
> > Meelis

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 31371
Subject: Re: Interfacing with serial port
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 21 May 2001 14:56:14 +0200
Links: << >>  << T >>  << A >>
indeed it was, i just forgot tu use my reply button ...

Frederic Darre wrote:
> 
> Thanks i don't know if this mail is for me but he can help me.
> 
> Fred
> 
> "Steven Derrien" <sderrien@irisa.fr> a écrit dans le message news:
> 3B08E926.DE5BE9C6@irisa.fr...
> > this should help you, otherwise you should find plenty of
> > reference if you look over the net
> >
> > http://www.beyondlogic.org/serial/serial1.htm
> > http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1999_w/RS232/
> >
> > try something like +RS232 +vhdl +fpga in your search engine
> >
> >
> >
> > Steven

Article: 31372
Subject: Re: Need A little prog?
From: "Victor Schutte" <victors@mweb.co.za>
Date: Mon, 21 May 2001 15:03:59 +0200
Links: << >>  << T >>  << A >>
Sounds like you need a UART.  Go and have  a look at:  www.opencores.org

It will help a lot if you tell us what you want to do.  You might get away
using a small, inexpensive PIC microcontroller instead.  Once you
'communicate' with your VirtexE (with the UART) you will need some form of
intelligence in the form of a soft core CPU, or a hard core (e.g. 8051)CPU
to do something with the data and or communicate back. If a UART is all you
require you only need a very cheap off the shelf device like a 8251 USART.

Victor


"Frederic Darre" <darre@irit.fr> wrote in message
news:9eaisr$mn7$1@news.cict.fr...
> Hello everybody
>
> I have a virtexE and i want to found a programme (java,vhdl,jbits ...)
which
> i can communicate with the serial port of my pc.
>
> Thanks for any help
> (Excuse my english i am a poor french student)
>
>



Article: 31373
Subject: Synplicity newsgroup?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 21 May 2001 16:22:45 +0300
Links: << >>  << T >>  << A >>

news:news.synplicity.com is not working by me, any one faced a similar problem?
It is so for the last 3-4 days.

Utku



Article: 31374
Subject: Re: XilinxCoreLib with Renoir
From: "Chandramohan Sateesh" <sateesh@spsda.com.sg>
Date: Mon, 21 May 2001 22:30:56 +0800
Links: << >>  << T >>  << A >>
Hi There,

You can use the HDL Designer Series the latest repackaged Renoir to do this.
The procedure is quite simple with this tool

Thanks

Sateesh
"Jean-Pierre Gehrig" <redbull@netplus.ch> wrote in message
news:3b02860d@news.vsnet.ch...
> I'm trying to use a dual port RAM generated by the Xilinx Core Generator
for
> a Spartan-II.
>
> Does anybody knows how to create a component from the VHO file with Renoir
> (I use Leonardo for synthesis)?
>
> Thanks,
>
> Jean-Pierre Gehrig
> Design Engineer
> HEVs Switzerland
>
>





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