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no i don't want to made a business and i have no xbox yet but as I am interested by FPGA developping a such device could be interesting for educative purpose <DerekSimmons@FrontierNet.net> a écrit dans le message de news: 1112454809.520025.125230@z14g2000cwz.googlegroups.com... > The little bit I have read about these is that the more complex ones > have two parts. The first part allows the user to interrupt the normal > booting process and choose a boot device may it be a another boot PROM, > flash memory card, or hard drive. The second part is alternative boot > PROM. They probably hacked the one on the mother and using a BIOS chip > from a motherboard with a similar chip set coded their own. Since the > XBox is based on a PC platform, compared to Game Cube and Play Station > 2 it probably would be easier to create a mod for the XBox but there is > always all that nasty encryption surrounding the DVD-ROM drive. > > Unless you trying to start a business I would imagine it would be > cheaper to buy one and possibly modify the mod kit. > > Derek >Article: 81876
The latest Microblaze version has an optional single-precision hardware Floating Point Unit (FPU): http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf Herb T wrote: > > Folks, > I'm looking at a design problem that may need a floating point unit > (single precision is fine). Part of the unknown at this point is that > it would be running with the Microblaze embedded soft core on a Spartan > 3S400. Do you have any recommendations for an FPU? Does such a > configuration leave room (system gates, on-chip resources, etc) for > anything else in terms of running a DSP type calculations (e.g. > adaptive filters) and device control? I've seen the core provided by > Quixilica, but would prefer to go to something free or open source due > to the fact that I may find out it's not the solution, esp for the > prototying phase. > Thanks, > -HTArticle: 81877
The "Create and Import Peripheral Wizard" (chapter 4: http://www.xilinx.com/ise/embedded/est_rm.pdf) is a good starting point. Use the skeleton files created as a starting point for your own custom core. Paul milind.parelkar@gmail.com wrote: > > How do you connect custom IP cores to Microblaze using IPIF? Should all > interface signals for the IPIF be on the top level entity of the custom > IP Core? What if all the signals are not required and some of these > signals are left unconnected? > > Please help. > > MilindArticle: 81878
The "Create and Import Peripheral Wizard" (chapter 4: http://www.xilinx.com/ise/embedded/est_rm.pdf) is a good starting point. Use the skeleton files created as a basis for your own custom core. Paul "beeraka@gmail.com" wrote: > > Hi everyone , > Can any one in brief tell me how to design a Master - > Slave IP Core on the OPB - Bus ..I just need a design which could read > from and write to any address that I specify ... I know how to design a > slave and I was successful in it but I am not able to understand how > the interaction between and Master and Slave should be because I know > that we cannot design a master alone .. I m using EDK 6.3 and > the ML 310 Board which has a XC2VP30 on it .. > > -- > Parag BeerakaArticle: 81879
Hi Milind, folllow the following steps: 1. create a template for a peripheral using the "create import peripheral wizard". 2. edit the user_logic.vhd file as requested for your application As to IPIF signals - I suggest you to leave these signals as they are If you do not use them as inputs they will be optimized out by the synthesizer and if you do not use some of IPIF outputs conenct them to '0' (e.g. - Retry etc.). Add ports to your user_logic.vhd(inputs/outputs) if needed for your functionality and do not forget to add these same signals on the peripheral top module (your_peripheral_name.vhd) and also add them to your component instantiation in the same file. synrthesize and simulate your peripheral and afterwards import it to your project using the "create import peripheral wizard". check out the following link - http://groups-beta.google.com/group/comp.arch.fpga/browse_frm/thread/b765dbc99599fd76/870b119af0fc6036?q=peripheral+%2B+moti&rnum=1#870b119af0fc6036 I explained there how to import your peripheral properly. after the import process - connect your peripheran and generate a new address for it. I hope that it helps.. Regards, Moti.Article: 81880
Hi When you open your Base System Builder and use it to add a UART peripheral the GUI contains a button called "DATA SHEET" and it will do the trick. Regards, Moti.Article: 81881
<shankar.vk@gmail.com> wrote in message news:1112358355.997835.104340@z14g2000cwz.googlegroups.com... > int* reg = 0x44400030; > *reg = 0x3; > > The above code is not able to modify the register. Have you previously written the same value to that location ? If so, it's possible that your compiler spots the duplication and doesn't do it a second time (unless you write something else in between). This is because "int" refers to a "variable" and not a memory location, per se. The difference is that writing to a memory location can have a side effect. This is what you want, so you may need to stick a "volatile" qualifier in, to make sure the compiler really does do a write. Richard [in PE12]Article: 81882
has anyone come across a PCI FPGA design using PLX-9656 Controller and Xilinx FPGA. We are using the MPRACE board and needed an application template to start of our own design -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 81883
Hi,
I'm using the XC95108 CPLD and Xilinx ISE 7.1.01i. The problem I am having
is
that outputs are inverted when they aren't supposed to be.
*****************
This is my vhdl file:
----------------------------------------------------------------------------
----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
Port ( In1 : in std_logic;
Out1 : out std_logic);
end test;
architecture Behavioral of test is
begin
Out1 <= In1;
end Behavioral;
*****************
This is my ucf file:
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "In1" LOC = "P24" ;
NET "Out1" LOC = "P54" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
*****************
Now i find if i put a low signal on pin 24 i get a high signal on pin 54 and
vice-versa, even though the post fit simulation shows it working correctly.
What could be wrong??
--
Regards,
Ross Marchant
ETG
Article: 81884While using RLOC (under ISE6.3i) I can assign a single FDC primitive to a specific slice in a CLB but cannot assign both flip-flops in a slice. RLOC parameter is just RxCy.S0 or RxCy.S1 but each slice has two flip-flops and I see no way to use both. Have not found any primitive or attribute to do thi assignment. It is the same when using XORCY and the design endup wasting half of the resources (for this particular segment of the design). So, is there a way to instruct the tool, in the VHDL (XST) source, to use resources in this such detailed way? The second question to follow is: is there a way to instruct the tool (map/router) to use, say, long lines instead of lots of local lines when sourcing several CLB inputs with a single signal? It also seems that there is a kind of check-list for router and when changing the direction/shape of a RLOCed circuit it uses different resources to make the connections. I cannot find a document in Xilinx web site instructing how to better use the tools according the device's architecture, tool's processing schemes and design goals.Article: 81885
"AugustoEinsfeldt": > While using RLOC (under ISE6.3i) I can assign a single FDC primitive to > a specific slice in a CLB but cannot assign both flip-flops in a slice. > RLOC parameter is just RxCy.S0 or RxCy.S1 but each slice has two > flip-flops and I see no way to use both. Have not found any primitive > or attribute to do thi assignment. > It is the same when using XORCY and the design endup wasting half of > the resources (for this particular segment of the design). > > So, is there a way to instruct the tool, in the VHDL (XST) source, to > use resources in this such detailed way? > > The second question to follow is: is there a way to instruct the tool > (map/router) to use, say, long lines instead of lots of local lines > when sourcing several CLB inputs with a single signal? > It also seems that there is a kind of check-list for router and when > changing the direction/shape of a RLOCed circuit it uses different > resources to make the connections. > I cannot find a document in Xilinx web site instructing how to better > use the tools according the device's architecture, tool's processing > schemes and design goals. Maybe this isn't a really answering any of your qestions, but maybe you'll be interested in xdl. If you're using windows, there'll be an html-file describing xdl in /xilinx/help/ instead of /xilinx/doc/ Gruss Jan BrunsArticle: 81886
Jan, thanks for this hint. XDL is a powerfull way to get the details I want, indeed. I will study it and shall build some simple tool to automate part of the work. Anyway, I will keep the hope to accomplish something in my first post using statements included in VHDL source files. It would make easier maintenance and debugging. -AugustoArticle: 81887
AugustoEinsfeldt wrote: > While using RLOC (under ISE6.3i) I can assign a single FDC primitive to > a specific slice in a CLB but cannot assign both flip-flops in a slice. > RLOC parameter is just RxCy.S0 or RxCy.S1 but each slice has two > flip-flops and I see no way to use both. Have not found any primitive > or attribute to do thi assignment. > It is the same when using XORCY and the design endup wasting half of > the resources (for this particular segment of the design). > > So, is there a way to instruct the tool, in the VHDL (XST) source, to > use resources in this such detailed way? > > The second question to follow is: is there a way to instruct the tool > (map/router) to use, say, long lines instead of lots of local lines > when sourcing several CLB inputs with a single signal? > It also seems that there is a kind of check-list for router and when > changing the direction/shape of a RLOCed circuit it uses different > resources to make the connections. > I cannot find a document in Xilinx web site instructing how to better > use the tools according the device's architecture, tool's processing > schemes and design goals. > To constrain two FFs to a slice, all you need to do is assign them both the same RLOC or LOC constraint. BretArticle: 81888
On 3 Apr 2005 17:25:20 -0700, "AugustoEinsfeldt" <aee@terra.com.br> wrote: >While using RLOC (under ISE6.3i) I can assign a single FDC primitive to >a specific slice in a CLB but cannot assign both flip-flops in a slice. >RLOC parameter is just RxCy.S0 or RxCy.S1 but each slice has two >flip-flops and I see no way to use both. Have not found any primitive >or attribute to do thi assignment. >It is the same when using XORCY and the design endup wasting half of >the resources (for this particular segment of the design). You can just use the same RLOC attribute for both FFs or XORCY primitives. If you want to specify a specific LUT, FF, XORCY within the slice, you need to also use the BEL attribute. Read about it here: http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0051_12.html >So, is there a way to instruct the tool, in the VHDL (XST) source, to >use resources in this such detailed way? Attributes can be specified either in the UCF file or in the VHDL/Verilog source. Look in this document: http://toolbox.xilinx.com/docsan/xilinx7/books/docs/xst/xst.pdf on page 222 >The second question to follow is: is there a way to instruct the tool >(map/router) to use, say, long lines instead of lots of local lines >when sourcing several CLB inputs with a single signal? There are direct routing constraint, but they are very hard to use, and require manual routing in the FPGA editor. For most applications, it would be better to use exhaustive timing constraints to specify your design requirements, and let the tools select the resources to acieve the requirements. While I don't agree with the sentiment, Xilinx's attitude is that if the constraints are met, the choice of resources should be irrelevant to the user. Other tools that may interest you other than the FPGA editor, are JBITs tools (no support for most recent products), and XDL (limited documentation, but complete access to the underlying design database. An enthusiastic engineer can derive sufficient understanding by examining XDL files, and do experiments in the FPGA editor, and seeing the resulting XDL. Same thing for directed routing). >It also seems that there is a kind of check-list for router and when >changing the direction/shape of a RLOCed circuit it uses different >resources to make the connections. >I cannot find a document in Xilinx web site instructing how to better >use the tools according the device's architecture, tool's processing >schemes and design goals. I don't believe such documentation exists. After you have used these products for about 16 years, it will start to come to you. Philip Philip Freidin FliptronicsArticle: 81889
Thank you, Philip and Bret for the replys. I am working with Xilinx FPGAs for 9 years but never went the deep and speed I'm doing now. MAP was resulting an error when trying to assign two FFs in a same slice. Found why: I am using different clock sources for FFs and it is only one per slice. Still, I have to solve a signal net distribution that PAR seems to having a hard time to meet the constraints. After using a TBUF to feed the signal in a longline the timming improved but not enough. I could (and will soon) move from current SP2E to a SP3 and let the tools to do the job but it is a good opportunity to learn more about using resources and building something very close to the device's architecture. My first attempt this way was around 5 years ago writing a tool to automate a dinamic reconfiguration process (before JBITs) in a XCV50 device. Pure research lost the fight against design jobs (the money, in the end) and I left the deeper FPGA for another moment. XDL is very promissing and shall work a bit on it. Thank you for your supporting. -Augusto AEE Engenharia Eletronica - BrazilArticle: 81890
I'd done this work with altera's fpga(ep1k50).Article: 81891
Hi anyone out there know where I can get z-dok connectors(tyco part number 1367555-1) for less than $72AUD or $55USD each. Or else, is there anyone who would like to split a pack with me. The minimum quantity is 6 but I only need two. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 81892
In article <425070fd@dnews.tpgi.com.au>, rossm@NOexcelSPAMtech.com.auSTRALIA says... > Hi, > > I'm using the XC95108 CPLD and Xilinx ISE 7.1.01i. The problem I am having > is > that outputs are inverted when they aren't supposed to be. > I do not know if it's the same error, but I filed a bug report for a case where 5.2 generated a working Jedec file and 7.1 did not. This error was confirmed as a SW-bug in the Jedec file generator. Try out an older Webpack like 5.2 or 6.3. Best regards KlausArticle: 81893
Hi Piotr,
You'll get considerably better accuracy, or considerably smaller lookup
tables, by using the Sunderland algorithm and/or the sine difference
algorithm.
Best, Syms.
"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message
news:d2m8k7$7ou$1@news.dialog.net.pl...
> Hello,
>
> my experiment has shown that high-quality sine wave can be
> easily generated using linear interpolation. A simple look-up
> table and a small multiplier is necessary, however I use two
> LUTs instead of one, because this reduces complexity of the
> circuit. But for a specialized IC the one LUT-based approach
> should be considerably cheaper. The idea is as follows: the
> first LUT contains 256 unsigned 18-bit sine values in the
> interval of [0,pi/2), sampled uniformly. The second LUT
> contains differences between consecutive samples (as
> I said above, this can be computed on-line, but is not well-suited
> for an FPGA chip because of long latency compensation paths,
> i.e. many wasted LEs). This ROM has only 11 bits, because
> max{(sin(2*pi*(k+1)/256) - sin(2*pi*k/256))*2^18} is just 1609.
> An 18-bits wide phase word is composed of three parts:
> quadrant_indicator (the upper 2 bits), lut_index (the next 8 bits)
> and phase_residue (remaining 8 bits). This provides:
>
> my_sin(x) = sign * lut_val[lut_index] + lut_dif[lut_index] *
> phase_residue;
>
> Of course sign, lut_index and phase_residue depend on
> currently selected quadrant, but this just a trivial remark.
>
> This simple scheme provides sine wave with 17 bits of accuracy,
> which can be used directly to feed a quadrature mixer. Another
> important property is that the interpolation error near pi/2 is
> negative (i.e. forall x . |my_sin(x)| < 1), so there is no need for
> guard bits. I have some ideas how to further increase accuracy,
> but I am not sure whether I should start developing them, because
> 17 bits are far better than any modern digital RF front-end expects.
>
> I have implemented a complete quadrature mixer (not just an NCO)
> on a multiplierless Cyclone 1C6 and it occupies only 815 LEs, where
> the majority of them is consumed by a 17x16 shared multiplier. Its
> top performance is limited by M4K RAMs and for -6, -7 and -8 speed
> grades this is, respectively, 255.9 MHz, 226.3 MHz and 197.0 MHz.
>
> So, this low cost and low complexity method needs 256 times
> smaller number of ROM cells than classical ROM-based designs
> and much less LEs than CORDIC-based approaches. Moreover,
> this is achieved without signal quality nor performance degradation.
>
> Best regards
> Piotr Wyderski
>
Article: 81894Hello, i'm from germany and just registered to this forum. Hello to everybody out there. I'm working on very small FPGA Designs which are size-comparable (about 4-40 Look-up-Tables on a VIRTEX FPGA) to 4 Bit-adders and 4 Bit-multipliers. I use them just for testing some things. The problem is that I use XPower to calculate the power consumption of the designs and the power values are not what i expected. I have a testbench, an input stimuli and the placed and routed design. Whenever i put stimulis to the design it delivers (like expected) the "mW" values. But if i change the stimuli to other ones, which are nearly the same, the power consumption raises to the double or stays the same. (after subtracting the quiescent part). There's (in most cases) nothing between them. Does anybody know this problem? Have I reached the smallest possible XPower value, or what is it? Oh, and does anybody know, how accurate XPower should be. Is there a chance to get some information about it? Thanks for all answers, parityArticle: 81895
thanks for your answers. after some research I eventually found out, that using both IEEE.STD_LOGIC_ARITH.ALL and IEEE.numeric_std.all was causing my problem.Article: 81896
Ross Marchant wrote: > Hi, > > I'm using the XC95108 CPLD and Xilinx ISE 7.1.01i. The problem I am having > is > that outputs are inverted when they aren't supposed to be. > > ***************** > > This is my vhdl file: > ---------------------------------------------------------------------------- > ---- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity test is > Port ( In1 : in std_logic; > Out1 : out std_logic); > end test; > > architecture Behavioral of test is > > begin > Out1 <= In1; > end Behavioral; > > ***************** > > This is my ucf file: > #PACE: Start of Constraints generated by PACE > > #PACE: Start of PACE I/O Pin Assignments > NET "In1" LOC = "P24" ; > NET "Out1" LOC = "P54" ; > > #PACE: Start of PACE Area Constraints > > #PACE: Start of PACE Prohibit Constraints > > #PACE: End of Constraints generated by PACE > > ***************** > > Now i find if i put a low signal on pin 24 i get a high signal on pin 54 and > vice-versa, even though the post fit simulation shows it working correctly. > What could be wrong?? > Try again removing your lib declaration --use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; regards, Laurent www.amontec.com ------------ And now a word from our sponsor ------------------ Do your users want the best web-email gateway? Don't let your customers drift off to free webmail services install your own web gateway! -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 81897
On Fri, 1 Apr 2005 11:03:22 -0800, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >But how do you calculate, or otherwise detect the concavities? >I have done some initial work with small areas and bit patterns >but one soon runs out of logic gates. Most of the traditional binary image manipulation algorithms use various types of linked memory structures for flexibility. These don't work at all well in FPGA. When faced with the limited memory and non-existent memory allocation opportunities in an FPGA, you'll need special algorithms that are sure to be application specific. The key questions, it seems to me, are... 1) How is the image presented to you? Do you get it pixel-by- pixel from a camera of some kind, or are you given ready- processed data structures from a CPU that writes to your FPGA? 2) How big is the largest object that you need to process? For the most interesting image processing operations, you need to be able to store a complete bitmap of the whole object, which in practice means storing every pixel in a rectangle at least big enough to hold the object. 3) Do you need to process multiple objects simultaneously? I ask this because, the last time I did any binary vision stuff, we were capturing images of codfish on a conveyor belt. The belt went under a line-scan camera, and it was wide enough that there could be several fish in view at any one time. Our software needed to process all of them, else you got an awful lot of waste fish on the floor :-) 4) Are you interested in any included holes in the object, or only its outline? If you care only about the outline, then the extent of the image on each scan line can be represented by only two numbers - the left and right boundaries of the object on that line. Given the kind of data representation I outlined in (4), there's a relatively simple algorithm for extracting the convex hull. It requires only two additional bits of storage associated with each scan line, in addition to the left and right boundary information. However, it is not totally FPGA-friendly because at each scan line you have to look back over all previous scan lines on the object. You may find it's best to include a little CPU in the design, to help with the sequencing of this or similar algorithms. I wonder... does your application REALLY need all the concavity information? It may be possible to get all the information you need from simple accumulated measurements such as the centre-of-gravity, area, and first and second moments of inertia of the object. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 81898
Hello Guys, I had a doubt about the IBUFG and BUFG in xilinx. 1.I have connected clock from oscillator to CLKG IO of the Xilinx. In this case is it required to instantiate the IBUFG inside my code also?. 2. The DCM output is already BUFG i think and so is it required to BUFG again in my code? Thanks and regards WilliamsArticle: 81899
Symon wrote:
> You'll get considerably better accuracy, or considerably smaller lookup
> tables, by using the Sunderland algorithm and/or the sine difference
> algorithm.
Thanks, I didn't know about them. The "sin(2*pi*x) - x" trick is
particularly nice, I'll think about incorporating it into my quadrature
mixer to increase accuracy beyond 17 bits (just to check the idea,
there's no technical reason to do so). However, compared to
http://www.ecdl.hut.fi/~jvan/dds3_files/mapiee.pdf
it seems that my algorithm (which is very simple, so I doubt that
I am the first inventor of it) is much better, because it needs
only 2^8 16-bit ROM cells to produce 17-bit approximation of
sin(x), where those algorithms need 2^8 9-bit cells to produce
~12 bits of accuracy. :-)
Best regards
Piotr Wyderski
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