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Hi, Here is my problem. My memory map is as follows: ISBRAM : 0xFFFFE000:0xFFFFFFFF SDRAM : = 0xF0000000:0xF1FFFFFF I download bootloop program with the bitstream. The program I want to execute is linked at 0xF0400000. Then I open XMD and write following commands: connect ppc hw -debugdevice cpunr 1 dow sw_projects/dpmain/executable.elf run This works fine the program starts to run, BUT I always get a machine check error at the start of the program. The PLB_Error is caused when I run dow sw_projects/dpmain/executable.elf, because for whatever reason the processor at this moment tries to read address 0xFFFFFFFC on the PLB bus. Any ideas, why this is and how it could be removed? Thanks, eArticle: 117876
On Apr 11, 12:10 pm, "zcsizma...@gmail.com" <zcsizma...@gmail.com> wrote: > On Apr 10, 11:51 pm, "H. Peter Anvin" <h...@zytor.com> wrote: > > > > > zcsizma...@gmail.com wrote: > > > > How big is your form factor? I think it is still easier to make a > > > motherboard for the Virtex-4 Mini module, and add a 5V TTL logic > > > converter and the power supplies vs. designing a new board. > > > I wouldn't worry about power supplies. That should be your smallest > > > problem. > > > > Other option is to put a small Spartan II and a uC (with external data > > > bus support, e.g. Atmega), and use the dual-port ram inside Spartan to > > > share memory between uC and Spartan. > > > The form factor is quite big -- 100x160 mm (Eurocard), so space is > > largely plentiful. The Virtex-4 mini module is quite expensive, though > > ($250), which is okay for a one-off but may be too much for an actual > > production run -- I would have to do the math on that. > > > I didn't realize that Spartan II was 5 V tolerant. I'm going to have to > > see if that is practical to combine with a microcontroller. Still needs > > dual power supplies, though If not, a 200,000-gate Spartan II > > apparently retails for $26 these days; that FPGA should be large enough > > to fit an 8- or 16-bit microcontroller core plus all the logic. > > > Anyone has any kind of idea how long Spartan II is likely to remain on > > the market? > > > -hpa > > IIRC you can put a simple microblaze (32 bits) design into the Spartan- > II, IF you don't need too much code space. But picoblaze (8 bit) can > be done as well. > Probably that would be the easiest solution, have a block ram in your > FPGA logic, and map that RAM into uBlaze. A suggestion if you decide to go 8-bit with PicoBlaze. Nial Stewart has adapted the Picoblaze 2 (Virtex-2 version) for Spartan 2. This overcomes the extremely small (256 instruction) code space of the original PicoBlaze for Spartan 2. I have used this in the Spartan 2 200K gate part and it leaves most of the logic free for your other needs. HTH, Gabor PS here's the header from the Nial's perl script for converting instruction RAM from Virtex 2 to Spartan format: # This is a Perl utility written to convert initialisation # definitions from Virtex Blockram (1024 x 18 bits) to SpartanII # Blockram (5 * 256 x 4 bits) format. # # This is to allow the bigger version of the Picoblaze processor # to be used with SpartanII devices. # # This is provided as is for general use without any guarantees or # warranties. # # =A9 Nial Stewart Developments 2003 # www.nialstewartdevelopments.co.ukArticle: 117877
For CORDIC algorithms check out Ray's website at http://www.andraka.com/cordic.htm - Subroto Datta "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1176348826.558748.152160@w1g2000hsg.googlegroups.com... > Hi, > I want to buy two books on CORDIC. One is focused on CORDIC theory and > algorithms, another on CORDIC applications. > > Which is the best book about CORDIC algorithms? > > Which is the best book about CORDIC applications? > > Thank you. > > Weng >Article: 117878
On Apr 12, 7:07 am, "Subroto Datta" <sda...@altera.com> wrote: > For CORDIC algorithms check out Ray's website athttp://www.andraka.com/cordic.htm > > - Subroto Datta > > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > news:1176348826.558748.152160@w1g2000hsg.googlegroups.com... > > > > > Hi, > > I want to buy two books on CORDIC. One is focused on CORDIC theory and > > algorithms, another on CORDIC applications. > > > Which is the best book about CORDIC algorithms? > > > Which is the best book about CORDIC applications? > > > Thank you. > > > Weng- Hide quoted text - > > - Show quoted text - Hi Subroto, Thank you for your pointing to Ray Andraka website. I have read his paper, a very nice paper. I will print all references in his paper too. But I am afraid that the paper was published in 1998, almost 9 years ago and there must have been new progresses on this topics. By searching Google using keyword: CORDIC, I found more than 300 books on the topics so that I need experts on this regard to point to the best books on the field. WengArticle: 117879
On Apr 11, 10:11 pm, kanthi.sidd...@gmail.com wrote: > iam doing projevt on Digital down converter.In that i need to multiply > RF signal and LO signal . which type of multiplier is suited for > multiplication of two sinusoidal signal using FPGA.if any body is > having code iwould be thankful to you When I first read about mixers, I thought that it was some special operation to have such interesting results. It was only later that I realized they were talking about the multiplication I learned in the third grade. (So *that's* why the symbol for a mixer is a big X!) Alan Nishioka PS. I only answered this so there would be two messages from people with the same first name.Article: 117880
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1176392513.597727.256450@d57g2000hsg.googlegroups.com...
> Thank you for your pointing to Ray Andraka website.
> I have read his paper, a very nice paper. I will print all references
> in his paper too. But I am afraid that the paper was published 1998,
> almost 9 years ago and there must have been new progresses on this
> topics.
Not necessarily. All the books on my reference shelf I refer to most often
are >10 years old. :-)
CORDIC was a great way to do many DSP functions before FPGAs with dedicated
fast low-power multipliers came along. Nowadays, a lot of its advantages are
waning. However, it's still a fascinating and elegant idea and worthy of
study (certainly I keep meaning to learn more about it!).
I'd definitely start by absorbing all that Ray has to say on the subject,
then go from there.
-Ben-
Article: 117881Dear all, I'm doing research on FPGA's LUT input size. And i'm using synplify pro to synthesize vhdl/verilog to edf for virtex2 device. Do you know how to limit the LUT input size to 1, 2,3 in synplify pro? And even, could I use 5,6,7,8 .... -input LUT in synplify pro (also using virtex2 device). Many thanks for your help ! Regards, YuArticle: 117882
I am trying to work through the "EDK 8.2 MicroBlaze Tutorial in Spartin 3" When I get to the point of "Generate Programming File" to implement the design on page 26, It appears that ISE does not call XPS to generate the EDK to create the directories "hdl, implemtation, & synthesis". I get the following error message; ERROR:HDLParsers:3264 - Can't read file "E:/users/sgwillis/Engineering/xilinx/designs/ edk82_mb_spart3/project_navigator/../hdl/system.vhd": No such file or directory. I am using the ISE 8.2.03i web pack with the EDK 8.2.02i. EDK 8.2i and SP2 was installed after ISE 8.2i and SP3 on a Windows XP Pro computer with SP2 and multiple patches. Any ideas/hints would be greatly appreciated. Thanks. V/R ScottArticle: 117883
On Apr 12, 4:38 am, easchei...@yahoo.com wrote: > My memory map is as follows: > > ISBRAM : 0xFFFFE000:0xFFFFFFFF > SDRAM : = 0xF0000000:0xF1FFFFFF > > This works fine the program starts to run, BUT > I always get a machine check error at the start > of the program. The PLB_Error is caused when I run > dow sw_projects/dpmain/executable.elf, because > for whatever reason the processor at this moment tries > to read address 0xFFFFFFFC on the PLB bus. > > Any ideas, why this is and how it could be removed? 0xFFFFFFFC is the reset vector, and I thought perhaps there is a problem with mapping this to ISBRAM. (If you are searching for this, you get more results searching for ISOCM.) Other designs have PLB bram at this address and jump to ISBRAM. But the Xilinx Ultracontroller doesn't use PLB bram. Looking at xapp575.pdf, however, it looks like they use some trickery to make this work correctly. It is not clear what they do, but it appears they have hard wired the reset vector to the otherwise unused PLB bus. I would be interested to know if other people have ISBRAM at the top of memory and how it was made to work. I have been thinking about changing my PLB bram to ISBRAM for speed. Alan NishiokaArticle: 117884
<yuchiwai@gmail.com> wrote in message news:1176395220.203418.61680@d57g2000hsg.googlegroups.com... > Dear all, > I'm doing research on FPGA's LUT input size. And i'm using synplify > pro to synthesize vhdl/verilog to edf for virtex2 device. Do you know > how to limit the LUT input size to 1, 2,3 in synplify pro? > > And even, could I use 5,6,7,8 .... -input LUT in synplify pro (also > using virtex2 device). > > Many thanks for your help ! > > Regards, > Yu > Hey Yu, I think you'll need to instantiate the LUTs in your HDL. Does the Synplify manual mention LUT input size? Cheers, Syms.Article: 117885
Ken Soon wrote: >> Start by adding two register levels to your 1920x12 >> distributed memory's output and your score will most likely drop from over >> 5M to possibly under 200k. Add extra registers until your timings are met >> or improvements stall. After this, you will need to realign your >> processing >> pipeline to account for the delays on this large distributed memory. >> > Hmm, so I can add register levels? How do I go about that? > I tried selecting the register duplication both in the synthesis and > implement design options. But to no avail. > So do u mean using FPGA editor? Adding output registers is simple... if rising_edge(clk) then memout_d1 <= memout; memout_d2 <= memout_d1; memout_d3 <= memout_d2; ... end if; You could add a generic port to your memory template to automatically generate these delays to keep your upper-level HDL clean. > Talking about FPGA editor, I was wondering about moving the problematic > source CLBs closer to the destination so as to cut down the delay? But there > are quite a few implications due to the other wires connection to those > CLBs. 1920/16 = 120 LUT-Ms to mux each bit, this means 7 2:1 mux layers. LUTs can do 2:1, slices do 2:1 and CLBs do 2:1 so you need to go through two full CLBs and one LUT to do this 120:1 mux. I think you will be fine if you add three output registers in the RAM's output path. Due to the high fan-out on the address bits, an extra register there should also help. With all this, you will get data four cycles later after the request. >> BTW, what was your LUT and slice-FF usage with that last attempt? > Ah forgot to save... > Well I did another one with instances of the Vertical sequential table and > the horizontal and vertical cofficients table using distributed ram > (Before this change, I remembered the block ram usage was 33 out of 36 for > linebuffer instance using distributed ram and th 4 input LUTs was 84%) > Number of Slices: 6718 out of 14752 45% > Number of Slice Flip Flops: 9007 out of 29504 30% > Number of 4 input LUTs: 13229 out of 29504 44% > Number used as logic: 7010 > Number used as Shift registers: 459 > Number used as RAMs: 5760 > Number of IOs: 322 > Number of bonded IOBs: 316 out of 376 84% > Number of BRAMs: 36 out of 36 100% > Number of MULT18X18SIOs: 36 out of 36 100% > Number of GCLKs: 1 out of 24 4% > > I figured this is vertical sequential table would be the better choice to > tackle the problem after forcing it to use distributed ram. After you implement the extra registers for the distributed RAMs, your FF usage should increase by about 2000. With resources currently under 50%, it should considerably improve your PAR results without any other fancy footwork. If parts of your design are mostly self-contained, you could floorplan them to reduce the amount of time PAR will spend making guesses about the optimal layout.Article: 117886
On Apr 11, 6:32 pm, "johnp" <johnp3+nos...@probo.com> wrote: > In theory, XST claims to support the Verilog $readmemh to initialize > memory. I'm > using the latest 9.x s/w verion. > > I look at the .syr output file from XST, and it claims to have read > the file. But... > > If I hook a logic analyzer up to the output of the memory, it looks > like it never got > initialized. > > Another problem I'm seeing is that XST appears to not like having an > address line > (@000) in the file. Also, if the the file is too short, XST complains > and discards > the initialization. > > I'll dig into this some more, but I was wondering if anyone had had > any success with this. > > Thanks! > > John Providenza Here's some more info... In the .syr report file from XST, I see the lines: INFO:Xst:2546 - "C:/usr/JOHNP/mentor/enet/hw/pblaze_rtl/../rtl/ pblaze.v" line 84: reading initialization file "../sim/foo.memh". but later... WARNING:Xst:1781 - Signal <dp_mem> is used but never assigned. Tied to default value. This explains why I get 0's from the memory - it's been optimised out and tied to 0. Any ideas for simple work-arounds? I've opened a WebCase, but my expectations from them are realistic, ie, very low. John ProvidenzaArticle: 117887
On Apr 11, 10:55 pm, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > It isn't clear in your post but I guess you are doing a post place and > route simulation. A typical mistake is to instantiate a post place > and route netlist from a testbench which was never intended to be connected > to such a netlist. An example: > > mynetlist dut(.clk(clk),.signalA(signalA), ... ); > always @(posedge clk) signalA <= someothersignal; > Correct. I'm doing a post-place and route simulation. My testbench only provides clock and reset to the module but there are a number of modules that simulate external components. All the inputs from these componenets are latched first and sampled on the internal clock. Some of them are asynchronously latched though which I suspect maybe part of the problem. I also traced some of the timing violations to two inferred latches that I thought harmless (never again). I was just wondering if the static timing analyzer calculates the timing paths length from a latch output rather than its driving flip-flop output?! Thanks for the suggestions /MHSArticle: 117888
After designing a peripheral and checking that it is working with the BFM simulation, I am trying to simulate the whole system. I created a simple system with BSB in order to get experience with this simulation. I generated the Hdl libraries in XPS and modified the modelsim.ini to use the Smartmodels ( I use Modelsim SE PLUS 6.2a). I also checked it with: VSIM>vsim unisim.ppc405 And it is working ok. XPS creates the directory simulation/behavior with the scripts to simulate the system in Modelsim. The system was compiled using these scripts. I have an error while the system is loaded: # Loading opb_arbiter_v1_02_e.or_gate(imp)#1 # ** Fatal: (vsim-3348) Port size (1) does not match actual size (32) for port '/system/opb/opb/opb_abus_i/y'. # Time: 0 ps Iteration: 0 Instance: /system/opb/opb/opb_abus_i File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/ opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125 # FATAL ERROR while loading design # Error loading design # 1 I do not how to solve this problem as the opb_arbiter_v1_02_e module is a Xilinx IP core, and it is read only. It has to be any solution, because some people are using this kind of simulation and I am trying to use it with a simple design created with BSB( bitstream ok, and the software project is the default TestAppMemory) Can anyone help me, thanks. Note: This is almost all the information of Modelsim # vsim -t ps system_conf # Loading /opt/modeltech/6.2a/linux/libswiftpli.sl # Loading /opt/modeltech/6.2a/linux/../std.standard # Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_1164(body) ... ... ... # Loading /opt/modeltech/6.2a/linux/libsm.sl # ** Note (SmartModel): # Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED # ** Note (SmartModel): # Platform Type: x86_linux (32-bit). # ** Note (SmartModel): # You can use the Browser tool to configure the SmartModel # Library and access information about SmartModels: # $LMC_HOME/bin/sl_browser # # SmartModel product documentation is available here: # $LMC_HOME/doc/smartmodel/manuals/intro.pdf # http://www.synopsys.com/products/lm/doc/smartmodel.html # # Notice: timing checks disabled with +notimingcheck at compile-time # ** Warning (SmartModel): # Model is being requested to run at a finer resolution than necessary. # Time: 0 ps Instance:/system/ppc405_0/ppc405_0/ppc405_i/ ippc405_swift/ppc405_swift_inst # Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/ unisim/.fpga_startup(fpga_startup_v) # Loading work.ppc405_1_wrapper(structure) # ** Warning (SmartModel): # Model is being requested to run at a finer resolution than necessary. # Time: 0 ps Instance:/system/ppc405_1/ppc405_1/ppc405_i/ ippc405_swift/ppc405_swift_inst # Loading work.jtagppc_0_wrapper(structure) # Loading jtagppc_cntlr_v2_00_a.jtagppc_cntlr(structure) ... ... ... # Loading opb_arbiter_v1_02_e.opb_arb_pkg(body) # Loading opb_v20_v1_10_c.opb_v20(imp)#1 # Loading opb_arbiter_v1_02_e.or_gate(imp)#1 # ** Fatal: (vsim-3348) Port size (1) does not match actual size (32) for port '/system/opb/opb/opb_abus_i/y'. # Time: 0 ps Iteration: 0 Instance: /system/opb/opb/opb_abus_i File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/ opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125 # FATAL ERROR while loading design # Error loading design # 1Article: 117889
-jg wrote: > > You need to define just how much the CPLD portion needs to DO. > - ie how many macrocells are needed > How much memory is shared, and what bandwdith is needed ? > > It is quite easy to set up shared memory access on a Microcontroller, > with external RAM and a CPLD - choose a fast SRAM, and lock the > CPLD access to the idle periods in the uC bus - that way, > you emulate dual-port memory with cheap SRAM. > Yes, I've pretty much independently come to the same conclusion. This is most likely the sanest option. The next step is to prototype the CPLD code and see what kind of CPLD it can fit into. The only potential concern with having the CPLD do the arbitration of the SRAM bus is needing too many I/O pins on the CPLD, but I'm sure that can be dealt with, too. -hpaArticle: 117890
Gabor, I have lots of experience with altera and some with xilinx FPGAs. I am pretty good with VHDL. The algorithms I might want to implement: optical flow projective image warp mpeg encode and decode neural network or support vector machine image histogram block matching algorithms (such as those in mpeg). - to name a few. On Apr 11, 5:51 pm, "Gabor" <g...@alacron.com> wrote: > On Apr 11, 1:24 pm, "wallge" <wal...@gmail.com> wrote: > > > Just wondered if anyone here has used these devices... > > I want to do embedded computer vision applications > > and it sounds like they are a pretty good fit. > > But I have no idea about the difficulty of using the tools > > and getting algorithmic concepts into hardware... > > > any feedback would be great. > > We've had some experience with these, but to date most of the work > has been done by "software guys" who have had some trouble getting > the hang of the programming paradigm. I think if your background is > in FPGA and other hardware design you'll have an easier time of it. > > I like to think of the FPOA as an FPGA without the main fabric, only > DSP and memory blocks. This is a bit of simplification since the > ALU's in the FPOA are really little programmed sequencers, but it > gets across the granularity of the part. Don't expect to write some > very high level code that is magically mapped into a quantity of these > blocks as for example your VHDL or Verilog might fit into Slices in > Xilinx FPGA's. In that respect the tools are relatively primitive, > more like FPGA editor than anything else I can think of. > > That being said, if you can partition your algorithm into pieces > that fit the blocks of the array, this part is much easier to > meet timing with than FPGA's. The headaches come in the interconnect > where you are forced to add pipeline delays based on route length. > There is some support in the tools to help deal with this, but again > it isn't as "pushbutton" as we've become accustomed to with FPGA > tools. Other issues arise when your data flow is constrained by > peripherals that require data to enter or exit the part on particular > columns or rows, and by the use of MAC and register file blocks that > are more sparse throught he array than the ALU's. > > The design entry runs under Visual Elite, which has some nice > features and simple built-in simulation. However the top level > of your design is pretty much a schematic calling up the block > elements of the array. If you can give an example of the kind > of algorithms you might do in the part I might be able to let > you know what to expect for "level of pain" to get it into the > FPOA. > > Regards, > GaborArticle: 117891
In the Xilinx Synthesis and Simulation Design Guide there is this phrase: "While Xilinx data sheets report that there are zero hold times on the internal registers and I/O registers with the default delay and using a global clock buffer, it is still possible to receive a $hold violation from the simulator. This $hold violation is really a $setup violation on the register. However, in order to get an accurate representation of the CLB delays, part of the setup time must be modeled as a hold time." Can somebody put some more explanation to this phrase? I understand how the setup/hold window can be shifted back and forth by adding delay to the data path but I dont understand why the need for modeling part of the setup time as hold time, and how to properly fix hold time violations. Thank you. /MHSArticle: 117892
If spartan 3e are really in mass production, why is it, that this kits: DO-SP3E1600E-DK-UNI-G are never available ? Not from xilinx (where the online store is just joke to navigate, sending peaple in circles), nor from avnet, nuhorizon, and digilent. Any insight ?Article: 117893
H. Peter Anvin <hpa@zytor.com> wrote: ... > The only potential concern with having the CPLD do the arbitration of > the SRAM bus is needing too many I/O pins on the CPLD, but I'm sure that > can be dealt with, too. Go with an FPGA. Some more external infrastructure needed, but much more possibilities... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 117894
On Apr 12, 9:24 am, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > news:1176392513.597727.256450@d57g2000hsg.googlegroups.com... > > > Thank you for your pointing to Ray Andraka website. > > I have read his paper, a very nice paper. I will print all references > > in his paper too. But I am afraid that the paper was published 1998, > > almost 9 years ago and there must have been new progresses on this > > topics. > > Not necessarily. All the books on my reference shelf I refer to most often > are >10 years old. :-) > > CORDIC was a great way to do many DSP functions before FPGAs with dedicated > fast low-power multipliers came along. Nowadays, a lot of its advantages are > waning. However, it's still a fascinating and elegant idea and worthy of > study (certainly I keep meaning to learn more about it!). > > I'd definitely start by absorbing all that Ray has to say on the subject, > then go from there. > > -Ben- Hi Ben, I have read Ray paper and went to his website and read "How to calculate sine()". After reading I still have difficulties understanding its process. Can you give an example on how to calculate sine(x), where x = 35 degrees? I don't understand why he could calculate the factor K before starting calculation. Because during calculating, one doesn't know how many iterations should be taken to reach required accuracy. Thank you. WengArticle: 117895
Hi Pete- For DSP applications, this is exactly what the hardware co-simulation engine of System Generator for DSP does. Check out http://www.xilinx.com/ise/optional_prod/system_generator.htm for more details. As Sylvain mentioned, you can build your own "HW co-sim" engine by attaching logic to the BSCAN component and using the CseJTAG Tcl interface to communicate with it using the USB-to-JTAG cable. While it's not trivial, it shouldn't be too much trouble to come up with a simple example to read and write registers in your design via JTAG. For details on attaching logic to the BSCAN interface, refer to http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=krs_blockRAM&iLanguageID=1&iCountryID=1. For details on the CseJtag Tcl interface, check out chapter 5 of http://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_9_1i_ug029.pdf and/or download ChipScope Pro (free for 60-days) and try out the "csejtag_example1.tcl" example that comes with the tool. Cheers, -Brad "Pedro" <pete.dudley@comcast.net> wrote in message news:jJOdnccREoEqDoTbnZ2dnUVZ_h-vnZ2d@comcast.com... > Mike > > I agree with you that an HDL simulator and a few testbenches should always > be the first line of attack. > > My problem comes in when I have to run 100 million clock cycles to verify > a design. This often happens with DSP designs that require a lot of data > through the filters to verify their functionality. Another case is when > the data is a two dimensional array and the operation is something like a > 2D FFT. It's easy to hit cases where its impossible to simulate the whole > thing. Granted its usually possible to cut down a simulation by changing > count limits, etc. > > In any case, I'm hoping that the USB interface might be easy to use though > it could also turn into a project of its own. > > Also, in theory, I could hand over an eval board to software developer and > they could start programming. The USB download cable could stand-in for > the pci interface that will eventually be there. > > Anyway, I just wanted to make it clear the special circumstances where I > would use hardware verification. Definitely, I will always use the > simulator to the maximum extent possible. > > Thanks for the reply. > > Pete > > > > "Mike Treseler" <mike_treseler@comcast.net> wrote in message > news:57t3b5F2ei71lU1@mid.individual.net... >> Pedro wrote: >> >>> I am looking for a more convenient way to use inexpensive eval boards to >>> test logic designs in an fpga. >> >> It is possible to do this without a board or an FPGA. >> >> Maybe I've logged too many hours debugging >> logical problems at a lab bench. but >> the novelty seems to have worn off. >> >> I use modelsim, an RTL viewer and >> static timing to verify FPGA logic designs. >> I expect the design to just work on the bench. >> If it doesn't, I fix the process. >> >> -- Mike Treseler > >Article: 117896
The ISE 9.1iSP3 GUI application `ise' appears to be incompatible with glibc-2.5. But when running it chrooted in a glibc-2.4 environment, it works perfectly (I used a Gentoo 2006.1 stage3 for these experiments, which contains a glibc-2.4 based system, instead of the glibc-2.5 used by current Gentoo systems). I hope that someone else profits from a week of experimentation ;-) Andreas KochArticle: 117897
emu, I went to the Xilinx.com website, did a search on the part number, clicked on the store for NuHorizons, and there is 1 in stock, and ships in 24 hrs. I know that some of the RoHS compliant boards have caught some folks by surprise (did not anticipate the demand). Other than that, I am unaware of any problems. Austin emu wrote: > If spartan 3e are really in mass production, why is it, that this > kits: > DO-SP3E1600E-DK-UNI-G > are never available ? > Not from xilinx (where the online store is just joke to navigate, > sending peaple in circles), > nor from avnet, nuhorizon, and digilent. > > Any insight ? >Article: 117898
Tracing timing violations in the post-p&r generated netlist can be cumbersome with all signal merging/renaming and inserted buffer. I was wondering if there is a way that I can back annotate the post place and route delays back to the RTL code? even approximate delays can reveal some design errors I would think. Thank you.Article: 117899
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1176406855.006693.190500@n76g2000hsh.googlegroups.com... > I have read Ray paper and went to his website and read "How to > calculate sine()". After reading I still have difficulties > understanding its process. > > Can you give an example on how to calculate sine(x), where x = 35 > degrees? > You seen this, right? http://en.wikipedia.org/wiki/Cordic HTH, Syms.
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