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Hi all, I am wondering if there is any way to use my legacy Spartan XL devices with ISE/WebPack as the front end. Is there anything I can do, or would I have to fall back to the old ISE Classic/LeonardoSpectrum routine? Thanks, VadimArticle: 76501
Vadim Vaynerman wrote: > > Hi all, > > I am wondering if there is any way to use my legacy Spartan XL devices with ISE/WebPack as the front end. Is there anything I can do, or would I have to fall back to the old ISE Classic/LeonardoSpectrum routine? Yup, you are stuck with the "classic" tools for this part. The Spartan (non II or 3) parts are based on the XC4000 family for which all support is dropped in the new tools. They only support the Virtex like devices and derivatives. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76502
Sorry about that, I missclicked... My question is this: is there ANY Xilinx FPGA that comes in a PLCC84 or PC84 package that is supported by the WebPck tools? I couldn't find that package for Spartan II devices, only for CPLDs, and I really want to use an FPGA. Any Ideas? Thanks VadimArticle: 76503
"Philip Freidin" <philip@fliptronics.com> wrote in message news:6ecoq0dbu5066rjf2c9fumh4q2q7v5cegt@4ax.com... > Truth in posting: > > >Path: path!border1.nntp.dca.giganews.com!nntp.giganews.com!news.glorb.com!postnews .google.com!not-for-mail > >From: zhiman@hotmail.com (Zhi) > >Newsgroups: comp.arch.fpga > >Subject: Re: RocketIO success? > >Date: 29 Nov 2004 11:19:02 -0800 > >Organization: http://groups.google.com > >Lines: 46 > >Message-ID: <ce9c6dd6.0411291119.6cff39c0@posting.google.com> > >References: <cnl7em$9q3$1@hood.uits.indiana.edu> > >NNTP-Posting-Host: 66.35.226.228 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< > >Content-Type: text/plain; charset=ISO-8859-1 > >Content-Transfer-Encoding: 8bit > >X-Trace: posting.google.com 1101755942 24698 127.0.0.1 (29 Nov 2004 19:19:02 GMT) > >X-Complaints-To: groups-abuse@google.com > >NNTP-Posting-Date: Mon, 29 Nov 2004 19:19:02 +0000 (UTC) > >Xref: newsmst01a.news.prodigy.com comp.arch.fpga:78930 > > > nslookup 66.35.226.228 > Name: ip66-35-226-228.altera.com > Address: 66.35.226.228 > > >Paul Smith <ptsmith@nospam.indiana.edu> wrote in message news:<cnl7em$9q3$1@hood.uits.indiana.edu>... > >> I'm considering the V2pro series for several projects. LOL I posted once earlier about Altera (as company) being at Electronica 2004 in Munich - in true belive that it was so, as when I was at that booth (Altera!) I asked "you are from Altera?" YES "From Altera directly, not representing them?" YES ang guess what? after the fair I looked at the business card that guy gave me: "Altera, represented by somecompany" !!? now someone posting under bogus name from Altera corp machine to the newsgroup, gosh what a world! AnttiArticle: 76504
"Vadim Vaynerman" <vadimv@ieee.org> wrote in message news:ee8a751.0@webx.sUN8CHnE... > Sorry about that, I missclicked... > > My question is this: is there ANY Xilinx FPGA that comes in a PLCC84 or > PC84 package that is supported by the WebPck tools? I couldn't find that > package for Spartan II devices, only for CPLDs, and I really want to use > an FPGA. Any Ideas? Use Altera Flex devices. They are available in PLCC and are supported by the current Altera free tools. LeonArticle: 76505
"Antti Lukats" <antti@case2000.com> wrote in message news:cosmqc$q0c$02$1@news.t-online.com... > if you have IP core that supports MMC then inserting SD card would yield > the > card to not be recognized at all. I could have thought a major point would be to produce something compatible with MMC and not annoy existing customers with loads of MMC equipment. Perhaps the SD spec just allows you to read MMC cards instead of having to replace them. > PS MMC spec ver 4 adds 8bit - per clock mode and 52MHz max clock so the > max > transfer rates are getting higher! > MMC_ver4 uses 6 more pins in addition to the SD card pins I wish they would just define card standards with an array of pin positions for D0...Dn and leave it up to the reader to detect and use whatever width of data bus both can support.Article: 76506
Hello from Gregg C Levine Is anyone using the JTAG software originally from the OpenWINCE project? http://openwince.sourceforge.net One of the defined interfaces is that of the one that Xilinix suggests for their hardware. -- Gregg C Levine landocalrissian atsign att dot net "This signature proudly flies X-Wings."Article: 76507
Hey, I was considering purchasing a DS-KIT-2VP20FF1152-SF eval board from Memec. http://www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIPro_FF1152_2.pdf I thought about getting a Virtex4 board, but I have not seen one with the Power PC yet. I need to commit a purchase before the end of the year. I've already got some of their mezzanine boards and system ACE adapter. I thought the Rocket I/O might be fun to play with. I want board resources to boot u-boot and Linux. It looks like I get a pretty good EDK bundle deal with this package. Maybe I should go with a P30? If anybody can comment on the Pro's and Con's before I commit the purchase, I would appreciate it very much. -Thanks, NewmanArticle: 76508
Hello, Xilinx has provided with HWICAP module which allows one to read and write configuration frames within the same FPGA. In the documentation it has been mentioned that using it one can read/write CLB frames but no mention has been made about BRAM frames. Will it also be able to access and update BRAM's as well? Please do let me know. Thanks HarishArticle: 76509
"newman5382" <newman5382@yahoo.com> wrote in message news:Pyusd.120442$6w6.36835@tornado.tampabay.rr.com... > Hey, > I was considering purchasing a DS-KIT-2VP20FF1152-SF eval board from > Memec. > > http://www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIPro_FF1152_2.pdf > > I thought about getting a Virtex4 board, but I have not seen one with the > Power PC yet. > I need to commit a purchase before the end of the year. > I've already got some of their mezzanine boards and system ACE adapter. > I thought the Rocket I/O might be fun to play with. > I want board resources to boot u-boot and Linux. > It looks like I get a pretty good EDK bundle deal with this package. > Maybe I should go with a P30? > > If anybody can comment on the Pro's and Con's before I commit the purchase, > I would appreciate it very much. we use that same board with VP20 for many purposes, its very good value for the price. VP20 is big enough, so the VP20 vs VP30 decision is yours and depends on budget. V4FX boards will defenetly not be available this year not even for preorder so if you need to place the order this year then this memec board is possible the best solution specially when you already have the sysace module and p160 boards you can use. we have a uclinux version working on this board, but using our simple bootloader to load the image from systemace AnttiArticle: 76510
Hello all, I've a design that contains a NCO (Numerically controlled oscillator). The NCO consists of a 32'bit accumulator. when i write the accumulator straight forward like this - process (clk,resetn) begin if resetn = '0' then accumulator <= (others =>'0'); elsif clk'event and clk ='1' then accumulator <= accumulator + inc_value; end if; end process; Fout <= accumulator (accumulator'high); the maximum frequency I can achive for 'clk' is ~ 150 MHz (spartan 3). I need it to work in ~200 MHz so I figured out that some pipelining is needed but I dont know how to do it because of the accumulator feedback. Maybe someone here can explain it to me or even give me a code example (which will be great). Thanks in advance, Moti.Article: 76511
>the maximum frequency I can achive for 'clk' is ~ 150 MHz (spartan 3). >I need it to work in ~200 MHz so I figured out that some pipelining is >needed but I dont know how to do it because of the accumulator >feedback. Maybe someone here can explain it to me or even give me a >code example (which will be great). google for carry-save adder. Or counter. The idea is to break the adder into chunks. The carry-out of each chunk goes into a FF and then into the carry-in of the next chunk. Chop it up into chunks that are small enough that they meet your speed requirements. With modern dedicated carry logic, this doesn't work as well as it did in the old days. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76512
"Moti Cohen" <moti@terasync.net> wrote in message news:c04bfe33.0412050155.7afd29ee@posting.google.com... > Hello all, > I've a design that contains a NCO (Numerically controlled oscillator). > The NCO consists of a 32'bit accumulator. when i write the accumulator > straight forward like this - > > process (clk,resetn) > begin > if resetn = '0' then > accumulator <= (others =>'0'); > elsif clk'event and clk ='1' then > accumulator <= accumulator + inc_value; > end if; > end process; > Fout <= accumulator (accumulator'high); > > the maximum frequency I can achive for 'clk' is ~ 150 MHz (spartan 3). > I need it to work in ~200 MHz so I figured out that some pipelining is > needed but I dont know how to do it because of the accumulator > feedback. Maybe someone here can explain it to me or even give me a > code example (which will be great). > > Thanks in advance, Moti. http://ipcores.openchip.org/ddsx.html NCO with max (virtual) frequency of 11 (eleven)GHz! for your speed you possible can optimize the adder to get the performance. however it is also possible to have way higher clock frequences for the NCO then the FPGA fabric supports. it is resource consuming but working solution. to get 11GHz performance (using V4 rocketio) the 40 NCO words are calculated each clock cycle and then the result is serialized in with rocket SERDES similarly in FPGA's with no special serdes there would be still be some speed gain using the NCO at lower frequency and calculatig maybe 4 or 8 bits per clock and then using very fast shift register to shif the bits out. that approuch would be useable for 400M+ frequencies (within FPGA fabric) AnttiArticle: 76513
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message news:cosqsi$214r$1@agate.berkeley.edu... > In article <colg9a$aeo1@cliff.xsj.xilinx.com>, > Jim Wu <nospam@nospam.com> wrote: > >picoblaze might be a good fit. > > Picoblaze is probably significantly slower and larger: The core of > the state machine needs to be at 125 MHz. > > But thanks for the suggestion. > -- > Nicholas C. Weaver. to reply email to "nweaver" at the domain > icsi.berkeley.edu picoblaze could possible run at 125MHz too, but it takes a little more resources than BRAM based statemachine. http://ipcores.openchip.org/rsm.html :) I really wonder there is no BlockRAM statemachine tool yet available, the "core" itself itself is plain simple so only some script is needed to prepare the rom contents. I hope I could find time todo it ! AnttiArticle: 76514
Hi Hall, you said -> The idea is to break the adder into chunks.. I know that I need to break the logic but my problem is what to do with the feedback path, should I break it too ? Regards, Moti.Article: 76515
Hi Antti, you worte -> http://ipcores.openchip.org/ddsx.html NCO with max (virtual) frequency of 11 (eleven)GHz! I couldnt find any detailed description there (only features + deliverables description for buying it) you worte -> For your speed you possible can optimize the adder to get the performance How would you suggest on doing this ? you worte -> similarly in FPGA's with no special serdes there would be still be some speed gain using the NCO at lower frequency and calculatig maybe 4 or 8 bits per clock and then using very fast shift register to shif the bits out. that approuch would be useable for 400M+ frequencies (within FPGA fabric It seems to be very very interesting solution for me (higher frequency = less jitter !! ) but I didnt realy understood how does it works so I will appreciate it if you will provide me with more details or a with a link to a detailed desciption.. Thanks, Moti.Article: 76516
Moti Cohen wrote:
>
> Hello all,
> I've a design that contains a NCO (Numerically controlled oscillator).
> The NCO consists of a 32'bit accumulator. when i write the accumulator
> straight forward like this -
>
> process (clk,resetn)
> begin
> if resetn = '0' then
> accumulator <= (others =>'0');
> elsif clk'event and clk ='1' then
> accumulator <= accumulator + inc_value;
> end if;
> end process;
> Fout <= accumulator (accumulator'high);
>
> the maximum frequency I can achive for 'clk' is ~ 150 MHz (spartan 3).
> I need it to work in ~200 MHz so I figured out that some pipelining is
> needed but I dont know how to do it because of the accumulator
> feedback. Maybe someone here can explain it to me or even give me a
> code example (which will be great).
>
> Thanks in advance, Moti.
This is not elegant and it uses three times the resources, but it should
run at twice your current speed.
process (clk,resetn)
begin
if resetn = '0' then
phase <= (others =>'0');
accsingle <= (others =>'0');
accdouble <= (others =>'0');
accfast <= (others =>'0');
elsif clk'event and clk ='1' then
phase <= not phase;
if (phase = '0') then
accfast <= accsingle;
else
accfast <= accdouble;
accsingle <= accdouble + inc_value;
accdouble <= accdouble + inc_value sll 1;
end if;
end if;
end process;
Fout <= accfast (accfast'high);
I don't have a feel for how close your speed is to the theoretical
maximum, but have you tried optimizing your current design by using the
floorplanner? First, find out what your critical path is. I expect it
will be from "inc_value" to "accumulator". If so, you can place
"inc_value" adjacent to "accumulator" to improve the routing delay.
One other note, I don't know if the tools are smart enough to deal with
a low true async reset. I always make mine high true and I belive that
is the way it is spec'd for the startup block in Xilinx FPGAs. If a low
true reset works, then nevermind...
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 76517"Antti Lukats" <antti@case2000.com> wrote in message news:coui5t$gbg$04$1@news.t-online.com... > "newman5382" <newman5382@yahoo.com> wrote in message > news:Pyusd.120442$6w6.36835@tornado.tampabay.rr.com... >> Hey, >> I was considering purchasing a DS-KIT-2VP20FF1152-SF eval board from >> Memec. >> >> > http://www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIPro_FF1152_2.pdf >> >> I thought about getting a Virtex4 board, but I have not seen one with > the >> Power PC yet. >> I need to commit a purchase before the end of the year. >> I've already got some of their mezzanine boards and system ACE adapter. >> I thought the Rocket I/O might be fun to play with. >> I want board resources to boot u-boot and Linux. >> It looks like I get a pretty good EDK bundle deal with this package. >> Maybe I should go with a P30? >> >> If anybody can comment on the Pro's and Con's before I commit the > purchase, >> I would appreciate it very much. > > we use that same board with VP20 for many purposes, its very good value > for > the price. > VP20 is big enough, so the VP20 vs VP30 decision is yours and depends on > budget. > V4FX boards will defenetly not be available this year not even for > preorder > so if you need to place the order this year then this memec board is > possible the best solution specially when you already have the sysace > module > and p160 boards you can use. > > we have a uclinux version working on this board, but using our simple > bootloader to load the image from systemace > Antti, Thanks for the reply. I kept on thinking about my possible purchase after I posted, and also looked thru some of the Virtex4 data sheets. The Tri-mode Ethernet Media Access Controller looked to be a compelling reason for me to wait till next year. Yes, I know I said I needed to order before the end of the year. Another FPGA vendor gave a presentation about custom ASIC blocks in their FPGA fabric that they might initially fill with an Ethernet MAC(s). I thought that was a good idea, I wish Xilinx would do something like that. It appears that they are. Thanks again for taking the time to share your VirtexIIPro experience with me. I do appreciate it. -NewmanArticle: 76518
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:41B32744.70D3A95F@yahoo.com...
> Moti Cohen wrote:
> >
> > Hello all,
> > I've a design that contains a NCO (Numerically controlled oscillator).
> > The NCO consists of a 32'bit accumulator. when i write the accumulator
> > straight forward like this -
> >
> > process (clk,resetn)
> > begin
> > if resetn = '0' then
> > accumulator <= (others =>'0');
> > elsif clk'event and clk ='1' then
> > accumulator <= accumulator + inc_value;
> > end if;
> > end process;
> > Fout <= accumulator (accumulator'high);
Selected Device : 3s1500fg676-5
Number of Slices: 17 out of 13312 0%
Speed Grade: -5
Minimum period: 4.407ns (Maximum Frequency: 226.912MHz)
----------------------------------------------------------------------------
----
Constraint | Requested | Actual |
Logic
| | |
Levels
----------------------------------------------------------------------------
----
TS_clk = PERIOD TIMEGRP "clk" 5 nS HIG | 5.000ns | 4.847ns | 2
H 50.000000 % | | |
----------------------------------------------------------------------------
----
> > the maximum frequency I can achive for 'clk' is ~ 150 MHz (spartan 3).
> > I need it to work in ~200 MHz so I figured out that some pipelining is
> > needed but I dont know how to do it because of the accumulator
> > feedback. Maybe someone here can explain it to me or even give me a
> > code example (which will be great).
> >
> > Thanks in advance, Moti.
>
> This is not elegant and it uses three times the resources, but it should
> run at twice your current speed.
>
> process (clk,resetn)
> begin
> if resetn = '0' then
> phase <= (others =>'0');
> accsingle <= (others =>'0');
> accdouble <= (others =>'0');
> accfast <= (others =>'0');
> elsif clk'event and clk ='1' then
> phase <= not phase;
> if (phase = '0') then
> accfast <= accsingle;
> else
> accfast <= accdouble;
> accsingle <= accdouble + inc_value;
> accdouble <= accdouble + inc_value sll 1;
> end if;
> end if;
> end process;
> Fout <= accfast (accfast'high);
Selected Device : 3s1500fg676-5
Number of Slices: 34 out of 13312 0%
Speed Grade: -5
Minimum period: 4.632ns (Maximum Frequency: 215.889MHz)
----------------------------------------------------------------------------
----
Constraint | Requested | Actual |
Logic
| | |
Levels
----------------------------------------------------------------------------
----
TS_clk = PERIOD TIMEGRP "clk" 5 nS HIG | 5.000ns | 4.886ns | 2
H 50.000000 % | | |
----------------------------------------------------------------------------
----
Rick, hmmm... care to comment?
see synthesis and timing reports above :)
Antti
Article: 76519"newman5382" <newman5382@yahoo.com> wrote in message news:FGGsd.94295$8G4.47360@tornado.tampabay.rr.com... > > "Antti Lukats" <antti@case2000.com> wrote in message > news:coui5t$gbg$04$1@news.t-online.com... > > "newman5382" <newman5382@yahoo.com> wrote in message > > news:Pyusd.120442$6w6.36835@tornado.tampabay.rr.com... > >> Hey, > >> I was considering purchasing a DS-KIT-2VP20FF1152-SF eval board from > >> Memec. > >> > >> > > http://www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIPro_FF1152_2.pdf > >> > >> I thought about getting a Virtex4 board, but I have not seen one with > > the > >> Power PC yet. > >> I need to commit a purchase before the end of the year. > >> I've already got some of their mezzanine boards and system ACE adapter. > >> I thought the Rocket I/O might be fun to play with. > >> I want board resources to boot u-boot and Linux. > >> It looks like I get a pretty good EDK bundle deal with this package. > >> Maybe I should go with a P30? > >> > >> If anybody can comment on the Pro's and Con's before I commit the > > purchase, > >> I would appreciate it very much. > > > > we use that same board with VP20 for many purposes, its very good value > > for > > the price. > > VP20 is big enough, so the VP20 vs VP30 decision is yours and depends on > > budget. > > V4FX boards will defenetly not be available this year not even for > > preorder > > so if you need to place the order this year then this memec board is > > possible the best solution specially when you already have the sysace > > module > > and p160 boards you can use. > > > > we have a uclinux version working on this board, but using our simple > > bootloader to load the image from systemace > > > > Antti, > Thanks for the reply. I kept on thinking about my possible purchase after > I posted, and also looked thru some of the Virtex4 data sheets. The > Tri-mode Ethernet Media Access Controller looked to be a compelling reason > for me to wait till next year. Yes, I know I said I needed to order before > the end of the year. Another FPGA vendor gave a presentation about custom > ASIC blocks in their FPGA fabric that they might initially fill with an > Ethernet MAC(s). I thought that was a good idea, I wish Xilinx would do > something like that. It appears that they are. > > Thanks again for taking the time to share your VirtexIIPro experience with > me. I do appreciate it. > > -Newman :) yes AGREE, if the money you can use is not of that kind that you *must* spend before the end of the year, then it makes sense to wait for V4FX - but prepare for some waiting, there is no direct info when FX based boards would come out. I wasnt able to wait so I ordered the V4LX from Avnet to get V4 taste, unfortunatly did rush too much, should have ordered ML401 thats a real nice piece of hardware for the $499 AnttiArticle: 76520
Moti Cohen wrote:
> elsif clk'event and clk ='1' then
> accumulator <= accumulator + inc_value;
> end if;
> end process;
> Fout <= accumulator (accumulator'high);
>
> the maximum frequency I can achive for 'clk' is ~ 150 MHz (spartan 3).
> I need it to work in ~200 MHz so I figured out that some pipelining is
> needed but I dont know how to do it because of the accumulator
> feedback.
Hmmm...
If inc_value'length < accumulator'length, maybe you
could do a slice addition of the lower bits with the
result msbit piped to enable an increment of the upper bits.
-- Mike Treseler
Article: 76521Hi Rickman, First of all, thanks for the code example It's always nice and clearer to get one of this. there is only one thing bothering me in your code - the "accsingle" register is sampled on each rising edge of clock and therefore does not improves the setup time (and therefore the frequency & clk rate) i suppose that it should be sampled on every 2'nd clock. So maybe your code contains a typo but the idea is "almost" clear and i'ts a very clever one. I presented this subject (my problem) to our algorithm's guy and he figured out a very nice way of breaking the logic into to or more levels (4, 8..) , but he is still working on it I will write the code here when he will finish it.. Thanks Moti.Article: 76522
Antti Lukats wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:41B32744.70D3A95F@yahoo.com... > > Moti Cohen wrote: > > > > > > Hello all, > > > I've a design that contains a NCO (Numerically controlled oscillator). > > > The NCO consists of a 32'bit accumulator. when i write the accumulator > > > straight forward like this - > > > > > > process (clk,resetn) > > > begin > > > if resetn = '0' then > > > accumulator <= (others =>'0'); > > > elsif clk'event and clk ='1' then > > > accumulator <= accumulator + inc_value; > > > end if; > > > end process; > > > Fout <= accumulator (accumulator'high); > > Selected Device : 3s1500fg676-5 > Number of Slices: 17 out of 13312 0% > Speed Grade: -5 > Minimum period: 4.407ns (Maximum Frequency: 226.912MHz) > > ---------------------------------------------------------------------------- > ---- > Constraint | Requested | Actual | > Logic > | | | > Levels > ---------------------------------------------------------------------------- > ---- > TS_clk = PERIOD TIMEGRP "clk" 5 nS HIG | 5.000ns | 4.847ns | 2 > H 50.000000 % | | | > ---------------------------------------------------------------------------- > ---- > > > > the maximum frequency I can achive for 'clk' is ~ 150 MHz (spartan 3). > > > I need it to work in ~200 MHz so I figured out that some pipelining is > > > needed but I dont know how to do it because of the accumulator > > > feedback. Maybe someone here can explain it to me or even give me a > > > code example (which will be great). > > > > > > Thanks in advance, Moti. > > > > This is not elegant and it uses three times the resources, but it should > > run at twice your current speed. > > > > process (clk,resetn) > > begin > > if resetn = '0' then > > phase <= (others =>'0'); > > accsingle <= (others =>'0'); > > accdouble <= (others =>'0'); > > accfast <= (others =>'0'); > > elsif clk'event and clk ='1' then > > phase <= not phase; > > if (phase = '0') then > > accfast <= accsingle; > > else > > accfast <= accdouble; > > accsingle <= accdouble + inc_value; > > accdouble <= accdouble + inc_value sll 1; > > end if; > > end if; > > end process; > > Fout <= accfast (accfast'high); > > Selected Device : 3s1500fg676-5 > Number of Slices: 34 out of 13312 0% > Speed Grade: -5 > Minimum period: 4.632ns (Maximum Frequency: 215.889MHz) > > ---------------------------------------------------------------------------- > ---- > Constraint | Requested | Actual | > Logic > | | | > Levels > ---------------------------------------------------------------------------- > ---- > TS_clk = PERIOD TIMEGRP "clk" 5 nS HIG | 5.000ns | 4.886ns | 2 > H 50.000000 % | | | > ---------------------------------------------------------------------------- > ---- > > Rick, hmmm... care to comment? > see synthesis and timing reports above :) This shows that my approach will run twice as fast. It produces two results rather than one and so can be constrained to require two clock periods. You need to set your timing constraints to reflect that. The only paths that don't run at the half clock rate are the output mux running into accfast and the phase control signal. Set the path delay on the accsingle and accdouble paths to be *two* clock periods (except for the enable from phase). But your timing numbers show both designs running at over 200 MHz which is the OPs requirement, IIRC. Did you have to do any floorplanning? Also, are these numbers post ROUTE or the output from synthesis? Timing results from synthesis are worthless. I would like to see the details on the critical path in each case. The logic for my code should be a minimum of 97 LUTs. Your result is only 34 slices which is a maximum of 68 LUTs. I suspect there is some problem so that the code does not synthesize correctly (possibly in the code). I have not looked at the CLB details of the newer Xilinx FPGAs. An adder still requires 1 LUT per bit, right? inc_value is a signal and not a constant, right? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76523
Hi Mike, Yes I know that, but my design inc_value'length is almost as the accumulator'length ( maybee I will be able to decrese two bits..) so it won't give me much more slack.. Thanks. Moti.Article: 76524
Moti wrote: > > Hi Rickman, > > First of all, thanks for the code example It's always nice and clearer > to get one of this. > there is only one thing bothering me in your code - the "accsingle" > register is sampled on each rising edge of clock and therefore > does not improves the setup time (and therefore the frequency & clk > rate) i suppose that it should be sampled on every 2'nd clock. So maybe > your code contains a typo but the idea is "almost" clear and i'ts a > very clever one. Yes, both accsingle and accdouble are sampled on the rising edge of the clock, but only when phase is high and so only *every other* clock. I guess I figured that would be obvious. The addfast signal captures the output of a mux on *every* clock so that it still has to run at full speed. But this path has no carry, so it should be faster than your previous result. In any regard, you can likely improve your results by floorplanning so that the registers involved are in ajacent (or even the same) CLBs to optimize routing. I see no reason that your original design would not run at 200 MHz. > I presented this subject (my problem) to our algorithm's guy and he > figured out a very nice way of breaking the logic into to or more > levels (4, 8..) , but he is still working on it I will write the code > here when he will finish it.. You will find that approach reduces the length of the carry path. But the basic minimum path is from one register output through the LUT and into a second register. This will be the ultimate limit for any adder design if you reduce the carry delay to a single LUT. To reach the full speed capability you likely will need to floorplan to get the optimally fast routing which will be between registers in the same CLB. At that point your carry delay may not matter with your requirement of 5 nS. Typically the carry delay is < 0.1 ns/bit or < 3.2 ns for the 32 bit adder. I guess all those words are trying to say that you can only do so much with pipelining an adder. Pipelining will break up the carry delay, the finer you break it up, the closer to get to the reg -> LUT -> reg delay, not zero delay. My dual parallel approach gets you directly to the minimum delay if that is what's needed. But try floorplanning before you do any more work with the algorithm. That should be sufficient at 32 bits. Also, you did place and route it, right? The timing results from synthesis are not very accurate since they "estimate" routing times. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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