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Messages from 21400

Article: 21400
Subject: How to solder FPGA in BGA package ?
From: edlee@gpetech.com (Edward)
Date: Wed, 22 Mar 2000 01:37:11 GMT
Links: << >>  << T >>  << A >>
We will be using a 350-pin BGA chip and is looking for some soldering
equipments such as hot air machines or IR ovens for very small
quantity prototyping.  I am looking for suggestions and tips for
shopping and using such equipments.

Edward


Article: 21401
Subject: Re: Clock nets using non-dedicated resources
From: "Tim" <tim@tile.demon.co.uk.notreally>
Date: Tue, 21 Mar 2000 19:38:06 -0700
Links: << >>  << T >>  << A >>
This solution is very tedious, but it should work.
A PERL hack would speed the search

  1.  use XDL to generate a .xdl file from your .ncd
      the syntax is "xdl -ncd2xdl designname"
  2.  search in the .xdl file for lines which look like this:

      net "clk_net_name" ,
        inpin  "instance_name_1" CLK                ,
        inpin  "instance_name_2" CLK                ,

The net for which you search should emerge :)


<boniolopez@my-deja.com> wrote in message
news:8b5mrk$k76$1@nnrp1.deja.com...
> Hi all,
> I'm not very new in FPGA design but I can't find the issue of
following
> problem:
>
>
> WARNING:Timing:33 - Clock nets using non-dedicated resources were
found
> in this
>    design. Clock skew on these resources will not be automatically
> addressed
>    during path analysis. To create a timing report that analyzes clock
> skew for
>    these paths, run trce with the '-skew' option.
>
>
>
> I'm quite sure to use in my design the deducted clock resources only
> (and connected to BufG or Buf GP). I think the syntheses tool can'
> recognise some part in my design and form it so, that clock some FF
> with the gated signal. But I cant find where.
>
> THE QUESTION: How I can find out where  the Alliance 2.1i found the
non-
> dedicated resources(which signal is such clock)?
>
> Any help will be appreciated,
> Bonio
> Remove_this_Bonio.lopez@gmx.ch_remove_this
>
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 21402
Subject: Good book on learning FPGA/VHDL/Verilog programming
From: pratipm@yahoo.com (Pratip Mukherjee)
Date: Wed, 22 Mar 2000 03:02:46 GMT
Links: << >>  << T >>  << A >>
I want learn about FPGA and VHDL or Verilog programming. I am planning to buy 
the kit from XESS Corp. along with their book and software. Is that sufficient 
for learning or should I also buy a standard book on the subject? In that case 
which book has good practical examples for the starters to try (which are not 
too simple like blink a LED nor too difficult like design of a 16bit RISC 
processor, as in the recent Circuit Cellar article?
Thanks.

Pratip Mukherjee
Article: 21403
Subject: Re: Virtex DLL inoperability
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 22 Mar 2000 03:22:07 GMT
Links: << >>  << T >>  << A >>
In article <20000320135410.12748.00002045@nso-fp.aol.com>, Winzker wrote:
>Im Artikel <38D0E9E8.CAC88D25@NOSPAM.com>, David Gilchrist
><david.gilchrist@NOSPAM.com> schreibt:
>
>>It turned out to be a problem with the place and route tool (Service
>>Pack 3 surprisingly enough).  The P & R tool was corrupting the bits
>>during BitGen. When this was updated the problem magically disappeared.
>
>This gives me the opportunity to ask Xilinx to be more open with information
>about problems. I'm a regular reader of the Xilinx web page, but when we
>had problems with the DLL I didn't found any hint to this problem.

I'd like to second that.  I've been browsing Xilinx's page for the past
couple days and in 10 minutes of reading this newsgroup I've found a lot
more information about Xilinx and their products than I did on their whole
webpage (not to mention significant misinformation supplied by their
webpage).  The whole thing stinks. :)
Article: 21404
Subject: Re: Virtex DLL inoperability
From: Peter Alfke <palfke@earthlink.net>
Date: Wed, 22 Mar 2000 04:06:35 GMT
Links: << >>  << T >>  << A >>


Greg Alexander wrote:

>   I've been browsing Xilinx's page for the past
> couple days and in 10 minutes of reading this newsgroup I've found a lot
> more information about Xilinx and their products than I did on their whole
> webpage (not to mention significant misinformation supplied by their
> webpage).  The whole thing stinks. :)

Strong words!
You have seen me jump in and clarify hardware and configuration questions.  If
you have a real problem, send me e-mail, and I will answer when I can.


Peter Alfke, Xilinx Applications
peter@xilinx.com

Article: 21405
Subject: Re: How to solder FPGA in BGA package ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 22 Mar 2000 01:05:03 -0500
Links: << >>  << T >>  << A >>
Edward wrote:
> 
> We will be using a 350-pin BGA chip and is looking for some soldering
> equipments such as hot air machines or IR ovens for very small
> quantity prototyping.  I am looking for suggestions and tips for
> shopping and using such equipments.
> 
> Edward

I just went through this for my board and I recommend that you stay away
from BGA packages unless you have access to a fab house with both the
equipment and the experience to use them. I first tried using a fab
house that had done some BGA projects with a hot air rework machine. My
board did not fare well with that method. Only 2 out of 6 boards worked
correctly and they used 8 chips doing them. Two of the chips were
assembled badly enough that they were removed before testing. 

One piece of equipment that is essential when mounting prototype BGAs is
an XRAY machine. That is the only way you can inspect the joints since
they are under the chip and not visible. Not many places have them. 

The soldering and mounting of the BGA chip itself is not a big deal. The
pitch is as large or larger than many other surface mount parts. An IR
oven likely won't work since it depends on direct heating by radient
heat. Much like a light beam, it is blocked by objects such as the BGA
package itself. I don't know for sure, but I think it would be a problem
to heat the package up enough to reflow the solder underneath. But as I
say, this I am not sure about this. 

So I suggest that you find a competent fab house that has experience
with BGA mounting. One place I can recommend is BEST in Rolling Meadows,
IL. Their phone number is 847/797-9250. The work they did for me was
good. Five out of five new boards worked fine. 

I am having my small production run done at Kuchera in Windber, PA,
phone number 814-467-9779. I have not seen their work yet. I will be
getting my boards back from them late this week. I can let you know how
it goes if you want. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21406
Subject: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 22 Mar 2000 06:06:59 GMT
Links: << >>  << T >>  << A >>
Is there anywhere for me to get the bitstream specs for xilinx chips?  I
want to buy the chip and then interface with it, I have no interest in
buying the chip and then something to interface with it, and then
installing windows to use the interface (in other words, I'm not going to
use Foundation or XSE or whatever, even if they are good, but I still want
to program the things).
Article: 21407
Subject: Re: Clock nets using non-dedicated resources
From: =?iso-2022-jp?B?GyRCMEIwZhsoQiAbJEI3chsoQg==?= <yasui149@oki.co.jp>
Date: Wed, 22 Mar 2000 15:14:19 +0900
Links: << >>  << T >>  << A >>
I think you should check the Map report file (.mrp) .
Section 2 describes gated clock name. and search that net in Section 8. load
and driver component of that net will be found.




Article: 21408
Subject: Virtex Secondary Clock Nets
From: "Tim" <tim@tile.demon.co.uk.notreally>
Date: Tue, 21 Mar 2000 23:24:01 -0700
Links: << >>  << T >>  << A >>
I have a telecomms application in which I need to
synchronize nine independent incoming data links to a
common (faster) Virtex clock.  I plan on putting
a FIFO (built from DP RAMs) on each incoming link
and clocking the FIFO inputs with the incoming clocks.

Each FIFO will be 16 Virtex slices and I would
like to drive the slice clock inputs with a signal
which goes

  from the incoming clock IOB
    via a secondary clock line
      to the slice clock inputs.

Since the FPGA will be somewhat full, and I want to
protect myself against the FIFO slices going walkabout,
I need to know where I should place them so that the
secondary clock routing works out optimally.

I guess the answer is something like this:

  "if the clock input is in column nn, put the FIFO
   slices in a vertical line in column nn+1"

But all my experiments have given pretty sub-optimal
results after PAR.  This was soooo easy with the GCLKs
in the XC4000.  Does anyone have any idea how to do the
placement with Virtex?

If Peter Alfke, or another of the Xilinx experts, is
reading this, it would be really nice to get an
explanation of which are the secondary clock wires, as
viewed in FPGA Editor, and how we arrange to route
on and off there wires.  This stuff was tremendously
well described for the 2000/3000/4000 in the old data
books.

Thanks



Article: 21409
Subject: Re: FPGA openness
From: Hobson Frater <hobson@xilinx.com>
Date: Tue, 21 Mar 2000 23:40:26 -0800
Links: << >>  << T >>  << A >>
Greg,

I'm not familiar with your level of knowledge about Xilinx and our products,
so please forgive me if the following is not what you're looking for.

The bitstream specs for Xilinx devices, indeed most programmable devices from
most companies, are proprietary.  This is done to ensure that our customers'
designs aren't copied or reverse-engineered (well at least not without a lot
of trouble) by our customers' competitors.

Now, I can read what you've said about the software in two different ways.
Again, I apologize if I've misunderstood you.

The first way I could read it is that you believe that you need to have
windows as well as our software running in the system in which your Xilinx
device will operate.  That is, you need to have the software on the board you
are designing.  This is not the case.  The software is used purely in the
development of the design, not for interfacing with the device.  Once the
design is finished and the bitstream has been generated, there is no need for
the software to be present in order for the device to work the way you've
designed it to work.

The other way I could read your comments is that you understand that the
software is for design development purposes only and that you just don't want
to have to use it.  As the above information may indicate, since the spec is
proprietary, there is really no other way to generate a bitstream than to use
the software.  I would mention, too, that our devices have many complex
features and can get quite large.  Designing something like this by hand
rather than using archetecture-specific mapping and placement & routing
software would be extremely difficult.  The bitstreams themselves range from
~54K bits to the tens of millions of bits.

Now, that said, there *is* a tool available for quickly modifying bitstreams
(not creating them from scratch).  It is called JBits, and you can read more
about it at http://www.xilinx.com/xilinxonline/jbits.htm

I hope this helps.

Regards,
Hobson Frater
Xilinx Customer Applications

Greg Alexander wrote:

> Is there anywhere for me to get the bitstream specs for xilinx chips?  I
> want to buy the chip and then interface with it, I have no interest in
> buying the chip and then something to interface with it, and then
> installing windows to use the interface (in other words, I'm not going to
> use Foundation or XSE or whatever, even if they are good, but I still want
> to program the things).

Article: 21410
Subject: Re: How to solder FPGA in BGA package ?
From: "Holger Kleinert" <Kleinert@ibpmt.com>
Date: Wed, 22 Mar 2000 09:37:04 +0100
Links: << >>  << T >>  << A >>
Hi !
For minimum equipment you need:

A metal printing frame for printing solder glue on the pads.
Then you have to place the part correctly on the board.
At least you need an oven to solder the parts.
This oven can be a standard thing like used for normal SMD soldering in
values.

At least you must scan the part with JTAG, or better use a XRAY machine.
JTAG scanning is much more cheaper :-)

Regards,
Holger

Edward <edlee@gpetech.com> schrieb in im Newsbeitrag:
38d8238c.23492640@news.bctel.net...
> We will be using a 350-pin BGA chip and is looking for some soldering
> equipments such as hot air machines or IR ovens for very small
> quantity prototyping.  I am looking for suggestions and tips for
> shopping and using such equipments.
>
> Edward
>
>


Article: 21411
Subject: Re: How to solder FPGA in BGA package ?
From: rob_dickinson@my-deja.com
Date: Wed, 22 Mar 2000 08:40:02 GMT
Links: << >>  << T >>  << A >>
In article <38D8628F.30F7146@yahoo.com>,
Rickman <spamgoeshere4@yahoo.com> wrote:
> Edward wrote:
> >
> > We will be using a 350-pin BGA chip and is looking for some
soldering
> > equipments such as hot air machines or IR ovens for very small
> > quantity prototyping. I am looking for suggestions and tips for
> > shopping and using such equipments.
> >
> > Edward
>
> I just went through this for my board and I recommend that you stay
away
> from BGA packages unless you have access to a fab house with both the
> equipment and the experience to use them. I first tried using a fab
> house that had done some BGA projects with a hot air rework machine.
My
> board did not fare well with that method. Only 2 out of 6 boards
worked
> correctly and they used 8 chips doing them. Two of the chips were
> assembled badly enough that they were removed before testing.
>
> One piece of equipment that is essential when mounting prototype BGAs
is
> an XRAY machine. That is the only way you can inspect the joints since
> they are under the chip and not visible. Not many places have them.
>
> The soldering and mounting of the BGA chip itself is not a big deal.
The
> pitch is as large or larger than many other surface mount parts. An IR
> oven likely won't work since it depends on direct heating by radient
> heat. Much like a light beam, it is blocked by objects such as the BGA
> package itself. I don't know for sure, but I think it would be a
problem
> to heat the package up enough to reflow the solder underneath. But as
I
> say, this I am not sure about this.
>
> So I suggest that you find a competent fab house that has experience
> with BGA mounting. One place I can recommend is BEST in Rolling
Meadows,
> IL. Their phone number is 847/797-9250. The work they did for me was
> good. Five out of five new boards worked fine.
>
> I am having my small production run done at Kuchera in Windber, PA,
> phone number 814-467-9779. I have not seen their work yet. I will be
> getting my boards back from them late this week. I can let you know
how
> it goes if you want.
>
> --
>
> Rick Collins

This isn't the NG for a big manufacturing discussion but this is my
tuppence worth and it's quite different to the above opinion.

1) XRAY.  No one in there right mind does xray inspection on large
batches of boards, it's done to callibrate a production line, if your
going to build more than a few then get to grips with designing jtag
into your system from the floor up, ie don't finish your design and
then wonder how to add jtag.  We got almost 100% coverage without going
to the likes of JTAG technologies or simillar.
2) If your going to do a lot of prototyping then just buy the latest
PACE machine or simillar and live with the fact that your going to
overheat your BGA's a bit to be safe (ie you won't be callibrating with
XRAY).  In 10 years time we'll all be wanting PACE or simillar to
supply us with wire bonding laser welding kit and wishing we could
still just get away with the BGA's that we've all become complete
comfortable with.
And then you will of course JTAG the finished result and keep in mind
that your BGA prototype might die early through overheating!
3) If your prototyping is low compared to your manufacturing then just
take your board to the assembler of your choice and put your PCB
through there oven with just the BGA mounted.  They will have
callibrated their oven, possibly with XRAY but probably statistically,
and you will get a perfectly mounted BGA out the other end. If they
have the promise of the final production run then they probably won't
charge you anything for doing so as it won't have cost them anything.

Rob


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21412
Subject: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
From: "Holger Kleinert" <Kleinert@ibpmt.com>
Date: Wed, 22 Mar 2000 10:21:04 +0100
Links: << >>  << T >>  << A >>
Hello All !

Actually I create a design with a Xilinx XCS20XL and Foundation Express V2.1
Software.
The design is VHDL only.

I have a problem concerning optimization of the design.
As the design does not use all signals on the bus,
I want some pins to be high impedance 'Z' all the time.

So, if I attach just a 'Z' in the architecture body to the signals they are
optimized away.
(See part of the listing below)
1) The pins then can not be places using the constraint file.
2) The pins get an pull up resistor attached.
Due to optimisation they are declares as 'not used', and all not used pins
get a pull up attached.

So my question :
What must I do to prevent the "pin away optimisation" for one signal.
Is it some directive like "-- don't touch " ???

Thank you for help

Holger

--***************

entity pci_target is
[....]

 nPERR    : out   std_logic;
 nSERR    : out   std_logic;

architecture pci_target_arch of pci_target is
[....]
      nPERR    <= 'Z';
      nSERR    <= 'Z';

--********************
--
Holger Kleinert
Development / Support

IBP Instruments GmbH
Sutelstrasse 7a
D-30659 Hannover, Germany

http://www.ibpmt.com
Fon : +49-511-652286
Fax : +49-511-652283




Article: 21413
Subject: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Wed, 22 Mar 2000 10:53:59 +0100
Links: << >>  << T >>  << A >>
Holger Kleinert a écrit :
> 
> Hello All !
> 
> Actually I create a design with a Xilinx XCS20XL and Foundation Express V2.1
> Software.
> The design is VHDL only.
> 
> I have a problem concerning optimization of the design.
> As the design does not use all signals on the bus,
> I want some pins to be high impedance 'Z' all the time.
> 
> So, if I attach just a 'Z' in the architecture body to the signals they are
> optimized away.
> (See part of the listing below)
> 1) The pins then can not be places using the constraint file.
> 2) The pins get an pull up resistor attached.
> Due to optimisation they are declares as 'not used', and all not used pins
> get a pull up attached.
> 
> So my question :
> What must I do to prevent the "pin away optimisation" for one signal.
> Is it some directive like "-- don't touch " ???

Exactly
If you use the GUI, choose "Edit synthesis constraints". You will be
able to place "don't touch" attributes on the pins you don't want to be
optimized away.
I think you can also put the constraints in you VHDL (if someone can
confirm my syntax):
-- pragma dc_script_begin
-- set_dont_touch <pin name>
-- set_dont_touch <other pin name>
...
-- pragma dc_script_end

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Reply-To: "Sherdyn" <sherdyn@yahoo.com>
Article: 21414
Subject: Re: How to solder FPGA in BGA package ?
From: "Sherdyn" <sherdyn@yahoo.com>
Date: Wed, 22 Mar 2000 18:33:36 +0800
Links: << >>  << T >>  << A >>
What is the cost of the JTAG equipment which can perform the boundary scan
function? Are there any ready made machine available and how easy is to
generate the scan chain and what is the whole process like?

Sherdyn

Holger Kleinert <Kleinert@ibpmt.com> wrote in message
news:8ba0ll$4o31t$1@fu-berlin.de...
> Hi !
> For minimum equipment you need:
>
> A metal printing frame for printing solder glue on the pads.
> Then you have to place the part correctly on the board.
> At least you need an oven to solder the parts.
> This oven can be a standard thing like used for normal SMD soldering in
> values.
>
> At least you must scan the part with JTAG, or better use a XRAY machine.
> JTAG scanning is much more cheaper :-)
>
> Regards,
> Holger
>
> Edward <edlee@gpetech.com> schrieb in im Newsbeitrag:
> 38d8238c.23492640@news.bctel.net...
> > We will be using a 350-pin BGA chip and is looking for some soldering
> > equipments such as hot air machines or IR ovens for very small
> > quantity prototyping.  I am looking for suggestions and tips for
> > shopping and using such equipments.
> >
> > Edward
> >
> >
>
>


Article: 21415
Subject: Re: How to solder FPGA in BGA package ?
From: Keith Wootten <Keith@wootten.demon.co.uk>
Date: Wed, 22 Mar 2000 10:42:55 +0000
Links: << >>  << T >>  << A >>
In article <38d8238c.23492640@news.bctel.net>, Edward
<edlee@gpetech.com> writes
>We will be using a 350-pin BGA chip and is looking for some soldering
>equipments such as hot air machines or IR ovens for very small
>quantity prototyping.  I am looking for suggestions and tips for
>shopping and using such equipments.
>
>Edward

Would it be possible to glue the chip in place using silver loaded epoxy
screened onto the PCB?  This is not a suggestion, just another question.

Cheers
-- 
Keith Wootten

-- 
Keith Wootten
Article: 21416
Subject: Re: Clock nets using non-dedicated resources
From: boniolopez@my-deja.com
Date: Wed, 22 Mar 2000 10:50:03 GMT
Links: << >>  << T >>  << A >>

>Wouldn't you use both edges ?
>I had the same problem some time ago (and YOU solve it ;o)

Hi Nicolas,
Glad to could help you.
But I in you report was a half of clock and in my report is whole clock
(250 and not
125). So I think to have another problem.
with best wishes,
Bonio
remove_this_bonio.lopez@gmx.ch

In article <38D7B5EE.FC773C65@dotcom.fr>,
Nicolas Matringe <nicolas@dotcom.fr> wrote:
> Wouldn't you use both edges ?
> I had the same problem some time ago (and YOU solve it ;o)
>
> boniolopez@my-deja.com a écrit :
> >
> > Hi all,
> > now I still see all my 4 clocks using BufG or BufGp also my
QUESTION IS
> > STILL ACTUAL.
> >
> > The second question now:
> > Below the results trce -skew.
> >
> > Why this constrain is not met if 177<250!!!!!!!!!
> > * TS_gpp1_dup0 = PERIOD TIMEGRP "gpp1_dup0" | 250.000ns | 177.536ns
|
> > 28
> > 250 nS HIGH 50.000 % | |
> > |
> >
>
> Nicolas MATRINGE DotCom S.A.
> Conception electronique 16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11 92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01 FRANCE
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21417
Subject: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
From: "Holger Kleinert" <Kleinert@ibpmt.com>
Date: Wed, 22 Mar 2000 12:30:12 +0100
Links: << >>  << T >>  << A >>
Hello Nicolas,

Thank you so far, I got the exactly syntax
-- pragma dc_script_begin
-- dont_touch {"nPERR"}
-- dont_touch {"nSERR"}
-- pragma dc_script_end

Unfortunately, this does not solve the problem complete.
I the Console Window I get a message like:

"Dpm : Warning: Port 'nPERR' has ot net attached to it - no pad cells
inserted at this port (FPGA-PADMAP-2)"

What Do I have to do now ?
Are there any other contraints to make ?

Thank you for help.
Regards,
--
Holger Kleinert
Development / Support

IBP Instruments GmbH
Sutelstrasse 7a
D-30659 Hannover, Germany

http://www.ibpmt.com
Fon : +49-511-651647
Fax : +49-511-652283


Nicolas Matringe <nicolas@dotcom.fr> schrieb in im Newsbeitrag:
38D89837.371C851C@dotcom.fr...
> Holger Kleinert a écrit :
> >
> > Hello All !
> >
> > Actually I create a design with a Xilinx XCS20XL and Foundation Express
V2.1
> > Software.
> > The design is VHDL only.
> >
> > I have a problem concerning optimization of the design.
> > As the design does not use all signals on the bus,
> > I want some pins to be high impedance 'Z' all the time.
> >
> > So, if I attach just a 'Z' in the architecture body to the signals they
are
> > optimized away.
> > (See part of the listing below)
> > 1) The pins then can not be places using the constraint file.
> > 2) The pins get an pull up resistor attached.
> > Due to optimisation they are declares as 'not used', and all not used
pins
> > get a pull up attached.
> >
> > So my question :
> > What must I do to prevent the "pin away optimisation" for one signal.
> > Is it some directive like "-- don't touch " ???
>
> Exactly
> If you use the GUI, choose "Edit synthesis constraints". You will be
> able to place "don't touch" attributes on the pins you don't want to be
> optimized away.
> I think you can also put the constraints in you VHDL (if someone can
> confirm my syntax):
> -- pragma dc_script_begin
> -- set_dont_touch <pin name>
> -- set_dont_touch <other pin name>
> ...
> -- pragma dc_script_end
>
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE


Article: 21418
Subject: Re: Clock nets using non-dedicated resources
From: boniolopez@my-deja.com
Date: Wed, 22 Mar 2000 12:15:29 GMT
Links: << >>  << T >>  << A >>
Thank you for good advice, yasui149
I have found the strange message in the .mrp file section 2.

WARNING:xvkpu:22 - The function generator
   inst_c68mx11/I_I_mpu0.s1[15].G_31.G_44 failed to merge with F5
multiplexer
   inst_c68mx11/mpu0/s_o[15].  There is a conflict for the FXMUX.  The
design
   will exhibit suboptimal

The net is situated inside the CPU core, I use.
Do you think this net cause the non-dedicated clock?. Can you explain
me why could be this conflict.

Thank you once more,
Bonio
remove_this_bonio.lopez@gmx.ch_remove_this

In article <8b9oog$bq3$1@lyra.eoa.telcom.oki.co.jp>,
=?iso-2022-jp?B?GyRCMEIwZhsoQiAbJEI3chsoQg==?= <yasui149@oki.co.jp>
wrote:
> I think you should check the Map report file (.mrp) .
> Section 2 describes gated clock name. and search that net in Section
8. load
> and driver component of that net will be found.
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21419
Subject: Re: Clock nets using non-dedicated resources
From: boniolopez@my-deja.com
Date: Wed, 22 Mar 2000 12:23:21 GMT
Links: << >>  << T >>  << A >>
Hi Andy,
Than you for replay.
I have tried to find your thread, but you write so many messages, that
it is impossiable without the subject name to find one. Could you write
the exact subj. or date of thread you mean.
regards,
Bonio
In article <8b8b8d$1t9b$1@noao.edu>,
"Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> wrote:
> boniolopez@my-deja.com wrote in message <8b5mrk$k76
$1@nnrp1.deja.com>...
> >Hi all,
> >I'm not very new in FPGA design but I can't find the issue of
following
> >problem:
> >
> >
> >WARNING:Timing:33 - Clock nets using non-dedicated resources were
found
> >in this
> > design. Clock skew on these resources will not be automatically
> >addressed
> > during path analysis. To create a timing report that analyzes clock
> >skew for
> > these paths, run trce with the '-skew' option.
> >
> >
> >
> >I'm quite sure to use in my design the deducted clock resources only
> >(and connected to BufG or Buf GP). I think the syntheses tool can'
> >recognise some part in my design and form it so, that clock some FF
> >with the gated signal. But I cant find where.
> >
> >THE QUESTION: How I can find out where the Alliance 2.1i found the
non-
> >dedicated resources(which signal is such clock)?
>
> Wow. I had the exact same problem. (scroll down in your newsreader;
maybe
> the articles haven't expired yet). turns out that it had to do with
crossing
> clock domains and such. One of the Xilinx apps guys sent me a note
with a
> shell script that parses ncdread's output so you can find out if there
> really is a problem.
>
> In FPGA Editor, you can highlight your clock nets and print out the
chip. I
> plotted mine onto E-size paper. Unfortunately, FPGA Editor only
prints out
> in gray-scale, so that fancy-shmancy HP DesignJet wasn't all that
helpful.
>
> --
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "Money is property; it is not speech."
> -- Justice John Paul Stevens
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21420
Subject: Re: Actel Design with A42MX36 Help
From: Andrew batchelor <andrew.batchelor@gecm.com>
Date: Wed, 22 Mar 2000 13:15:23 +0000
Links: << >>  << T >>  << A >>
> Thanks all for your Help,

 Well as requested here is a little more information about the logic
functions. I have generated a 2K dual port ram with the part by using a
mutliplexor to sort out what data goes where(for the write cycle). On the
input to the address lines there is a latch which will run up to 55 MHz no
problem. The problem comes when I route the tracks form the latch to the
rams. They have according to the data book a set-up time of about 2.3ns, and
the fastest I can get my signal to settle is about 16-17 ns. When I look at
the actual timings then the static timing analysis tools includes set-up
time but not the same as those in the data book :-(  Very Strange. I am
fairly convinced that I am getting a good fit, but it needs to be tweaked a
bit.

Andy Batchelor
BAE Systems
Rochester




Article: 21421
Subject: Re: Virtex DLL inoperability
From: Ray Andraka <randraka@ids.net>
Date: Wed, 22 Mar 2000 13:47:05 GMT
Links: << >>  << T >>  << A >>
Did you try the hotline?  The support engineers on the hotline may not be able to
find a solution, but at least they call you back and the problem gets on record
(eventually it even gets added to the on-line answers database).  To be fair, I
think Xilinx is quite a bit more forthcoming than most in the industry.  Who else
has such an extensive problems and solutions database posted on line for the
whole world to see?

Greg Alexander wrote:

> In article <20000320135410.12748.00002045@nso-fp.aol.com>, Winzker wrote:
> >Im Artikel <38D0E9E8.CAC88D25@NOSPAM.com>, David Gilchrist
> ><david.gilchrist@NOSPAM.com> schreibt:
> >
> >>It turned out to be a problem with the place and route tool (Service
> >>Pack 3 surprisingly enough).  The P & R tool was corrupting the bits
> >>during BitGen. When this was updated the problem magically disappeared.
> >
> >This gives me the opportunity to ask Xilinx to be more open with information
> >about problems. I'm a regular reader of the Xilinx web page, but when we
> >had problems with the DLL I didn't found any hint to this problem.
>
> I'd like to second that.  I've been browsing Xilinx's page for the past
> couple days and in 10 minutes of reading this newsgroup I've found a lot
> more information about Xilinx and their products than I did on their whole
> webpage (not to mention significant misinformation supplied by their
> webpage).  The whole thing stinks. :)

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21422
Subject: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN 2.1i ?
From: "Holger Kleinert" <Kleinert@ibpmt.com>
Date: Wed, 22 Mar 2000 14:54:39 +0100
Links: << >>  << T >>  << A >>
Hello All !

I actually make a design with a Xilinx Spartan 20XL device.
I use Foundation Express V2.1i.
The entire design is VHDL.

I want to implement the Global Set/Reset feature in VHDL
and referred to "Systhesis and Simulation Design Guide"  from Xilinx.
(downloadable from Xilinx WebSite)

Page 4-17 gives an example of implementig such a feature,
but this don't work with my tool.

At first I do not have the library "UNISIM" and
at second the STARTBUF component is not recognized..

If anyone has implemented GSR feature successfully in VHDL
please eMail me !!!!

Thank you !

Holger

Here is my listing:

-----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

library UNISIM;        -- This library can not be found and is not delivered
use UNISIM.all;

entity pci_target is
    port (
    [.....]
    nRST     : in    std_logic;
    [.....]
    );
end pci_target;

architecture pci_target_arch of pci_target is
  signal nRESET     : std_logic;

  component INV
    port (I: in  std_logic;
          O: out std_logic);
  end component;

  component STARTBUF
    port (GSRIN:  in  std_logic;
          GSROUT: out std_logic);
  end component;

begin
  U1 : INV       port map (I => nRST, O => nRESET);
  U2 : STARTBUF  port map (GSRIN =>nRESET, GSROUT =>RESET_INT);
end architecture;

----------------------------------------------------------------------------
---------
--
Holger Kleinert
Development / Support

IBP Instruments GmbH
Sutelstrasse 7a
D-30659 Hannover, Germany

http://www.ibpmt.com
Fon : +49-511-652286
Fax : +49-511-652283




Article: 21423
Subject: Re: Virtex DLL inoperability
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 22 Mar 2000 09:19:23 -0500
Links: << >>  << T >>  << A >>
Another reason to call the hot line is that they seem to be able to find
things in the data base that users can't. At least that has been my
experience. They seem to know the way to phrase a search. And I think
they have a bit higher speed access than the rest of us ;)


Ray Andraka wrote:
> 
> Did you try the hotline?  The support engineers on the hotline may not be able to
> find a solution, but at least they call you back and the problem gets on record
> (eventually it even gets added to the on-line answers database).  To be fair, I
> think Xilinx is quite a bit more forthcoming than most in the industry.  Who else
> has such an extensive problems and solutions database posted on line for the
> whole world to see?
> 
> Greg Alexander wrote:
> 
> > In article <20000320135410.12748.00002045@nso-fp.aol.com>, Winzker wrote:
> > >Im Artikel <38D0E9E8.CAC88D25@NOSPAM.com>, David Gilchrist
> > ><david.gilchrist@NOSPAM.com> schreibt:
> > >
> > >>It turned out to be a problem with the place and route tool (Service
> > >>Pack 3 surprisingly enough).  The P & R tool was corrupting the bits
> > >>during BitGen. When this was updated the problem magically disappeared.
> > >
> > >This gives me the opportunity to ask Xilinx to be more open with information
> > >about problems. I'm a regular reader of the Xilinx web page, but when we
> > >had problems with the DLL I didn't found any hint to this problem.
> >
> > I'd like to second that.  I've been browsing Xilinx's page for the past
> > couple days and in 10 minutes of reading this newsgroup I've found a lot
> > more information about Xilinx and their products than I did on their whole
> > webpage (not to mention significant misinformation supplied by their
> > webpage).  The whole thing stinks. :)
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21424
Subject: Re: Actel Design with A42MX36 Help
From: Rickman <spamgoeshere4@yahoo.com>
Date: Wed, 22 Mar 2000 09:23:04 -0500
Links: << >>  << T >>  << A >>
Andrew batchelor wrote:
> 
> > Thanks all for your Help,
> 
>  Well as requested here is a little more information about the logic
> functions. I have generated a 2K dual port ram with the part by using a
> mutliplexor to sort out what data goes where(for the write cycle). On the
> input to the address lines there is a latch which will run up to 55 MHz no
> problem. The problem comes when I route the tracks form the latch to the
> rams. They have according to the data book a set-up time of about 2.3ns, and
> the fastest I can get my signal to settle is about 16-17 ns. When I look at
> the actual timings then the static timing analysis tools includes set-up
> time but not the same as those in the data book :-(  Very Strange. I am
> fairly convinced that I am getting a good fit, but it needs to be tweaked a
> bit.
> 
> Andy Batchelor
> BAE Systems
> Rochester

You should try to duplicate the registers you are using for the address.
You may be able to get away with two sets. This will cut down on the
routing length and therefore the delay. If two is not enough, you can
try three or four sets of registers. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com


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