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Messages from 31825

Article: 31825
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Article: 31826
Subject: Re: one state machine
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Wed, 6 Jun 2001 13:21:50 -0400
Links: << >>  << T >>  << A >>
> > How do you know?  Do you go in and check with FPGA editor?
>
> You can do that. But a quick comparison can be made with the usage
> report (FFs, LUTs ...)

Huh?  What are you comparing it TO?

> >
> > What has happened is now that the parts are so much faster, just like
the
> > x86 CPUs, one can get design implementations that are not very optimal,
but
> > meet timing.  The parts are also so much larger, so taking up more
resources
> > using HDLs to implement a function, isn't such a big deal.
>
> HDL software isnt THAT bad. Sure, a pro can always get better results
> than a "stupid" compiler but for what efford??
> Finetuning by hand is required only for lets say 10% of all designs. I
> think its like in software business. 90% of computation time is spent in
> 10% of the code. So optimize the 10%.

Absolutely correct.  If you can use larger, faster parts, and the project
isn't cost sensitive, then any tool that you think is best for you, will
probably work.

> > Er, I have been using HDLs since they first came out...I know them quite
> > well, and have done probably hundreds of thousands of lines of ASIC,
FPGA
> > and simulation code in HDL.  That has nothing to do with the actual
issues
> > that the tools have.
>
> What kind of HDL??

Verilog and VHDL, Synplicity, FPGA Express, Synopsys...to name a few...




Article: 31827
Subject: Re: one state machine
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Wed, 6 Jun 2001 13:29:18 -0400
Links: << >>  << T >>  << A >>
> > So jump in and get to know HDLs. You may even like it once you learn the
> > flow.
>
> 100% ACK.

Actually, I find the best design flow to use schematics for the data paths
(since that's what typically gets floorplanned the most), and HDL for the
random logic and state machines.  When the HDLs don't make timing, or are to
obese, I then convert them to schematics.




Article: 31828
Subject: Re: one state machine
From: "Erik Widding" <widding@birger.com>
Date: Wed, 06 Jun 2001 17:51:05 GMT
Links: << >>  << T >>  << A >>
"Austin Franklin" <austin@dar54kroom.com> wrote in message
news:9flori$mqd$1@slb7.atl.mindspring.net...
> That's wrong.  I've been doing BOTH schematics and HDL for over a decade
for
> ASIC and FPGA designs.  I know HDLs and the associated tools quite well.
> HDL tools STILL can't give you what a schematic can, unless you use the
HDL
> as a netlister.
>
> There certainly are circumstances where the compromises that HDLs pose
don't
> interfere with the design criteria.  There is nothing wrong, per se, with
> HDLs, it's just the right tool for the right job, and HDLs aren't always
the
> right tool.

My $0.02:

Most projects have places where an HDL is the most efficient mode of design
entry, as well as places where the schematics are most appropriate.  I think
this is why "mixed-entry" tools are becoming more popular.

State-diagram editors make creating state-machines much easier than using
schematics or language.

Schematics are clearly the easiest way to understand complex data-paths.

HDLs are very useful, when schematics prove to obscure the intentions of the
implementor, i.e. complex if-then-else constructs.

Use what works best for how your mind works.  I think in pictures.  Some
times it is easier to represent those pictures with diagrams, and sometimes
it is easier to represent those pictures with language.  It is just
important to make sure that whatever entry methodology that is used produces
the same result as if one were to map the design to the individual logic
elements himself.

With a good graphical/mixed-entry tool (and there are many to choose from,
the now defunct Escalade DesignBook is still my favorite) one can tag the
pictures with attributes in the exact same way he tags his HDL, so the
synthesis and P&R tools do what you want.

IMHO design entry method is about three things:
    1. Ease of initial design.
    2. Absolute control over all stages of the process (i.e. being able to
force the result that you desire, without contradicting #1).
    3. Cost of documenting and maintaining the design.



Regards,
Erik Widding.

--
Birger Engineering, Inc.  --------------------------------  781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180  -------  http://www.birger.com




Article: 31829
Subject: Re: Xilinx Configuration Bitstream
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 6 Jun 2001 18:03:49 GMT
Links: << >>  << T >>  << A >>
"Austin Franklin" <austin@dar54kroom.com> writes:

(snip)

>The only people who need the bitstream are the people developing the back
>end tools, NOT the design entry tools.

I was once working on a project that would have needed to know
some of the bits.  Most of the design was static, but some constants
had to be changed before the data was loaded.  Xilinx will tell you
where the LUT bits are, at least in the 4000 series.  (So you know
which bits to ignore when you read the data out again.)

Mostly it was loading the values for ROM compiled into the design,
in a systolic array where each chip had different values.
There are probably other projects that need similar information.

-- glen

Article: 31830
Subject: Re: Xilinx Configuration Bitstream
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 06 Jun 2001 11:17:02 -0700
Links: << >>  << T >>  << A >>
In Virtex ( and its derivatives ) you can load any LUT "sideways" by using the
shift-register function SRL16. So you can change any LUT content on-the-fly
without reconfiguring, and without interfering with all its inputs.

Peter Alfke
=================================

glen herrmannsfeldt wrote:

> "Austin Franklin" <austin@dar54kroom.com> writes:
>
> (snip)
>
> >The only people who need the bitstream are the people developing the back
> >end tools, NOT the design entry tools.
>
> I was once working on a project that would have needed to know
> some of the bits.  Most of the design was static, but some constants
> had to be changed before the data was loaded.  Xilinx will tell you
> where the LUT bits are, at least in the 4000 series.  (So you know
> which bits to ignore when you read the data out again.)
>
> Mostly it was loading the values for ROM compiled into the design,
> in a systolic array where each chip had different values.
> There are probably other projects that need similar information.
>
> -- glen


Article: 31831
Subject: Re: Help in FIFO design
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Wed, 06 Jun 2001 12:21:24 -0600
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> Even $2.50 is significant in some silicon sectors.
> 
> 8032, romless 8 bit uC, are available for about 60c, 40/44 pins, and
> I think Z80's are still used, for under $2

The point here is there is really no "middle class"
in computer chips and design.{I have a "middle class" PC and I need to upgrade
:-( }
You have the "peanut" systems for $.25 with 1 chip
You have the Elephant stuff for $2500 with the latest design. While there has
been
new designs developed we still have the crummy cpu's cause 
the are cheap.I don't expect  any new features or other designs
from FPGA chips because they don't cut the mustard for any
designs other than simple RISC.
Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk
Updated - Now with schematics.

Article: 31832
Subject: Re: Help in FIFO design
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 6 Jun 2001 18:22:21 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <peter.alfke@xilinx.com> writes:

>Austin, let' not mix up hardware and software.
>I am sure that the computer industry used FIFOs and LIFO stacks in 
>software, but there were no semiconductor memories around before 1969.
>It started then with some puny 64-bit memories, and the ILLIAC used 
>the first large arrays of (puny) bipolar memories, but otherwise it 
>was a mag-core world.  Intel was founded in the summer of 1969, 
>(I joined Fairchild the day Bob Noyce left, no correlation! ) 
and their first product was an n-channel MOS memory and
>(I think ) also a bipolar memory. All way below 1024 bits.

I believe that IBM claims the first semiconductor computer memory
as either the protection keys in the 360/91 or the cache in the
360/85, both I believe before 1969.  They may have been a lot
smaller than 64bit/chip, though, maybe 4bit/chip.  Neither were
a FIFO.

There were buffer memories before FIFO, where they were loaded
(FI) and then read out (FO) but not both at the same time.
A card reader would read a card to a small core array, then read
it out one character at a time.  It would not read the next card
until it was completely empty.  I beleive that the FIFO's peter
is writing about have the ability to read and write at the same
time, or at least interleave read and write operations.

There are some very good books on the history of computers.  If
you read some you might be surprised how much they did with how
little, not so long ago.

-- glen

Article: 31833
Subject: Re: Help in FIFO design
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 06 Jun 2001 11:53:31 -0700
Links: << >>  << T >>  << A >>

glen herrmannsfeldt wrote:

> There were buffer memories before FIFO, where they were loaded
> (FI) and then read out (FO) but not both at the same time.
> A card reader would read a card to a small core array, then read
> it out one character at a time.  It would not read the next card
> until it was completely empty.  I beleive that the FIFO's peter
> is writing about have the ability to read and write at the same
> time, or at least interleave read and write operations.

Yes, simultaneous asynchronous write and read.
To be precise, the 3341 FIFO was really a specialized shift register, where
4-bit parallel data was shifted in and then, on its own, "bubbled" down the
shift register until it lined up behind the last remaining entry ( or at the
output). The whole thing was a "controlled and distributed race condition",
where each 4-bit location made an asynchronous decision to transfer to the
downstream neighbor and after that, asynchronously, signal its emptiness to the
upstream neighbor. Distributed handshake, no common clock at all.
30 years later, I can still draw you the schematic... Maybe that's where my
infatuation with tricky asynchronous circuits got started.

Peter Alfke

>


Article: 31834
Subject: Re: one state machine
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 06 Jun 2001 21:29:44 +0200
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:
> 
> I can agree with Falk, but my interests may be special.
> I am creating tiny, very tight-knit designs that squeeze the last fractional
> nanosecond ( or best density ) out of a chip.
> I know the architecture, its possibilities and limitations, and I already see
> the one and only interconnect scheme that gives me my 1 GHz counter, or my 250

Hey Peter, when will we see you 1 GHz frequency counter in Virtex II???
Are the ICs still not fast enought??
Tried cheating with cold spray ?? ;-)) (As you told us, the ICs are as
twice as fast at -40C compared to 85C, were the spec says something
about 850  MHz toggle rate . . . .;-))

> 
> I want an HDL dialect subset that allows me to dictate connectivity to the last
> iota, but do it in an ASCII format that's easier to communicate and to integrate

Hmm, looks like direct instanmciating of architecture components. OK,
this doesnt solve the P&R problem.
But there is still the FPGA editor ;-)

-- 
MFG
Falk



Article: 31835
Subject: Re: one state machine
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 06 Jun 2001 21:37:37 +0200
Links: << >>  << T >>  << A >>
Austin Franklin schrieb:
> 
> > > How do you know?  Do you go in and check with FPGA editor?
> >
> > You can do that. But a quick comparison can be made with the usage
> > report (FFs, LUTs ...)
> 
> Huh?  What are you comparing it TO?

To the result of the old version. As many noticed, the was sometime a
big difference in the design size when Xilinx changed from 2.1 to 3.1,
but with the right settings of the tools, you got the good old size.
Yes, this is not so nice, but as I said, we dont live in a perfect
world.
Even with Xilinx ;-)

> > 10% of the code. So optimize the 10%.
> 
> Absolutely correct.  If you can use larger, faster parts, and the project
> isn't cost sensitive, then any tool that you think is best for you, will
> probably work.

Hmmm, I think if you know your compiler really good (some kind of
intimate relationship ;-) then you can also get good (dense, fast)
results for cost/speed sensitve designs. Lets say 80% of the speed, Ray
Andraka would achieve with finetuning by hand ;-))

-- 
MFG
Falk



Article: 31836
Subject: Re: one state machine
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 06 Jun 2001 21:42:27 +0200
Links: << >>  << T >>  << A >>
Austin Franklin schrieb:
> 
> > > So jump in and get to know HDLs. You may even like it once you learn the
> > > flow.
> >
> > 100% ACK.
> 
> Actually, I find the best design flow to use schematics for the data paths
> (since that's what typically gets floorplanned the most), and HDL for the
> random logic and state machines.  When the HDLs don't make timing, or are to
> obese, I then convert them to schematics.

Hmm. I think we all agree that the designer needs a block diagram on
paper/document for documentation AND in his head. Schematics naturally
supports this block diagramms for free. I dont use schematics, just use
a generic tool to draw the block diagramm of my circuit, the details are
covered with comments in the VHDL code.

-- 
MFG
Falk



Article: 31837
Subject: Re: Help in FIFO design
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 06 Jun 2001 12:48:00 -0700
Links: << >>  << T >>  << A >>
I wrote:
> The PDP-1 doesn't contain any FIFOs.

"Austin Franklin" <austin@dar54kroom.com> writes:
> How do you know that?  Do you have the schematics for the entire PDP-1
> system and the peripherals?

As a matter of fact, I have seen PDP-1 schematics, and those of the most
of the standard peripherals.  It's fairly likely that I'll be involved
in a PDP-1 restoration project in the near future.

> Just because it isn't labeled "FIFO" doesn't mean it isn't performing
> a FIFO function.

To be a FIFO, it needs to have memory with input and output pointers, or
some sort of fall-through chain of latches.  The PDP-1 has neither.
Core memory was expensive, and much of the expense was the overhead, not
the cores.  Thus it did not make economic sense to have small core
assemblies (with or without counters) for individual peripherals.
Instead they used "cycle break", which today is called DMA.  The buffers
were in the main memory.  They did not act as fifos; rather a complete
"record" was transferred, and an interrupt generated.

Low-speed devices used interrupts or programmed I/O.  Again, no FIFOs
present.

I wrote:
> And yet after he clarified that he meant "semiconductor industry", you
> continued to try to refute his claim.

"Austin Franklin" <austin@dar54kroom.com> writes:
> Er, no.  As I said, go back and read the thread.  I've said a number of
> times, I am not, and did not, refute the claim that it was the first
> available integrated circuit  FIFO or how ever you want to qualify it.
> Others opined that it was the first semiconductor FIFO, which is what I
> continued to refute.  Any digital designs done since 1960 would be made from
> semiconductors.

This is getting really stupid.  Yes, you *could* use discrete
transistors, or tubes, or nand gates, to make a FIFO.  You could use
gears, ratchets, cams, etc. to make a mechanical FIFO.  You could use
carbon atoms to make a nanotech FIFO.  This is all irrelevant.  The fact
that it was possible does not indicate that ANYONE had offered a FIFO as
a product.

Article: 31838
Subject: Re: one state machine
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Wed, 6 Jun 2001 15:49:43 -0400
Links: << >>  << T >>  << A >>
> My $0.02:

Hell, that was very well put, and at least worth a nickel!

Must be our Right Coast thinking...;-)

> Most projects have places where an HDL is the most efficient mode of
design
> entry, as well as places where the schematics are most appropriate.  I
think
> this is why "mixed-entry" tools are becoming more popular.

Becoming?  I guess I've just always done it what way!




Article: 31839
Subject: Re: one state machine
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 06 Jun 2001 22:04:30 +0200
Links: << >>  << T >>  << A >>
Austin Franklin schrieb:
> 
> >
> > Here we go. Schematic is IMHO just practical for simple designs, but
> > when complexity rises, you are lost with schematics.
> 
> Absolutely untrue, if you know how to use the tool.  In fact, one of the
> most complex and fastest CPUs ever made, and its support chips, were done in
> schematic, simply because HDL tools could not do the job.

What CPU?
When was it designed?

 
>  Sure, it takes it
> > time to get into VHDL (or Verilog) but it is not THAT hard. And once in,
> > you will NEVER return to schematics, because HDL is much more powerful,
> > easier to use and is a much different way of designing digital logic.
> 
> That's wrong.  I've been doing BOTH schematics and HDL for over a decade for
> ASIC and FPGA designs.  I know HDLs and the associated tools quite well.
> HDL tools STILL can't give you what a schematic can, unless you use the HDL
> as a netlister.

Hmm, I dont get your point. What do you mean with that?

Ok, to give an example for my point of view.

Some time ago, a friend of mine called me for help on his digital
project. He wanted to build a nonlinear counter in a MACH device. He
spent MUCH time drawing the schematics for the counter (he made it from
bare FFs Uhhhh) some decoding logic, MUX ....

It didnt work, the clock was gated by a MUX and some other problem. So I
tried to redesign it from the very beginning. We went to the lab and
started changing the old schematic. Afer a while I was pissed off,
droped the schematic, got to ABEl and did the thing within 10 minutes.

To make it clear, you CAN do this also in schematics. You DONT have to
build yout own counter, ther are many counter modules in the libraries.
yes. But my point is this.
I want to describe the behavior of the circuit in a more abtract way,
not down to gates an FFs. When I need decoding logic, I just write some
case/If statements, the optimization is done by the compiler, which is
1000000 times faster and saver than doing the decoding by hand.

Example:

SIGNAL CNT: std_logic_vector(7 downto 0);

....

-- BAD schematic style

decode<= cnt(7) and NOT cnt(6) and cnt(5) and cnt(4) and cnt(3) and NOT
cnt(2) and cnt(1) and cnt(0);

-- decode is 1 when cnt=187 otherwise 0
-- how would you do such a decoder in schematic?? Use a comparator? Draw
all the wires to 1 and 0. To do so, you have to convert 187 into binary
(yes, this is easy with a pocket calculator, but allmost UNREADABLE in
the schamatic)

-- GOOD HDL style

decode<='1' when cnt=187 else '0';

-- This is very easy to read and to maintain, isnt it?? And it will be
perfectly optimized (I KNOW, some tools will not do fency tricks with
the carry chain for this comparator)
 
> There certainly are circumstances where the compromises that HDLs pose don't
> interfere with the design criteria.  There is nothing wrong, per se, with
> HDLs, it's just the right tool for the right job, and HDLs aren't always the
> right tool.

Hmmm?? Maybe if digital design is just a small part of your work and you
need just some simple decoders, registers, then schematics is much
easier, intuitive, but if you are and allmost full-time digital designer
on larger (not just giant) projects, you schould drop schematics
quickly, I think.

-- 
MFG
Falk



Article: 31840
Subject: Re: Xilinx Configuration Bitstream
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 06 Jun 2001 22:06:51 +0200
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:
> 
> In Virtex ( and its derivatives ) you can load any LUT "sideways" by using the
> shift-register function SRL16. So you can change any LUT content on-the-fly
> without reconfiguring, and without interfering with all its inputs.

Yes, but what can you do when you would like to add a series number in
your FPGA bitstream?
Compile every design with a new number?? No.

-- 
MFG
Falk



Article: 31841
Subject: ASIC vs FPGA designer
From: hristostev@yahoo.com (hristo)
Date: 6 Jun 2001 13:49:32 -0700
Links: << >>  << T >>  << A >>
hey,

what a hardware designer should put in his mind(as differences and
performance criterias) once he targets ASIC or FPGA ?

H.S

Article: 31842
Subject: Re: one state machine
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 06 Jun 2001 14:19:41 -0700
Links: << >>  << T >>  << A >>

Falk Brunner wrote:

> Hey Peter, when will we see you 1 GHz frequency counter in Virtex II???
> Are the ICs still not fast enought??

My "worst-case-1 GHz-ambition" ran into a problem, since Virtex-II has no direct
connect from Q back to the LUT or any other inverter input, and 800 MHz was not
acceptable to me. Then I found the solution: The DCM has an optional divide-by-two
input flip-flop, and that little devil runs well beyond 1 GHz. So I can come in with
a global clock, prescale by 2, and the rest of the counter should be easy.
Except I got ambitious and want to modify the counter such that it can count low
frequencies, say 1 kHz, with 6 digit accuracy (in one second, not 15 minutes), by
automatically switching to period measurement. Conceptually it's done, but not yet
implemented. "The better is always the enemy of the good".

No cheating with cold spray here, I leave that to the universities. :-)
Gruß
Peter



Article: 31843
Subject: Xilinx RapidIO?
From: Petter Gustad <spam@gustad.com>
Date: 06 Jun 2001 23:25:02 +0200
Links: << >>  << T >>  << A >>

I noticed that Xilinx announced RapidIO support on their Web site. Is
this simply that they support LVDS IO compatible with RapidIO, or is
it a core which supports the entire RapidIO physical layer interface?
If it's the latter, how does the interface to this core look like?

Thanks
Petter

-- 
________________________________________________________________________
Petter Gustad            8'h2B | ~8'h2B            http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}

Article: 31844
Subject: Re: Help in FIFO design
From: "Austin Franklin" <austin@dar54kroom.com>
Date: Wed, 6 Jun 2001 17:37:20 -0400
Links: << >>  << T >>  << A >>
> It's fairly likely that I'll be involved
> in a PDP-1 restoration project in the near future.

Where?

> > Just because it isn't labeled "FIFO" doesn't mean it isn't performing
> > a FIFO function.
>
> To be a FIFO, it needs to have memory with input and output pointers, or
> some sort of fall-through chain of latches.

Technically, two back to back flops IS a FIFO.  "Pointers" and "flags" are
not required to be a FIFO.

> > And yet after he clarified that he meant "semiconductor industry", you
> > continued to try to refute his claim.
>
> "Austin Franklin" <austin@dar54kroom.com> writes:
> > Er, no.  As I said, go back and read the thread.  I've said a number of
> > times, I am not, and did not, refute the claim that it was the first
> > available integrated circuit  FIFO or how ever you want to qualify it.
> > Others opined that it was the first semiconductor FIFO, which is what I
> > continued to refute.  Any digital designs done since 1960 would be made
from
> > semiconductors.
>
> This is getting really stupid.

You're right!

>  Yes, you *could* use discrete
> transistors, or tubes, or nand gates, to make a FIFO.  You could use
> gears, ratchets, cams, etc. to make a mechanical FIFO.  You could use
> carbon atoms to make a nanotech FIFO.  This is all irrelevant.  The fact
> that it was possible does not indicate that ANYONE had offered a FIFO as
> a product.

Again, you aren't reading what was said.  I NEVER said anyone offered a FIFO
as a product prior to 1971.  I said FIFOs were used long before 1971,
period.  Argue against what I DID say, not what I DIDN'T!




Article: 31845
Subject: Re: Help in FIFO design
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Wed, 06 Jun 2001 14:54:05 -0700
Links: << >>  << T >>  << A >>

You are all just jealous because I am the inventor of the
world famous 8-way superscalar D flip-flop.  Unfortunately,
I was beaten to market by the 74377.  Now, I am largely
forgotten, and much abused.

Shed a tear for me...
Eric

Eric Smith wrote:
> This is getting really stupid.  Yes, you *could* use discrete
> transistors, or tubes, or nand gates, to make a FIFO.  You could use
> gears, ratchets, cams, etc. to make a mechanical FIFO.  You could use
> carbon atoms to make a nanotech FIFO.  This is all irrelevant.  The fact
> that it was possible does not indicate that ANYONE had offered a FIFO as
> a product.

Article: 31846
Subject: Re: Help in FIFO design
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 06 Jun 2001 14:55:19 -0700
Links: << >>  << T >>  << A >>
"Austin Franklin" <austin@dar54kroom.com> writes:
> Technically, two back to back flops IS a FIFO.  "Pointers" and "flags" are
> not required to be a FIFO.

By themselves, no.  It takes some specific logic to make them behave as
a FIFO.  Counters are one way of doing it, but there are certainly others.

Article: 31847
Subject: Re: Help in FIFO design
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 06 Jun 2001 15:03:07 -0700
Links: << >>  << T >>  << A >>
"Austin Franklin" <austin@dar54kroom.com> writes:
> Again, you aren't reading what was said.  I NEVER said anyone offered a FIFO
> as a product prior to 1971.  I said FIFOs were used long before 1971,
> period.  Argue against what I DID say, not what I DIDN'T!

The discussion was started because Peter claimed to have developed the
industry's first FIFO.  He later clarified that he meant semiconductor
industry.

If people built FIFOs out of transistors, NAND gates, or whatever
before the Fairchild part, I don't see how that qualifies as a
"semiconductor industry FIFO".

I could take a big pile of transistors and make a machine to play Royal
Fizzbin (sp?).  But even if it was the first machine made out of
semiconductors that played Royal Fizzbin, I don't think any sensible
person would then say that it was the semiconductor industry's first
Royal Fizzbin machine, because it was NOT developed by the semiconductor
industry, it just happened to use their parts.

The first automobile probably was assembled with at least a few nuts and
bolts, but wasn't called "the nut and bolt industry's first
automobile".

Article: 31848
Subject: FPGA / starterkit / VHDL
From: "Michael Zirngibl" <greenland@vr-web.de>
Date: Thu, 7 Jun 2001 00:05:44 +0200
Links: << >>  << T >>  << A >>
Is there a cheap & available FPGA starterkit
that comes with VHDL software ?

Michael



Article: 31849
Subject: Re: Xilinx Configuration Bitstream
From: Neil Franklin <neil@franklin.ch.remove>
Date: 07 Jun 2001 00:16:47 +0200
Links: << >>  << T >>  << A >>
Falk Brunner <Falk.Brunner@gmx.de> writes:

> Yes, but what can you do when you would like to add a series number in
> your FPGA bitstream?
> Compile every design with a new number?? No.

Use JBits to make an serial number modification tool.

That is an _very_easy_ thing to do.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery



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